Ship Fase B slices: hierarchy, derating bands, timing, PI, ESD/return.

ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.
This commit is contained in:
2026-09-20 09:35:04 +02:00
parent facbaa2305
commit 342792df2d
16 changed files with 1259 additions and 27 deletions
+11
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@@ -2,6 +2,17 @@
What's new in Periscope.
## 2.33.0 — 2026-09-20 — Fase B: hierarchy, derating bands, timing, PI, ESD/return
Usable slices (not a platform): component→pin→net→block inventory, capacitor PASS/MARGIN/RISK from Vop/Vrated, RC/strap timing only with numbers, local vs bulk PI, ESD and HS return as REVIEW.
- [Fixed] `complete_finding` clamps ERROR unless `finding_class=RULE` and `provenance=MANDATORY` (LLM REVIEW cannot stay ERROR).
- [New] `hierarchy.json` + `PE-HIER-001` dangling IC pins.
- [New] Derating table `stress` PASS/MARGIN/RISK; findings `PE-DRT-001/002/003`.
- [New] `PE-TIM-001/002` skip without R/C and t_reset or Vih/Vil.
- [New] `PE-PI-001/002` local vs bulk; distance only with `layout_rules` mm.
- [New] `PE-ESD-001`, `PE-RET-001` are REVIEW, never RULE ERROR.
## 2.32.1 — 2026-09-20 — PCB Action on card + parsed geometry in AI context
Finding cards always show an **Action.** sentence (`action`, else `recommendation`, else a default). PCB AI context now includes vias under the footprint, copper thickness, nearby trace widths, courtyard, and keepout polygons from `.kicad_pcb`.
@@ -943,6 +943,7 @@ function DeratingTable({
<th className="pb-2 pr-4 font-medium">Value</th>
<th className="pb-2 pr-4 font-medium">C_eff</th>
<th className="pb-2 pr-4 font-medium">Type</th>
<th className="pb-2 pr-4 font-medium">Engine</th>
<th className="pb-2 pr-4 font-medium">Net+</th>
<th className="pb-2 pr-4 font-medium">Net</th>
<th className="pb-2 pr-4 font-medium text-right">Rated V</th>
@@ -1003,6 +1004,15 @@ function DeratingTable({
<span className="text-muted-foreground"></span>
)}
</td>
<td className="py-2 pr-4 text-xs">
{row.stress && row.stress !== "UNKNOWN" ? (
<Badge variant="outline" className="text-[10px] px-1.5 py-0">
{row.stress}
</Badge>
) : (
<span className="text-muted-foreground"></span>
)}
</td>
<td className="py-2 pr-4 font-mono text-xs">
{row.net_plus ?? <span className="text-muted-foreground"></span>}
</td>
+20 -2
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@@ -11,6 +11,10 @@ export function isLayoutFinding(f: {
id.startsWith("PCB-") ||
f.source === "pcb_review" ||
f.source === "pcb_power_thermal" ||
f.source === "hierarchy_check" ||
f.source === "timing_check" ||
f.source === "pi_check" ||
f.source === "esd_return_check" ||
rid.startsWith("PE-PLC") ||
rid.startsWith("PE-LAY") ||
rid.startsWith("PE-SI") ||
@@ -19,7 +23,12 @@ export function isLayoutFinding(f: {
rid.startsWith("PE-THM") ||
rid.startsWith("PE-VIA") ||
rid.startsWith("PE-KEL") ||
rid.startsWith("PE-STCH")
rid.startsWith("PE-STCH") ||
rid.startsWith("PE-HIER") ||
rid.startsWith("PE-TIM") ||
rid.startsWith("PE-PI") ||
rid.startsWith("PE-ESD") ||
rid.startsWith("PE-RET")
);
}
@@ -31,10 +40,19 @@ export function isPcbExamFinding(f: {
return (
f.source === "pcb_review" ||
f.source === "pcb_power_thermal" ||
f.source === "hierarchy_check" ||
f.source === "timing_check" ||
f.source === "pi_check" ||
f.source === "esd_return_check" ||
rid.startsWith("PE-PWR") ||
rid.startsWith("PE-THM") ||
rid.startsWith("PE-VIA") ||
rid.startsWith("PE-KEL") ||
rid.startsWith("PE-STCH")
rid.startsWith("PE-STCH") ||
rid.startsWith("PE-HIER") ||
rid.startsWith("PE-TIM") ||
rid.startsWith("PE-PI") ||
rid.startsWith("PE-ESD") ||
rid.startsWith("PE-RET")
);
}
+1
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@@ -413,6 +413,7 @@ export interface DeratingRow {
c_eff_f?: number | null;
c_eff_formatted?: string | null;
dc_bias_model?: "stima" | null;
stress?: "PASS" | "MARGIN" | "RISK" | "UNKNOWN";
}
export interface DeratingSettings {