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Ship Fase B slices: hierarchy, derating bands, timing, PI, ESD/return.

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ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.
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michele
2026-09-20 09:35:04 +02:00
parent facbaa2305
commit 342792df2d
16 changed files with 1259 additions and 27 deletions
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docs/piano-pcb-review.md
+22 -4
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@@ -55,8 +55,14 @@ Mutex vs analisi e vs placement. SSE `pcb_*`. IDs `PCB-{ref}-{001}`. KiCad `/net
| PE-LAY-001…003 | pad/ref/hierarchy nets |
| PE-PLC-001…004 | `layout_rules` numerici |
| PE-SI-001 | `length_match` mm |
| PE-DRT-001 | Vop e Vrated |
| PE-PWR-001 | I_load + width; IPC solo con thickness e Tjmax |
| PE-DRT-001 | Vop e Vrated, Vop > Vr → RULE ERROR |
| PE-DRT-002 | 0.8 < Vop/Vr ≤ 1 → RISK MARGIN |
| PE-DRT-003 | Vop/Vr ≤ 0.8 → PASS summary INFO |
| PE-HIER-001 | pin IC senza net |
| PE-TIM-001/002 | RC / strap solo con numeri |
| PE-PI-001/002 | local vs bulk; mm solo da layout_rules |
| PE-ESD-001 / PE-RET-001 | REVIEW unless mandatory FACT |
| PE-VIA-001 | via count + I_load (INFO, no tabella inventata) |
| PE-THM-001 | P=I_load×drop, courtyard senza pour/via |
| PE-KEL-001 | sense/Kelvin pintable + ≥2 altri sul net |
@@ -70,10 +76,22 @@ AI PCB: skip IC senza pintable (`run schematic review first`).
## Fasi
**A — shipped (questa slice):** oggetto finding condiviso, clamp provenance/class, decisions, UI, libreria unica, geometria gated, net-slash.
**A — shipped:** oggetto finding condiviso, clamp provenance/class (**ERROR solo RULE+MANDATORY**), decisions, UI, libreria unica, geometria gated, net-slash, Action on card, geometria in contesto AI.
**B — pianificata (non finta):** gerarchia component→system; timing; energy/thermal solo con parametri; ratings; derating PASS/MARGIN/RISK; PI; SI oltre skew; return path oltre stitch INFO; ESD/EMI; thermal FEM; BOM↔PCB↔datasheet; SPOF come REVIEW.
**B — questa slice (shipped, gated):**
**C — fuori:** auto-place, write-back pcbnew, unire i job, sshd/keys.
| ID | Cosa | Gate |
| --- | --- | --- |
| Gerarchia | `hierarchy.json` component→pin→net→block | grafo (+ domains se `classify`) |
| PE-HIER-001 | pin IC senza net | FACT net='' |
| PE-DRT-001/002/003 | RISK / MARGIN / PASS | Vop **e** Vrated; niente % dielettrico inventato |
| PE-TIM-001/002 | RC reset / strap | R, C e t_reset o Vih/Vil numerici |
| PE-PI-001/002 | local vs bulk, I se noto | cap valorizzati; distanza solo con `max_distance_mm` |
| PE-ESD-001 | ESD connettore/USB | REVIEW se manca parte ESD |
| PE-RET-001 | return HS senza via GND | REVIEW, non ERROR |
**B — ancora aperta:** energy/thermal FEM; SI oltre skew mm; BOM↔PCB↔datasheet completo; SPOF; EMI oltre ESD REVIEW.
**C — fuori:** auto-place, write-back pcbnew, unire i job, sshd/keys, PinScope identity/fork.
Deploy: `ssh periscope` + `/root/periscope/scripts/update-periscope.sh`.