Ship Fase B slices: hierarchy, derating bands, timing, PI, ESD/return.

ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.

backend/periscopex/derating.py

@@ -95,6 +95,18 @@ def _dielectric_category(component_subtype: str | None, dielectric: str | None)
     return "ceramic"
 
 
+def _stress(op: float | None, rated: float | None) -> str:
+    """PASS / MARGIN / RISK from Vop vs Vrated. No invented dielectric %."""
+    if op is None or rated is None or rated <= 0:
+        return "UNKNOWN"
+    ratio = op / rated
+    if ratio > 1.0:
+        return "RISK"
+    if ratio > 0.8:
+        return "MARGIN"
+    return "PASS"
+
+
 def build_derating_table(graph: DesignGraph) -> list[dict]:
     """Build a capacitor voltage derating table from the design graph.
 
@@ -180,6 +192,7 @@ def build_derating_table(graph: DesignGraph) -> list[dict]:
             "c_eff_f": c_eff,
             "c_eff_formatted": c_eff_fmt,
             "dc_bias_model": "stima" if factor is not None else None,
+            "stress": _stress(op_voltage, rated_v),
         })
 
     rows.sort(key=lambda r: natural_sort_key(r["designator"]))