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Add remaining PCB analysis checks to run_pcb_checks (2.62.1).

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Phase B: stackup vs fab spec, via current with datasheet I (no IPC via
chart), ESD pad distance, USB-PD, PoE isolation voltage, antenna, and
PDN Z(f). Skip without evidence. Not DRC or FEM.
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michele
2026-09-21 20:49:21 +02:00
parent 69d5dd9313
commit 20733f0ec6
15 changed files with 776 additions and 6 deletions
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periscope/src/frontend/content/changelog.md
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What's new in Periscope.
## 2.62.1 — 2026-09-21 — PCB analysis remainder (Phase B)
Stackup vs fab spec, via current with datasheet I (no IPC via chart), ESD pad distance TVS–connector, USB-PD contract, PoE isolation voltage, antenna keepout/matching, PDN Z(f). Same pipeline and finding quality as 2.61.2 / 2.62.0. Skip if no evidence. Not DRC. Not FEM.
- [New] `PE-STK-001` board copper thickness vs sourced fab stackup (never 1 oz).
- [New] `PE-VIA-002` I + via count/drill FACT; IPC via ampacity is not applied.
- [New] `PE-ESD-002` TVS–connector **pad** distance (via ≠ pad); INFO if no mm.
- [New] `PE-PD-001` USB-PD only with a PD controller (not USB2 Rd).
- [New] `PE-POE-004` isolation voltage only from a sourced number.
- [New] `PE-ANT-001`/`002` antenna keepout and matching if an antenna exists.
- [New] `PE-PDN-001` Z(f) only with frequency-domain FACT; SI Z0 is not PDN.
## 2.62.0 — 2026-09-21 — HF lines/buses in PCB checks (Phase A)
USB / Eth / DDR / MIPI / PCIe / HDMI / LVDS / HF clock in `run_pcb_checks` at the same finding quality as 2.61.2. Pair integrity: stub (track only; via ≠ pad ≠ zone), reference-split under the line, BOM termination. CPU data/address/control and FPGA only if that device is on the graph. Skip if no evidence. Not DRC. Not FEM. Datasheet millimetres only; no invented Z/I.