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Ship remaining PCB plan slices: BOM chain, SPOF, EMI FACT, gated Tj.

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Package/pinout/ratings mismatches, SPOF as REVIEW, EMI only with a
datasheet quote, and Tj from copper+vias+θJA when every parameter exists.
Re-extract SI layout_rules from 1.12.0; ImpedenceFinder license stays UNKNOWN.
This commit is contained in:
michele
2026-09-20 12:29:27 +02:00
parent 65a91419a2
commit 1b3529501f
20 changed files with 1337 additions and 30 deletions
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frontend/content/changelog.md
+11 -1
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@@ -2,6 +2,16 @@
What's new in Periscope.
## 2.35.0 — 2026-09-20 — BOM↔PCB↔datasheet, SPOF, EMI FACT, gated Tj
Remaining Fase B slices except auto-place and thermal FEM / OpenEMS.
- [New] `PE-BOM-010`…`014` package / pinout / voltage / temp / current when BOM, PCB, and datasheet all have numbers.
- [New] `PE-SPOF-001` single regulator or shared crystal — REVIEW, never ERROR.
- [New] `PE-EMI-001` only if `layout_rules` quotes EMI/common-mode/ferrite/shield (not IEC 61000).
- [New] `PE-THM-002` Tj = Ta + P·θJA when P, θJA, copper area, and via count exist; else INSUFFICIENT.
- [Changed] Pintable skill `1.12.0`: SI+EMI kinds; empty SI on older extracts triggers schematic re-extract (`si_extract_needed.json` on PCB). ImpedenceFinder license remains UNKNOWN (no upstream LICENSE).
## 2.34.0 — 2026-09-20 — ImpedenceFinder SI checks (not a dump table)
USB/HDMI/PCIe/ETH/LVDS/DDR layout_rules (diff/SE Z, skew, max length, spacing, ref plane, vias, layer, return, series R) are compared to ImpedenceFinder + copper. One PASS/FAIL/MARGIN finding per requirement. I2C/GPIO/CC/REGN are not 50 Ω.
@@ -10,7 +20,7 @@ USB/HDMI/PCIe/ETH/LVDS/DDR layout_rules (diff/SE Z, skew, max length, spacing, r
- [Changed] `PE-SI-001` only on impedance-controlled buses matching the rule `net_class`.
- [Changed] extract-pintable `layout_rules` kinds for SI; `default_model_version` 1.11.0.
## 2.33.2 — 2026-09-20 — PCB complete UI, not a raw SSE error
A finished PCB exam no longer shows the raw watcher string `pcb_status=complete (terminal)`. The SSE hatch emits `pcb_complete`; the PCB page then opens `/report?domain=layout` (expand-on-click tree).
frontend/src/lib/layout-finding.ts
+14 -2
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@@ -15,6 +15,9 @@ export function isLayoutFinding(f: {
f.source === "timing_check" ||
f.source === "pi_check" ||
f.source === "esd_return_check" ||
f.source === "bom_pcb_check" ||
f.source === "spof_check" ||
f.source === "emi_check" ||
rid.startsWith("PE-PLC") ||
rid.startsWith("PE-LAY") ||
rid.startsWith("PE-SI") ||
@@ -28,7 +31,10 @@ export function isLayoutFinding(f: {
rid.startsWith("PE-TIM") ||
rid.startsWith("PE-PI") ||
rid.startsWith("PE-ESD") ||
rid.startsWith("PE-RET")
rid.startsWith("PE-RET") ||
rid.startsWith("PE-SPOF") ||
rid.startsWith("PE-EMI") ||
/^PE-BOM-01[0-4]$/.test(rid)
);
}
@@ -44,6 +50,9 @@ export function isPcbExamFinding(f: {
f.source === "timing_check" ||
f.source === "pi_check" ||
f.source === "esd_return_check" ||
f.source === "bom_pcb_check" ||
f.source === "spof_check" ||
f.source === "emi_check" ||
rid.startsWith("PE-PWR") ||
rid.startsWith("PE-THM") ||
rid.startsWith("PE-VIA") ||
@@ -53,6 +62,9 @@ export function isPcbExamFinding(f: {
rid.startsWith("PE-TIM") ||
rid.startsWith("PE-PI") ||
rid.startsWith("PE-ESD") ||
rid.startsWith("PE-RET")
rid.startsWith("PE-RET") ||
rid.startsWith("PE-SPOF") ||
rid.startsWith("PE-EMI") ||
/^PE-BOM-01[0-4]$/.test(rid)
);
}