Add MODE=pcb layout exam job with AI and deterministic checks.

Parallel pcb_status pipeline: parse board, classify domains/groups,
inventory traces, PE-LAY/PLC/SI/DRT checks, per-IC datasheet review.
Findings merge into the report UI. No auto-place or pcbnew write-back.

tests/test_placement_check.py

@@ -278,3 +278,14 @@ def test_keepout_without_courtyard_is_silent():
         _xtal_keepout_cons(),
         _x1_keepout_layout(net="GND", courtyard=False),
     ) == []
+
+
+def test_schema_deterministic_runner_omits_layout_checks():
+    """PCB placement/SI belong to MODE=pcb, not the schematic review seed."""
+    import inspect
+
+    from backend.services.validation import _run_deterministic_checks
+
+    src = inspect.getsource(_run_deterministic_checks)
+    assert "check_placement" not in src
+    assert "check_si" not in src