Add MODE=pcb layout exam job with AI and deterministic checks.

Parallel pcb_status pipeline: parse board, classify domains/groups,
inventory traces, PE-LAY/PLC/SI/DRT checks, per-IC datasheet review.
Findings merge into the report UI. No auto-place or pcbnew write-back.
This commit is contained in:
2026-09-19 22:54:17 +02:00
parent a2011dad91
commit 16c606ae3d
28 changed files with 1906 additions and 32 deletions
+3
View File
@@ -148,6 +148,9 @@ async def get_project(project_id: str, request: Request):
healed_pl = proj_svc.heal_if_placement_stuck(storage, owner_user_id, project_id)
if healed_pl is not None:
meta = healed_pl
healed_pcb = proj_svc.heal_if_pcb_stuck(storage, owner_user_id, project_id)
if healed_pcb is not None:
meta = healed_pcb
return meta.model_dump()