Gate PCB SI not_reviewed to board ICs, not the shared library.

Emmaforo listed 20 stale 1.5–1.7 MPNs (LAN8720A, W25Q, …) as
not reviewed while the four BOM ICs were already extracted and reviewed.
This commit is contained in:
2026-09-20 14:05:03 +02:00
parent 312057b6d3
commit 0a75e5971a
3 changed files with 103 additions and 23 deletions
+46
View File
@@ -80,6 +80,52 @@ def test_si_refresh_when_old_extract_has_only_decoupling():
)
def test_si_extract_needed_skips_board_ics_only_not_shared_library():
from backend.services.pcb_pipeline import si_extract_needed_skips
graph = DesignGraph(
components={
"U5": Component(
reference="U5", value="ESP32-C6-WROOM-1", footprint="",
component_type=ComponentType.IC, mpn="ESP32-C6-WROOM-1",
pins={"1": "EN"},
),
"J1": Component(
reference="J1", value="USB-C", footprint="",
component_type=ComponentType.CONNECTOR, mpn="TYPE-C-31-M-12",
pins={},
),
},
nets={},
)
fresh = ComponentConstraints(
mpn="ESP32-C6-WROOM-1",
model_version="1.13.0",
pintable=[Pin(number="1", name="EN")],
absolute_maximum_ratings=[],
rules=[],
layout_rules=[{"kind": "decoupling_proximity", "pin": "EN"}],
)
stale_lib = ComponentConstraints(
mpn="LAN8720A",
model_version="1.5.0",
pintable=[Pin(number="1", name="TXP")],
absolute_maximum_ratings=[],
rules=[],
layout_rules=[],
)
stale_board = fresh.model_copy(update={"model_version": "1.5.0", "layout_rules": []})
assert si_extract_needed_skips(
graph, {"ESP32-C6-WROOM-1": fresh, "LAN8720A": stale_lib}, "1.13.0",
) == []
skips = si_extract_needed_skips(
graph, {"ESP32-C6-WROOM-1": stale_board, "LAN8720A": stale_lib}, "1.13.0",
)
assert len(skips) == 1
assert skips[0]["designator"] == "U5"
assert "LAN8720A" not in skips[0]["designator"]
def test_package_family_mismatch_is_pe_bom_010():
from backend.periscopex.bom_pcb_check import check_bom_pcb_datasheet