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michele
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michele
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michele
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michele
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michele
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+16
@@ -0,0 +1,16 @@
|
||||
|
||||
# Local datasheets — not committed
|
||||
datasheets/
|
||||
|
||||
# KiCad generated / local files
|
||||
**/~*.lck
|
||||
**/*.lck
|
||||
**/_restore_backup_*/
|
||||
|
||||
# Generated reports / exports
|
||||
hardware/kicad/HubAudio/ERC.rpt
|
||||
hardware/kicad/HubAudio/ERC.txt
|
||||
hardware/kicad/HubAudio/*.asc
|
||||
hardware/kicad/HubAudio/*.csv
|
||||
hardware/kicad/HubAudio/export_project_*.csv
|
||||
|
||||
@@ -1,2 +1,151 @@
|
||||
# HubAudio# HubAudio
|
||||
# HubAudio
|
||||
|
||||
## Professional Embedded Audio Platform
|
||||
|
||||
HubAudio is a modular embedded audio platform designed around a clear separation of hardware domains:
|
||||
|
||||
- System control
|
||||
- Audio processing
|
||||
- Digital radio
|
||||
- Wireless audio
|
||||
- Clock management
|
||||
- Power management
|
||||
|
||||
The primary design objective is maintainability.
|
||||
|
||||
The architecture follows the principle:
|
||||
|
||||
> Code and hardware design must fit in the engineer's head.
|
||||
|
||||
Complexity is introduced only when it provides a measurable improvement in reliability, flexibility or performance.
|
||||
|
||||
---
|
||||
|
||||
# Project Goals
|
||||
|
||||
HubAudio is intended to provide:
|
||||
|
||||
- High quality digital audio routing
|
||||
- Multiple audio sources and destinations
|
||||
- Expandable DSP processing
|
||||
- Robust embedded operation
|
||||
- Professional PCB architecture
|
||||
- Long-term maintainability
|
||||
|
||||
---
|
||||
|
||||
# Core Architecture
|
||||
|
||||
## Main Domains
|
||||
|
||||
SYSTEM DOMAIN
|
||||
|
||||
ESP32-S3
|
||||
|
|
||||
Control / Network / UI
|
||||
|
|
||||
|
|
||||
AUDIO CONTROL BUS
|
||||
|
||||
|
||||
AUDIO DOMAIN
|
||||
|
||||
ADAU1467
|
||||
|
||||
+-------------+-------------+
|
||||
| | |
|
||||
I2S SPDIF Bluetooth
|
||||
| | |
|
||||
Si4684 IO Codec BT Module
|
||||
Radio
|
||||
|
||||
---
|
||||
|
||||
# Hardware Philosophy
|
||||
|
||||
The system is divided into independent domains:
|
||||
|
||||
## System Domain
|
||||
|
||||
Responsible for:
|
||||
|
||||
- Connectivity
|
||||
- User interface
|
||||
- Configuration
|
||||
- Network services
|
||||
- OTA updates
|
||||
|
||||
Main component:
|
||||
|
||||
- ESP32-S3
|
||||
|
||||
|
||||
## Audio Domain
|
||||
|
||||
Responsible for:
|
||||
|
||||
- Routing
|
||||
- DSP processing
|
||||
- Mixing
|
||||
- Sample rate management
|
||||
|
||||
Main component:
|
||||
|
||||
- Analog Devices ADAU1467
|
||||
|
||||
|
||||
## RF Domain
|
||||
|
||||
Responsible for:
|
||||
|
||||
- Digital radio reception
|
||||
- Wireless communication
|
||||
|
||||
|
||||
## Power Domain
|
||||
|
||||
Responsible for:
|
||||
|
||||
- Battery operation
|
||||
- USB power
|
||||
- Voltage regulation
|
||||
- Monitoring
|
||||
|
||||
|
||||
---
|
||||
|
||||
# Repository Structure
|
||||
|
||||
|
||||
HubAudio/
|
||||
|
||||
├── docs/
|
||||
│
|
||||
├── hardware/
|
||||
│
|
||||
├── firmware/
|
||||
│
|
||||
├── simulation/
|
||||
│
|
||||
├── research/
|
||||
│
|
||||
└── tools/
|
||||
|
||||
|
||||
---
|
||||
|
||||
# Design Rules
|
||||
|
||||
1. Prefer simple architectures.
|
||||
2. Avoid unnecessary abstraction.
|
||||
3. Separate noisy and sensitive domains.
|
||||
4. Document every architectural decision.
|
||||
5. Choose components for lifecycle, not only price.
|
||||
|
||||
---
|
||||
|
||||
# Status
|
||||
|
||||
Architecture phase.
|
||||
|
||||
Hardware implementation follows documented decisions.
|
||||
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@@ -37,13 +37,14 @@ The Audio Processor is responsible for:
|
||||
- audio clock generation
|
||||
- synchronization of external audio peripherals
|
||||
|
||||
The Audio Processor is considered the audio domain master.
|
||||
The Audio Processor is the sole timing and routing master of the Audio Domain.
|
||||
|
||||
The System Controller participates in the Audio Domain as a digital audio source. It does not act as the audio timing master or routing controller. Its role inside the audio domain is equivalent to other digital audio sources.
|
||||
|
||||
The System Controller has a dual role:
|
||||
|
||||
- audio source inside the Audio Domain
|
||||
system supervisor inside the Control Domain
|
||||
- system supervisor inside the Control Domain
|
||||
|
||||
It operates as system supervisor and is responsible for:
|
||||
|
||||
|
||||
@@ -23,7 +23,7 @@ audio transport interface.
|
||||
|
||||
## Decision
|
||||
|
||||
The SPI architecture is divided into independent functional domains.
|
||||
The SPI architecture is divided into independent control domains.
|
||||
|
||||
The System Controller operates as the master of the system control SPI bus.
|
||||
|
||||
@@ -88,8 +88,7 @@ commands exchanged on the external SPI control interface.
|
||||
|
||||
Internal RAM
|
||||
|
||||
The System Controller controls the initialization process but does not directly access
|
||||
the internal operational memory of the Radio Receiver.
|
||||
The System Controller supervises the Radio Receiver initialization process. Internal firmware loading remains under the responsibility of the Radio Receiver boot architecture.
|
||||
|
||||
## Consequences
|
||||
|
||||
|
||||
@@ -41,13 +41,15 @@ External audio devices operate as I2S slaves whenever supported.
|
||||
|
||||
## Audio Input Allocation
|
||||
|
||||
| Audio Processor Port | Device | Function |
|
||||
|| Audio Processor Input | Device | Function |
|
||||
|---|---|---|
|
||||
| SDATA_IN0 | System Controller | Network audio stream |
|
||||
| SDATA_IN1 | Radio Receiver | Radio audio |
|
||||
| SDATA_IN2 | DECODEC | Optical digital input |
|
||||
| SDATA_IN3 | Bluetooth RX | Wireless audio input |
|
||||
| SPDIFIN | Optical Interface | Optical digital audio input |
|
||||
| SDATA_IN2 | Bluetooth RX | Wireless audio input |
|
||||
|
||||
The ADAU1467 internal audio routing matrix allows any digital audio input
|
||||
to be routed to the DSP core, ASRCs, serial outputs or SPDIF output.
|
||||
|
||||
System Controller --------
|
||||
Radio Receiver ---------
|
||||
@@ -57,11 +59,13 @@ BT RX ---------/
|
||||
|
||||
## Audio Output Allocation
|
||||
|
||||
| Audio Processor Port | Device | Function |
|
||||
## Audio Output Allocation
|
||||
|
||||
| Audio Processor Output | Device | Function |
|
||||
|---|---|---|
|
||||
| SDATA_OUT0 | CODEC/DAC | Analog audio output |
|
||||
| SDATA_OUT1 | Bluetooth TX | Wireless audio output |
|
||||
| SDATA_OUT2 | ENCODEC | Optical digital output |
|
||||
| SPDIFOUT | Optical Interface | Optical digital audio output |
|
||||
| SDATA_OUT3 | Reserved | Future expansion |
|
||||
|
||||
Audio Processor
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
# ADR-004 – Power Domain Architecture
|
||||
|
||||
- **Status:** Accepted
|
||||
- **Date:** YYYY-MM-DD
|
||||
- **Date:** 2026-08-02
|
||||
|
||||
# Context
|
||||
|
||||
|
||||
@@ -0,0 +1,771 @@
|
||||
# DigiRadio — Clock Architecture and I²S Clock-Domain Implementation
|
||||
|
||||
**Document ID:** ARCH-CLOCK-001
|
||||
**Status:** Design Baseline
|
||||
**Revision:** 2.0
|
||||
**Date:** 2026-08-15
|
||||
**Scope:** ADAU1467, Si4684, ESP32-S31-WROOM3, TLV320AIC3104IRHBR, BT1035, S/PDIF
|
||||
|
||||
---
|
||||
|
||||
## 1. Purpose
|
||||
|
||||
This document defines the DigiRadio digital-audio clock architecture and the physical implementation rules for the I²S clock signals.
|
||||
|
||||
The architecture is based on the **ADAU1467** as the central DSP and audio-clock hub.
|
||||
|
||||
The design objectives are:
|
||||
|
||||
- one primary 12.288 MHz audio reference;
|
||||
- 48 kHz primary audio sample rate;
|
||||
- removal of the dedicated Si4684 crystal by supplying its external reference from the ADAU1467;
|
||||
- use of the TLV320AIC3104 as the analog audio codec;
|
||||
- independent BCLK/LRCLK pairs for the individual I²S interfaces;
|
||||
- no external BCLK/LRCLK splitter or "clock mixing" network;
|
||||
- explicit separation of ADAU1467 input and output clock domains;
|
||||
- use of ADAU1467 internal clock-domain architecture rather than electrically tying unrelated clock signals together.
|
||||
|
||||
This document is an **implementation document**: it defines how the clock architecture shall be translated into the KiCad schematic and PCB.
|
||||
|
||||
---
|
||||
|
||||
# 2. Architectural Principle
|
||||
|
||||
The fundamental design principle is:
|
||||
|
||||
> **Each external I²S peripheral receives its own BCLK/LRCLK pair from the corresponding ADAU1467 serial-port clock domain.**
|
||||
|
||||
The PCB shall **not electrically combine BCLK or LRCLK signals belonging to different serial ports**.
|
||||
|
||||
The ADAU1467 internally generates and manages the required audio clock domains.
|
||||
|
||||
Therefore, the PCB must not contain a global:
|
||||
|
||||
```text
|
||||
BCLK ─┬─ Device 1
|
||||
├─ Device 2
|
||||
├─ Device 3
|
||||
└─ Device 4
|
||||
|
||||
or:
|
||||
|
||||
|
||||
LRCLK ─┬─ Device 1
|
||||
├─ Device 2
|
||||
├─ Device 3
|
||||
└─ Device 4
|
||||
|
||||
unless a specific group of peripherals has deliberately been assigned to the same physical clock source and the electrical topology has been explicitly designed for that purpose.
|
||||
The default DigiRadio implementation is one BCLK/LRCLK pair per I²S interface.
|
||||
|
||||
3. Master Reference Clock
|
||||
3.1 Primary reference
|
||||
The DigiRadio primary audio reference is:
|
||||
|
||||
|
||||
12.288 MHz
|
||||
|
||||
generated by a passive crystal connected to the ADAU1467 oscillator/MCLK input.
|
||||
Architecture:
|
||||
|
||||
|
||||
12.288 MHz crystal
|
||||
│
|
||||
▼
|
||||
ADAU1467 MCLK/XTAL
|
||||
│
|
||||
▼
|
||||
PLL
|
||||
│
|
||||
▼
|
||||
Clock Generators
|
||||
│
|
||||
├── audio clock domains
|
||||
└── CLKOUT
|
||||
|
||||
The 12.288 MHz reference is appropriate for a 48 kHz audio system because:
|
||||
|
||||
|
||||
12.288 MHz / 256 = 48 kHz
|
||||
|
||||
|
||||
4. ADAU1467 Clock Architecture
|
||||
The ADAU1467 contains the clock-generation infrastructure required for a multi-peripheral audio system.
|
||||
The important architectural distinction is:
|
||||
|
||||
|
||||
ADAU1467 INPUT CLOCK DOMAINS
|
||||
≠
|
||||
ADAU1467 OUTPUT CLOCK DOMAINS
|
||||
|
||||
Even if two domains are configured to exactly the same nominal frequency, they are not to be treated as the same physical PCB clock net.
|
||||
The ADAU1467 provides multiple serial input and output ports and multiple clock domains, allowing different peripherals to be assigned independently.
|
||||
This is the reason a separate BCLK/LRCLK splitter IC is not required by the baseline architecture.
|
||||
|
||||
5. Primary Audio Rate
|
||||
The primary DigiRadio audio rate is:
|
||||
|
||||
|
||||
Fs = 48 kHz
|
||||
|
||||
For stereo I²S with 32-bit slots:
|
||||
|
||||
|
||||
BCLK = 48,000 × 32 × 2
|
||||
= 3,072,000 Hz
|
||||
= 3.072 MHz
|
||||
|
||||
Therefore the baseline values are:
|
||||
Signal
|
||||
Frequency
|
||||
Master reference
|
||||
12.288 MHz
|
||||
LRCLK / WCLK
|
||||
48 kHz
|
||||
BCLK
|
||||
3.072 MHz
|
||||
I²S slot width
|
||||
32 bit
|
||||
Channels
|
||||
2
|
||||
These values are the baseline. Individual devices must still be configured according to their own I²S timing and supported formats.
|
||||
|
||||
6. Global Clock Tree
|
||||
The logical architecture is:
|
||||
|
||||
|
||||
12.288 MHz
|
||||
passive crystal
|
||||
│
|
||||
▼
|
||||
┌────────────────┐
|
||||
│ ADAU1467 │
|
||||
│ │
|
||||
│ MCLK / PLL │
|
||||
│ Clock Generators│
|
||||
│ │
|
||||
│ DSP @ 48 kHz │
|
||||
└───────┬────────┘
|
||||
│
|
||||
┌───────────────┴────────────────┐
|
||||
│ │
|
||||
▼ ▼
|
||||
CLKOUT 12.288 MHz I²S clock domains
|
||||
│ │
|
||||
┌────┴────┐ ┌──────────┼──────────┐
|
||||
│ │ │ │ │
|
||||
▼ ▼ ▼ ▼ ▼
|
||||
Si4684 AIC3104 Si4684 BT1035 Codec
|
||||
XTALI MCLK I²S IN I²S OUT I²S
|
||||
|
||||
The 12.288 MHz reference and the I²S BCLK/LRCLK signals are separate functions.
|
||||
|
||||
7. Si4684 Reference Clock
|
||||
7.1 External reference
|
||||
The Si4684 supports an external reference clock through XTALI.
|
||||
The DigiRadio design shall use:
|
||||
|
||||
|
||||
ADAU1467 CLKOUT
|
||||
│
|
||||
│ 12.288 MHz
|
||||
▼
|
||||
Si4684 XTALI
|
||||
|
||||
The Si4684 shall be configured for the appropriate external-clock mode.
|
||||
The firmware configuration must explicitly set:
|
||||
|
||||
|
||||
XTAL_FREQ = 12,288,000 Hz
|
||||
|
||||
and the correct external-clock CLK_MODE.
|
||||
The Si4684 crystal oscillator configuration parameters shall not be blindly reused for external-clock operation.
|
||||
7.2 Crystal removal
|
||||
The Si4684's dedicated crystal is therefore not part of the baseline design.
|
||||
The only primary 12.288 MHz crystal in the DigiRadio design is the one associated with the ADAU1467.
|
||||
7.3 Electrical validation
|
||||
Before schematic/PCB freeze, verify:
|
||||
• ADAU1467 CLKOUT output level;
|
||||
• Si4684 XTALI input limits;
|
||||
• frequency;
|
||||
• duty cycle;
|
||||
• rise/fall time;
|
||||
• startup sequence;
|
||||
• signal integrity;
|
||||
• routing noise coupling.
|
||||
|
||||
8. Si4684 I²S Input
|
||||
The Si4684 audio data enters the ADAU1467.
|
||||
Baseline:
|
||||
|
||||
|
||||
Si4684 ADAU1467
|
||||
|
||||
DOUT ──────────────────────► Serial IN
|
||||
BCLK ◄────────────────────── Serial IN clock
|
||||
LRCLK ◄────────────────────── Serial IN frame clock
|
||||
|
||||
The Si4684 is configured as an I²S slave.
|
||||
The BCLK/LRCLK pair used by the Si4684 belongs to the selected ADAU1467 input clock domain.
|
||||
It shall not be physically connected to the BCLK/LRCLK pair used by an ADAU1467 output port merely because both operate at 48 kHz.
|
||||
|
||||
9. ESP32-S31-WROOM3 I²S Input
|
||||
The ESP32 audio stream enters the ADAU1467.
|
||||
Preferred configuration:
|
||||
|
||||
|
||||
ADAU1467 = I²S clock master
|
||||
ESP32 = I²S clock slave
|
||||
|
||||
Physical connection:
|
||||
|
||||
|
||||
ESP32 DATA ─────────────────► ADAU1467 Serial IN
|
||||
|
||||
ADAU1467 BCLK_x ────────────► ESP32 BCLK
|
||||
ADAU1467 LRCLK_x ───────────► ESP32 LRCLK
|
||||
|
||||
The ESP32 BCLK/LRCLK pair is a dedicated clock pair for that serial interface.
|
||||
It is not to be joined to the Si4684 BCLK/LRCLK pair on the PCB.
|
||||
The final ESP32 firmware shall use:
|
||||
|
||||
|
||||
Fs = 48 kHz
|
||||
slot width = 32 bit
|
||||
I²S slave mode
|
||||
|
||||
where supported by the selected ESP32 I²S implementation.
|
||||
|
||||
10. TLV320AIC3104 Codec
|
||||
The codec is:
|
||||
|
||||
|
||||
TLV320AIC3104IRHBR
|
||||
|
||||
It provides:
|
||||
• stereo ADC;
|
||||
• stereo DAC;
|
||||
• Line In;
|
||||
• Line Out;
|
||||
• headphone output path;
|
||||
• digital I²S interface;
|
||||
• internal clock/PLL circuitry.
|
||||
|
||||
11. Codec MCLK
|
||||
The codec can use the same 12.288 MHz clock reference.
|
||||
Preferred connection:
|
||||
|
||||
|
||||
ADAU1467 CLKOUT
|
||||
│
|
||||
│ 12.288 MHz
|
||||
▼
|
||||
TLV320AIC3104 MCLK
|
||||
|
||||
At 48 kHz:
|
||||
|
||||
|
||||
12.288 MHz / 256 = 48 kHz
|
||||
|
||||
This provides a clean and deterministic clock relationship between the ADAU1467 and codec.
|
||||
The codec's PLL/divider configuration must be programmed according to the TLV320AIC3104 datasheet.
|
||||
|
||||
12. Codec ADC — Line In to ADAU1467
|
||||
The analog input path is:
|
||||
|
||||
|
||||
LINE IN
|
||||
│
|
||||
▼
|
||||
TLV320AIC3104 ADC
|
||||
│
|
||||
│ DOUT
|
||||
▼
|
||||
ADAU1467 Serial IN
|
||||
|
||||
The digital clock connection is:
|
||||
|
||||
|
||||
ADAU1467 BCLK_CODEC_IN
|
||||
│
|
||||
└──────────────► AIC3104 BCLK
|
||||
|
||||
ADAU1467 LRCLK_CODEC_IN
|
||||
│
|
||||
└──────────────► AIC3104 WCLK/LRCLK
|
||||
|
||||
and:
|
||||
|
||||
|
||||
AIC3104 DOUT ─────────► ADAU1467 Serial IN
|
||||
|
||||
The codec ADC interface is therefore an ADAU1467 input serial port.
|
||||
|
||||
13. Codec DAC — ADAU1467 to Line Out / Headphone
|
||||
The output path is:
|
||||
|
||||
|
||||
ADAU1467 Serial OUT
|
||||
│
|
||||
│ DIN
|
||||
▼
|
||||
TLV320AIC3104 DAC
|
||||
│
|
||||
├──► LINE OUT
|
||||
│
|
||||
└──► HEADPHONE AMPLIFIER
|
||||
│
|
||||
▼
|
||||
Headphone Jack
|
||||
|
||||
Clocking:
|
||||
|
||||
|
||||
ADAU1467 BCLK_CODEC_OUT
|
||||
│
|
||||
└──────────────► AIC3104 BCLK
|
||||
|
||||
ADAU1467 LRCLK_CODEC_OUT
|
||||
│
|
||||
└──────────────► AIC3104 WCLK/LRCLK
|
||||
|
||||
Data:
|
||||
|
||||
|
||||
ADAU1467 Serial OUT DATA ──► AIC3104 DIN
|
||||
|
||||
The codec output clock pair is a dedicated ADAU1467 output clock-domain pair.
|
||||
|
||||
14. Important: Codec Input and Output Clocks
|
||||
Even though the codec ADC and DAC operate at the same nominal:
|
||||
|
||||
|
||||
48 kHz / 3.072 MHz
|
||||
|
||||
the schematic shall not assume that the codec ADC and DAC automatically share one physical BCLK/LRCLK net.
|
||||
The preferred implementation is:
|
||||
|
||||
|
||||
ADAU1467 INPUT CLOCK DOMAIN
|
||||
│
|
||||
├── BCLK_CODEC_IN
|
||||
└── LRCLK_CODEC_IN
|
||||
│
|
||||
▼
|
||||
AIC3104 ADC
|
||||
|
||||
|
||||
ADAU1467 OUTPUT CLOCK DOMAIN
|
||||
│
|
||||
├── BCLK_CODEC_OUT
|
||||
└── LRCLK_CODEC_OUT
|
||||
│
|
||||
▼
|
||||
AIC3104 DAC
|
||||
|
||||
Whether the final AIC3104 implementation can safely use one common physical clock pair for both directions is a specific codec-interface configuration decision and must be made from the TLV320AIC3104 timing/master/slave requirements.
|
||||
The architecture does not require us to tie the two domains together.
|
||||
|
||||
15. BT1035
|
||||
The BT1035 is an I²S output peripheral.
|
||||
Preferred configuration:
|
||||
|
||||
|
||||
ADAU1467 = I²S master
|
||||
BT1035 = I²S slave
|
||||
|
||||
Physical connections:
|
||||
|
||||
|
||||
ADAU1467 BCLK_BT
|
||||
└──────────────► BT1035 BCLK
|
||||
|
||||
ADAU1467 LRCLK_BT
|
||||
└──────────────► BT1035 LRCLK
|
||||
|
||||
ADAU1467 DATA_BT
|
||||
└──────────────► BT1035 I²S DATA
|
||||
|
||||
Baseline:
|
||||
|
||||
|
||||
48 kHz
|
||||
32 bit
|
||||
BCLK = 3.072 MHz
|
||||
|
||||
The BT1035 interface is an ADAU1467 output clock domain.
|
||||
It shall not share a PCB BCLK/LRCLK net with the codec unless deliberately configured and electrically verified.
|
||||
|
||||
16. S/PDIF Input
|
||||
S/PDIF is handled by the dedicated ADAU1467 S/PDIF input.
|
||||
|
||||
|
||||
S/PDIF IN
|
||||
│
|
||||
▼
|
||||
ADAU1467 S/PDIF RX
|
||||
│
|
||||
▼
|
||||
ASRC / DSP clock domain
|
||||
|
||||
There is no external BCLK/LRCLK connection.
|
||||
The recovered S/PDIF clock is not physically combined with the I²S clock network.
|
||||
|
||||
17. S/PDIF Output
|
||||
Likewise:
|
||||
|
||||
|
||||
ADAU1467 S/PDIF TX
|
||||
│
|
||||
▼
|
||||
S/PDIF OUT
|
||||
|
||||
No external BCLK/LRCLK is required.
|
||||
|
||||
18. Clock-Domain Allocation
|
||||
The following is the proposed logical allocation.
|
||||
Input side
|
||||
Device
|
||||
ADAU interface
|
||||
Clock ownership
|
||||
Si4684
|
||||
Serial IN 0
|
||||
ADAU1467 input clock domain
|
||||
ESP32-S31-WROOM3
|
||||
Serial IN 1
|
||||
ADAU1467 input clock domain
|
||||
AIC3104 ADC
|
||||
Serial IN 2
|
||||
ADAU1467 input clock domain
|
||||
S/PDIF
|
||||
Dedicated S/PDIF IN
|
||||
Recovered S/PDIF clock / ASRC
|
||||
Output side
|
||||
Device
|
||||
ADAU interface
|
||||
Clock ownership
|
||||
BT1035
|
||||
Serial OUT 0
|
||||
ADAU1467 output clock domain
|
||||
AIC3104 DAC
|
||||
Serial OUT 1
|
||||
ADAU1467 output clock domain
|
||||
S/PDIF
|
||||
Dedicated S/PDIF OUT
|
||||
ADAU1467 S/PDIF subsystem
|
||||
The exact serial-port numbers are implementation assignments and shall be finalized against the ADAU1467 pinout and PCB placement.
|
||||
|
||||
19. No Clock "Mishmash"
|
||||
The following shall be considered a design rule:
|
||||
Do not electrically connect unrelated BCLK or LRCLK signals merely because they have the same frequency.
|
||||
For example, these are logically different:
|
||||
|
||||
|
||||
BCLK_SI4684
|
||||
BCLK_ESP32
|
||||
BCLK_CODEC_IN
|
||||
BCLK_BT
|
||||
BCLK_CODEC_OUT
|
||||
|
||||
Even if all are:
|
||||
|
||||
|
||||
3.072 MHz
|
||||
|
||||
they are separate clock nets.
|
||||
Likewise:
|
||||
|
||||
|
||||
LRCLK_SI4684
|
||||
LRCLK_ESP32
|
||||
LRCLK_CODEC_IN
|
||||
LRCLK_BT
|
||||
LRCLK_CODEC_OUT
|
||||
|
||||
remain separate nets.
|
||||
This provides:
|
||||
• deterministic ownership;
|
||||
• no contention between clock drivers;
|
||||
• cleaner PCB routing;
|
||||
• easier debugging;
|
||||
• easier clock-domain changes;
|
||||
• easier future support for different sample rates.
|
||||
|
||||
20. Internal ADAU1467 Clock Relationship
|
||||
The important distinction is:
|
||||
|
||||
|
||||
PHYSICAL PCB CONNECTION
|
||||
≠
|
||||
LOGICAL CLOCK RELATIONSHIP
|
||||
|
||||
The ADAU1467 can derive several clock domains from the same master reference.
|
||||
Therefore:
|
||||
|
||||
|
||||
BCLK_A = 3.072 MHz
|
||||
BCLK_B = 3.072 MHz
|
||||
BCLK_C = 3.072 MHz
|
||||
|
||||
does not imply:
|
||||
|
||||
|
||||
BCLK_A = physical net BCLK_B = physical net BCLK_C
|
||||
|
||||
They are independently generated/assigned clock-domain signals.
|
||||
The synchronization relationship is established by the ADAU1467 clock-generation architecture.
|
||||
|
||||
21. PCB Net Naming
|
||||
The schematic shall use explicit net names.
|
||||
Recommended names:
|
||||
|
||||
|
||||
MCLK_12M288
|
||||
SI4684_BCLK
|
||||
SI4684_LRCLK
|
||||
SI4684_SDOUT
|
||||
|
||||
ESP32_BCLK
|
||||
ESP32_LRCLK
|
||||
ESP32_SDOUT
|
||||
|
||||
CODEC_ADC_BCLK
|
||||
CODEC_ADC_LRCLK
|
||||
CODEC_ADC_SDOUT
|
||||
|
||||
BT_BCLK
|
||||
BT_LRCLK
|
||||
BT_SDIN
|
||||
|
||||
CODEC_DAC_BCLK
|
||||
CODEC_DAC_LRCLK
|
||||
CODEC_DAC_SDIN
|
||||
|
||||
SPDIF_IN
|
||||
SPDIF_OUT
|
||||
|
||||
Do not use a generic:
|
||||
|
||||
|
||||
BCLK
|
||||
LRCLK
|
||||
|
||||
label for the entire board unless that net is intentionally a single shared physical clock.
|
||||
|
||||
22. PCB Routing Rules
|
||||
22.1 MCLK_12M288
|
||||
Route:
|
||||
|
||||
|
||||
ADAU1467 CLKOUT
|
||||
│
|
||||
├──► Si4684 XTALI
|
||||
└──► AIC3104 MCLK
|
||||
|
||||
The two loads may be fed from the same source only after checking the ADAU1467 CLKOUT drive capability and total input capacitance.
|
||||
Keep the clock routes short and away from switching-regulator nodes.
|
||||
22.2 BCLK/LRCLK
|
||||
Each clock pair shall be routed independently:
|
||||
|
||||
|
||||
ADAU1467
|
||||
│
|
||||
├── SI4684_BCLK / LRCLK
|
||||
│
|
||||
├── ESP32_BCLK / LRCLK
|
||||
│
|
||||
├── CODEC_ADC_BCLK / LRCLK
|
||||
│
|
||||
├── BT_BCLK / LRCLK
|
||||
│
|
||||
└── CODEC_DAC_BCLK / LRCLK
|
||||
|
||||
Avoid unnecessary stubs.
|
||||
Use source termination if required by signal-integrity analysis.
|
||||
|
||||
23. Why No External Clock Splitter?
|
||||
A clock splitter is not required simply because several peripherals use 48 kHz.
|
||||
The ADAU1467 already provides the required clock-generation architecture.
|
||||
Adding an external clock splitter would introduce:
|
||||
• another active clock component;
|
||||
• additional propagation delay;
|
||||
• additional jitter;
|
||||
• additional power consumption;
|
||||
• another configuration dependency;
|
||||
• another possible failure point.
|
||||
It should therefore be added only if electrical analysis proves that a specific fanout requirement cannot be met by the ADAU1467 clock outputs.
|
||||
|
||||
24. Why Not Share BCLK/LRCLK Everywhere?
|
||||
Sharing clock signals is technically possible in some I²S designs, but it is not the baseline DigiRadio architecture.
|
||||
The risks of indiscriminate sharing are:
|
||||
• conflicting clock drivers;
|
||||
• accidental master/master configuration;
|
||||
• long PCB branches;
|
||||
• uncontrolled stubs;
|
||||
• difficult debugging;
|
||||
• inability to independently change one interface;
|
||||
• confusion between ADAU input and output clock domains.
|
||||
The ADAU1467 gives us enough clock-domain infrastructure to avoid these problems.
|
||||
Therefore the design deliberately favors independent clock pairs.
|
||||
|
||||
25. Master/Slave Policy
|
||||
The baseline policy is:
|
||||
Device
|
||||
I²S role
|
||||
ADAU1467
|
||||
Master
|
||||
Si4684
|
||||
Slave
|
||||
ESP32-S31-WROOM3
|
||||
Slave
|
||||
TLV320AIC3104
|
||||
Slave where supported/configured
|
||||
BT1035
|
||||
Slave
|
||||
This avoids multiple external clock masters.
|
||||
Any deviation must be documented as an explicit architecture change.
|
||||
|
||||
26. Sample-Rate Conversion
|
||||
If an external source operates at a sample rate different from 48 kHz:
|
||||
|
||||
|
||||
External clock domain
|
||||
│
|
||||
▼
|
||||
ADAU1467 Serial Port
|
||||
│
|
||||
▼
|
||||
ASRC
|
||||
│
|
||||
▼
|
||||
48 kHz DSP domain
|
||||
|
||||
The external BCLK/LRCLK must remain local to that interface.
|
||||
It shall not be forced onto the main 48 kHz clock net.
|
||||
|
||||
27. Final Logical Architecture
|
||||
|
||||
|
||||
12.288 MHz
|
||||
ADAU CRYSTAL
|
||||
│
|
||||
▼
|
||||
┌───────────────┐
|
||||
│ ADAU1467 │
|
||||
│ │
|
||||
│ PLL │
|
||||
│ Clock Gen. │
|
||||
│ DSP │
|
||||
└───────┬───────┘
|
||||
│
|
||||
┌──────────────┼───────────────┐
|
||||
│ │ │
|
||||
▼ ▼ ▼
|
||||
CLKOUT INPUT DOMAINS OUTPUT DOMAINS
|
||||
12.288 MHz │ │
|
||||
│ │ │
|
||||
┌─────┴─────┐ │ ┌────┼─────┐
|
||||
│ │ │ │ │
|
||||
▼ ▼ ▼ ▼ ▼
|
||||
Si4684 AIC3104 Si4684 BT1035 AIC3104
|
||||
XTALI MCLK I²S IN I²S OUT I²S OUT
|
||||
▲ │ │
|
||||
│ │ │
|
||||
ESP32 I²S BCLK/LR BCLK/LR
|
||||
▲
|
||||
│
|
||||
ESP32 DATA
|
||||
|
||||
S/PDIF remains on the dedicated ADAU1467 interfaces.
|
||||
|
||||
28. Implementation Sequence
|
||||
The schematic implementation shall proceed in this order:
|
||||
1 Place ADAU1467.
|
||||
2 Place the 12.288 MHz crystal and its oscillator network.
|
||||
3 Define ADAU1467 PLL and clock-generator configuration.
|
||||
4 Define serial input clock domains.
|
||||
5 Assign Si4684 to an input serial port.
|
||||
6 Assign ESP32 to an input serial port.
|
||||
7 Assign AIC3104 ADC to an input serial port.
|
||||
8 Define output clock domains.
|
||||
9 Assign BT1035 to an output serial port.
|
||||
10 Assign AIC3104 DAC to an output serial port.
|
||||
11 Connect ADAU1467 CLKOUT to Si4684 XTALI.
|
||||
12 Connect ADAU1467 CLKOUT to AIC3104 MCLK if the final loading analysis permits.
|
||||
13 Route every BCLK/LRCLK pair as a separate named net.
|
||||
14 Verify that no two clock outputs are accidentally shorted.
|
||||
15 Verify all master/slave settings.
|
||||
16 Verify SigmaStudio serial-port and clock-domain assignments against the schematic.
|
||||
17 Perform signal-integrity review before PCB release.
|
||||
|
||||
29. Verification Checklist
|
||||
Master clock
|
||||
• 12.288 MHz crystal connected to ADAU1467.
|
||||
• ADAU1467 PLL configuration verified.
|
||||
• 12.288 MHz CLKOUT configuration verified.
|
||||
• CLKOUT loading verified.
|
||||
Si4684
|
||||
• Dedicated crystal removed.
|
||||
• XTALI driven from ADAU1467 CLKOUT.
|
||||
• External-clock mode configured.
|
||||
• XTAL_FREQ = 12,288,000 Hz.
|
||||
• I²S slave mode configured.
|
||||
• Dedicated SI4684_BCLK net.
|
||||
• Dedicated SI4684_LRCLK net.
|
||||
ESP32
|
||||
• I²S slave mode verified.
|
||||
• Dedicated ESP32_BCLK net.
|
||||
• Dedicated ESP32_LRCLK net.
|
||||
• 48 kHz / selected slot format verified.
|
||||
TLV320AIC3104
|
||||
• MCLK = 12.288 MHz verified.
|
||||
• ADC serial input assigned.
|
||||
• DAC serial output assigned.
|
||||
• Master/slave mode verified.
|
||||
• ADC BCLK/LRCLK routing verified.
|
||||
• DAC BCLK/LRCLK routing verified.
|
||||
• Headphone path verified.
|
||||
BT1035
|
||||
• I²S slave mode verified.
|
||||
• 48 kHz / 32-bit configuration verified.
|
||||
• Dedicated BT_BCLK.
|
||||
• Dedicated BT_LRCLK.
|
||||
S/PDIF
|
||||
• Dedicated ADAU1467 S/PDIF IN.
|
||||
• Dedicated ADAU1467 S/PDIF OUT.
|
||||
• No BCLK/LRCLK connection required.
|
||||
PCB
|
||||
• No unintended common BCLK net.
|
||||
• No unintended common LRCLK net.
|
||||
• No master/master connection.
|
||||
• Clock routes kept short.
|
||||
• Switching-node coupling checked.
|
||||
• Signal integrity checked.
|
||||
|
||||
30. Design Decision
|
||||
The DigiRadio clock architecture is therefore based on the following definitive principles:
|
||||
1 One primary 12.288 MHz crystal on the ADAU1467.
|
||||
2 ADAU1467 is the central audio clock master.
|
||||
3 Main audio rate is 48 kHz.
|
||||
4 Baseline I²S BCLK is 3.072 MHz for stereo 32-bit slots.
|
||||
5 Si4684 receives 12.288 MHz externally from ADAU1467 CLKOUT.
|
||||
6 The Si4684 dedicated crystal is removed.
|
||||
7 TLV320AIC3104 may receive the same 12.288 MHz master reference on MCLK.
|
||||
8 Each I²S peripheral receives its own BCLK/LRCLK pair.
|
||||
9 Input and output ADAU1467 clock domains are treated as distinct.
|
||||
10 BCLK/LRCLK signals are not electrically mixed on the PCB.
|
||||
11 No generic BCLK/LRCLK splitter is required by the architecture.
|
||||
12 S/PDIF uses the dedicated ADAU1467 interfaces.
|
||||
13 ASRC is used when an external source belongs to an incompatible/asynchronous clock domain.
|
||||
14 All clock-domain assignments must be explicitly reflected in both SigmaStudio and KiCad.
|
||||
|
||||
31. References
|
||||
Primary references to be kept with the DigiRadio repository:
|
||||
• Analog Devices — ADAU1463/ADAU1467 Data Sheet.
|
||||
• Analog Devices — ADAU1467 product and evaluation-board documentation.
|
||||
• Silicon Labs — Si468x Receiver Programming Guide (AN649).
|
||||
• Silicon Labs — Si4684 hardware/reference documentation.
|
||||
• Texas Instruments — TLV320AIC3104 Data Sheet.
|
||||
• Feasycom — BT1035 Programming User Guide.
|
||||
• DigiRadio SigmaStudio project and generated DSP configuration.
|
||||
Vendor documents stored in the repository shall be treated as the implementation references. If a newer revision is added, this architecture document shall be reviewed before schematic freeze.
|
||||
@@ -0,0 +1,316 @@
|
||||
# HubAudio — MCP23S17 GPIO Distribution
|
||||
|
||||
**Progetto:** HubAudio
|
||||
**Revisione:** definitiva
|
||||
**Data:** 2026-08-22
|
||||
|
||||
---
|
||||
|
||||
## Distribuzione GPIO
|
||||
|
||||
| IC | PORTA | GPIO | Segnale | Direzione | Pull |
|
||||
|---|---|---|---|---|---|
|
||||
| U34 | A | GPA0 | `SI4684_RESET` | OUT | UP |
|
||||
| U34 | A | GPA1 | `SI4684_SMODE` | OUT | - |
|
||||
| U34 | A | GPA2 | `SI4684_ANT_SEL` | OUT | - |
|
||||
| U34 | A | GPA3 | `SI4684_INT` | IN | - |
|
||||
| U34 | A | GPA4 | `ADAU1467_RESET` | OUT | UP |
|
||||
| U34 | A | GPA5 | `ADAU1467_SELFBOOT` | OUT/STRAP | UP |
|
||||
| U34 | A | GPA6 | `RESERVED` | — | - |
|
||||
| U34 | A | GPA7 | `MIC_SOURCE_SELECT` | OUT | - |
|
||||
| U34 | B | GPB0 | `MIC_DETECT` | IN | UP |
|
||||
| U34 | B | GPB1 | `LINE_IN_DETECT` | IN | UP |
|
||||
| U34 | B | GPB2 | `LINE_OUT_DETECT` | IN | UP |
|
||||
| U34 | B | GPB3 | `JACK_DETECT` | IN | UP |
|
||||
| U34 | B | GPB4 | `BQ25896_INT` | IN | UP |
|
||||
| U34 | B | GPB5 | `BQ25896_PG#` | IN | UP |
|
||||
| U34 | B | GPB6 | `BQ27441_GPOUT` | IN | UP |
|
||||
| U34 | B | GPB7 | `TPS63020_PG` | IN | UP |
|
||||
| U36 | A | GPA0 | `BT1035_RESET` | OUT | - |
|
||||
| U36 | A | GPA1 | `BT1035_SYSCTRL` | OUT | DOWN |
|
||||
| U36 | A | GPA2 | `UART_RESET` | OUT | UP |
|
||||
| U36 | A | GPA3 | `UART_INT` | IN | - |
|
||||
| U36 | A | GPA4 | `ETH_RST#` | OUT | UP |
|
||||
| U36 | A | GPA5 | `ANALOG_POWER_EN` | OUT | - |
|
||||
| U36 | A | GPA6 | `ETHERNET_POWER_EN` | OUT | - |
|
||||
| U36 | A | GPA7 | `BQ25896_PSEL` | OUT | - |
|
||||
| U36 | B | GPB0 | `INA228_ANALOG_ALERT` | IN | UP |
|
||||
| U36 | B | GPB1 | `INA228_DIGITAL_ALERT` | IN | UP |
|
||||
| U36 | B | GPB2 | `TEMP_PWR_ALERT` | IN | UP |
|
||||
| U36 | B | GPB3 | `TEMP_ESP32_ALERT` | IN | UP |
|
||||
| U36 | B | GPB4 | `TEMP_ETH_ALERT` | IN | UP |
|
||||
| U36 | B | GPB5 | `TEMP_CODEC_ALERT` | IN | UP |
|
||||
| U36 | B | GPB6 | `RESERVED` | — | - |
|
||||
| U36 | B | GPB7 | `RESERVED` | — | - |
|
||||
|
||||
---
|
||||
|
||||
# Pull-up / Pull-down
|
||||
|
||||
## Pull-UP
|
||||
|
||||
Le seguenti linee hanno pull-up esterno:
|
||||
|
||||
- `SI4684_RESET`
|
||||
- `ADAU1467_RESET`
|
||||
- `ADAU1467_SELFBOOT`
|
||||
- `MIC_DETECT`
|
||||
- `LINE_IN_DETECT`
|
||||
- `LINE_OUT_DETECT`
|
||||
- `JACK_DETECT`
|
||||
- `BQ25896_INT`
|
||||
- `BQ25896_PG#`
|
||||
- `BQ27441_GPOUT`
|
||||
- `TPS63020_PG`
|
||||
- `UART_RESET`
|
||||
- `ETH_RST#`
|
||||
- `INA228_ANALOG_ALERT`
|
||||
- `INA228_DIGITAL_ALERT`
|
||||
- `TEMP_PWR_ALERT`
|
||||
- `TEMP_ESP32_ALERT`
|
||||
- `TEMP_ETH_ALERT`
|
||||
- `TEMP_CODEC_ALERT`
|
||||
|
||||
Per le linee open-drain/status viene utilizzato come valore nominale:
|
||||
|
||||
**10 kΩ**
|
||||
|
||||
In particolare:
|
||||
|
||||
- `BQ27441_GPOUT` → 10 kΩ
|
||||
- `TPS63020_PG` → 10 kΩ
|
||||
- `INA228_ANALOG_ALERT` → 10 kΩ
|
||||
- `INA228_DIGITAL_ALERT` → 10 kΩ
|
||||
- `BQ25896_INT` → 10 kΩ
|
||||
- `BQ25896_PG#` → 10 kΩ
|
||||
- `TEMP_PWR_ALERT` → 10 kΩ
|
||||
- `TEMP_ESP32_ALERT` → 10 kΩ
|
||||
- `TEMP_ETH_ALERT` → 10 kΩ
|
||||
- `TEMP_CODEC_ALERT` → 10 kΩ
|
||||
|
||||
## Pull-DOWN
|
||||
|
||||
- `BT1035_SYSCTRL` → **10 kΩ verso GND**
|
||||
|
||||
## Nessun pull esterno
|
||||
|
||||
- `SI4684_SMODE`
|
||||
- `SI4684_ANT_SEL`
|
||||
- `SI4684_INT`
|
||||
- `MIC_SOURCE_SELECT`
|
||||
- `BT1035_RESET`
|
||||
- `UART_INT`
|
||||
- `ANALOG_POWER_EN`
|
||||
- `ETHERNET_POWER_EN`
|
||||
- `BQ25896_PSEL`
|
||||
- tutti i GPIO `RESERVED`
|
||||
|
||||
---
|
||||
|
||||
# Sensori di temperatura
|
||||
|
||||
Sono previsti sensori di temperatura **I²C** basati su **TMP117**.
|
||||
|
||||
I sensori sono distribuiti fisicamente sulla scheda per monitorare le zone termicamente più significative:
|
||||
|
||||
| Sensore | Zona | Posizione |
|
||||
|---|---|---|
|
||||
| `TEMP_PWR` | Dominio alimentazione | BOTTOM, vicino ai dispositivi di alimentazione |
|
||||
| `TEMP_ESP32` | ESP32 | vicino all'ESP32 |
|
||||
| `TEMP_ETH` | Ethernet / PHY | vicino al PHY Ethernet |
|
||||
| `TEMP_CODEC` | Codec TAC5212 | vicino al codec |
|
||||
|
||||
I sensori condividono il bus I²C e vengono identificati tramite il relativo indirizzo `ADDR`.
|
||||
|
||||
Ogni sensore dispone di:
|
||||
|
||||
- alimentazione locale
|
||||
- condensatore di bypass **100 nF**
|
||||
- `SDA`
|
||||
- `SCL`
|
||||
- `ADDR`
|
||||
- `ALERT`
|
||||
|
||||
### ALERT
|
||||
|
||||
L'uscita `ALERT` dei TMP117 viene utilizzata come segnalazione hardware verso il Device Manager:
|
||||
|
||||
- `TEMP_PWR_ALERT` → U36 GPB2
|
||||
- `TEMP_ESP32_ALERT` → U36 GPB3
|
||||
- `TEMP_ETH_ALERT` → U36 GPB4
|
||||
- `TEMP_CODEC_ALERT` → U36 GPB5
|
||||
|
||||
Le linee `ALERT` sono ingressi del MCP23S17 e utilizzano un pull-up esterno da **10 kΩ**.
|
||||
|
||||
Il Device Manager può quindi ricevere immediatamente una segnalazione di superamento della soglia termica senza dover effettuare continuamente il polling dei sensori.
|
||||
|
||||
---
|
||||
|
||||
## Note sui dispositivi
|
||||
|
||||
### SI4684
|
||||
|
||||
`SI4684_RESET` è il reset active-low del dispositivo.
|
||||
|
||||
Il pull-up garantisce il rilascio del reset dopo la fase di power-up.
|
||||
|
||||
### ADAU1467
|
||||
|
||||
`ADAU1467_RESET` è active-low.
|
||||
|
||||
`ADAU1467_SELFBOOT` deve essere HIGH per il self-boot dalla EEPROM.
|
||||
|
||||
### TAC5212
|
||||
|
||||
Il codec `XTAC5212IRGER` è il **TAC5212**.
|
||||
|
||||
Non esiste un reset hardware dedicato da collegare al MCP23S17; il reset è gestito tramite la configurazione software del dispositivo.
|
||||
|
||||
**U34 GPA6 = RESERVED.**
|
||||
|
||||
### BT1035
|
||||
|
||||
`BT1035_RESET` non necessita di pull-up esterno perché il modulo dispone del proprio pull-up interno.
|
||||
|
||||
`BT1035_SYSCTRL` richiede invece il pull-down esterno.
|
||||
|
||||
### BQ27441
|
||||
|
||||
`GPOUT` è open-drain e il datasheet raccomanda esplicitamente una resistenza di pull-up da **10 kΩ**.
|
||||
|
||||
### TPS63020
|
||||
|
||||
`PG` è un'uscita **open-drain**. Il pull-up è quindi necessario quando il segnale viene utilizzato come ingresso digitale dal MCP23S17.
|
||||
|
||||
### INA228
|
||||
|
||||
`ALERT` è la linea di alert del monitor e viene utilizzata come ingresso verso il MCP23S17; è prevista con pull-up esterno.
|
||||
|
||||
### TMP117
|
||||
|
||||
Il TMP117 è utilizzato come sensore di temperatura locale.
|
||||
|
||||
La comunicazione avviene tramite I²C. Il pin `ALERT` viene utilizzato per generare una segnalazione hardware verso il Device Manager tramite U36.
|
||||
|
||||
Ogni sensore dispone di un proprio indirizzo I²C tramite il pin `ADDR`.
|
||||
|
||||
---
|
||||
|
||||
# Regola generale
|
||||
|
||||
Ogni net deve avere **una sola resistenza fisica di pull-up/pull-down**.
|
||||
|
||||
Se una net viene condivisa da più dispositivi, non devono essere installate resistenze duplicate sui vari dispositivi.
|
||||
|
||||
Il pull-up interno del MCP23S17 non viene utilizzato come sostituto dei pull-up esterni delle linee di stato/open-drain.
|
||||
|
||||
Per le linee `ALERT` dei TMP117 viene mantenuto il pull-up esterno da **10 kΩ**.
|
||||
|
||||
---
|
||||
|
||||
# Distribuzione funzionale
|
||||
|
||||
## U34 PORTA — Audio / Radio Control
|
||||
|
||||
| GPIO | Funzione |
|
||||
|---|---|
|
||||
| GPA0 | SI4684 RESET |
|
||||
| GPA1 | SI4684 SMODE |
|
||||
| GPA2 | SI4684 ANT SEL |
|
||||
| GPA3 | SI4684 INT |
|
||||
| GPA4 | ADAU1467 RESET |
|
||||
| GPA5 | ADAU1467 SELFBOOT |
|
||||
| GPA6 | RESERVED |
|
||||
| GPA7 | MIC SOURCE SELECT |
|
||||
|
||||
## U34 PORTB — Detection / Power Status
|
||||
|
||||
| GPIO | Funzione |
|
||||
|---|---|
|
||||
| GPB0 | MIC DETECT |
|
||||
| GPB1 | LINE IN DETECT |
|
||||
| GPB2 | LINE OUT DETECT |
|
||||
| GPB3 | JACK DETECT |
|
||||
| GPB4 | BQ25896 INT |
|
||||
| GPB5 | BQ25896 PG# |
|
||||
| GPB6 | BQ27441 GPOUT |
|
||||
| GPB7 | TPS63020 PG |
|
||||
|
||||
## U36 PORTA — BT / UART / Ethernet / Power
|
||||
|
||||
| GPIO | Funzione |
|
||||
|---|---|
|
||||
| GPA0 | BT1035 RESET |
|
||||
| GPA1 | BT1035 SYSCTRL |
|
||||
| GPA2 | UART RESET |
|
||||
| GPA3 | UART INT |
|
||||
| GPA4 | ETH RESET |
|
||||
| GPA5 | ANALOG POWER EN |
|
||||
| GPA6 | ETHERNET POWER EN |
|
||||
| GPA7 | BQ25896 PSEL |
|
||||
|
||||
## U36 PORTB — Power / Temperature Monitoring
|
||||
|
||||
| GPIO | Funzione |
|
||||
|---|---|
|
||||
| GPB0 | INA228 ANALOG ALERT |
|
||||
| GPB1 | INA228 DIGITAL ALERT |
|
||||
| GPB2 | TEMP PWR ALERT |
|
||||
| GPB3 | TEMP ESP32 ALERT |
|
||||
| GPB4 | TEMP ETH ALERT |
|
||||
| GPB5 | TEMP CODEC ALERT |
|
||||
| GPB6 | RESERVED |
|
||||
| GPB7 | RESERVED |
|
||||
|
||||
---
|
||||
|
||||
# Tabella resistenze da inserire nello schematico
|
||||
|
||||
| Net | Resistenza | Collegamento |
|
||||
|---|---:|---|
|
||||
| `SI4684_RESET` | 10 kΩ | VIO → RESET |
|
||||
| `ADAU1467_RESET` | 10 kΩ | IOVDD → RESET |
|
||||
| `ADAU1467_SELFBOOT` | 10 kΩ | IOVDD → SELFBOOT |
|
||||
| `MIC_DETECT` | 10 kΩ | VIO → DETECT |
|
||||
| `LINE_IN_DETECT` | 10 kΩ | VIO → DETECT |
|
||||
| `LINE_OUT_DETECT` | 10 kΩ | VIO → DETECT |
|
||||
| `JACK_DETECT` | 10 kΩ | VIO → DETECT |
|
||||
| `BQ25896_INT` | 10 kΩ | VIO → INT |
|
||||
| `BQ25896_PG#` | 10 kΩ | VIO → PG# |
|
||||
| `BQ27441_GPOUT` | 10 kΩ | VDD → GPOUT |
|
||||
| `TPS63020_PG` | 10 kΩ | VOUT/VIO → PG |
|
||||
| `BT1035_SYSCTRL` | 10 kΩ | SYSCTRL → GND |
|
||||
| `UART_RESET` | 10 kΩ | VIO → RESET |
|
||||
| `ETH_RST#` | 10 kΩ | VIO → RESET# |
|
||||
| `INA228_ANALOG_ALERT` | 10 kΩ | VIO → ALERT |
|
||||
| `INA228_DIGITAL_ALERT` | 10 kΩ | VIO → ALERT |
|
||||
| `TEMP_PWR_ALERT` | 10 kΩ | VIO → ALERT |
|
||||
| `TEMP_ESP32_ALERT` | 10 kΩ | VIO → ALERT |
|
||||
| `TEMP_ETH_ALERT` | 10 kΩ | VIO → ALERT |
|
||||
| `TEMP_CODEC_ALERT` | 10 kΩ | VIO → ALERT |
|
||||
|
||||
---
|
||||
|
||||
# Stato
|
||||
|
||||
**U34:** assegnazione completa.
|
||||
|
||||
**U36:** assegnazione completa.
|
||||
|
||||
**TAC5212:** nessun GPIO dedicato al reset.
|
||||
|
||||
**BT1035_RESET:** nessun pull esterno.
|
||||
|
||||
**BT1035_SYSCTRL:** 10 kΩ pull-down.
|
||||
|
||||
**Linee open-drain/status:** pull-up 10 kΩ.
|
||||
|
||||
**TMP117:** 4 sensori I²C distribuiti nelle zone termicamente significative.
|
||||
|
||||
**TMP117 ALERT:** collegati al Device Manager tramite U36 GPB2–GPB5.
|
||||
|
||||
**U34 GPA6:** RESERVED.
|
||||
|
||||
**U36 GPB6–GPB7:** RESERVED.
|
||||
|
||||
**INTB U34/U36:** non collegati intenzionalmente.
|
||||
@@ -0,0 +1,291 @@
|
||||
# ARCH-PCB-001 — Layer Architecture & Routing Strategy
|
||||
|
||||
**Project:** HubAudio
|
||||
**PCB:** 6-layer mixed-signal audio/RF board
|
||||
**Status:** Architecture baseline
|
||||
**Revision:** 1.0
|
||||
**Date:** 2026-08-24
|
||||
|
||||
---
|
||||
|
||||
## 1. Purpose
|
||||
|
||||
This document defines the layer architecture and routing strategy for the HubAudio PCB.
|
||||
|
||||
The objectives are:
|
||||
|
||||
- minimize EMI and crosstalk;
|
||||
- provide short and well-defined return paths for high-speed signals;
|
||||
- preserve signal integrity for audio, clock, SPI, USB, Ethernet and RF interfaces;
|
||||
- isolate slow control signals from critical high-speed routing;
|
||||
- simplify placement and routing decisions;
|
||||
- maintain a consistent PCB architecture throughout layout.
|
||||
|
||||
The layer assignment is an architectural constraint, not merely a routing preference.
|
||||
|
||||
---
|
||||
|
||||
## 2. PCB Stackup
|
||||
|
||||
The PCB uses a 6-layer stackup with 35 µm copper on all copper layers.
|
||||
|
||||
| Layer | Type | Primary Function |
|
||||
|---|---|---|
|
||||
| **L1 — F.Cu** | Copper | Components + high-speed / critical signals |
|
||||
| **L2 — In1.Cu** | Copper | **GND plane** |
|
||||
| **L3 — In2.Cu** | Copper | Slow signals / control |
|
||||
| **L4 — In3.Cu** | Copper | **POWER plane** |
|
||||
| **L5 — In4.Cu** | Copper | **GND plane** |
|
||||
| **L6 — B.Cu** | Copper | Components + slow / secondary signals |
|
||||
|
||||
### Dielectric structure
|
||||
|
||||
| Interface | Dielectric |
|
||||
|---|---:|
|
||||
| L1 ↔ L2 | 0.10 mm prepreg |
|
||||
| L2 ↔ L3 | 0.535 mm core |
|
||||
| L3 ↔ L4 | 0.10 mm prepreg |
|
||||
| L4 ↔ L5 | 0.535 mm core |
|
||||
| L5 ↔ L6 | 0.10 mm prepreg |
|
||||
|
||||
Total nominal PCB thickness is approximately **1.58 mm**, compatible with a nominal 1.6 mm PCB construction.
|
||||
|
||||
---
|
||||
|
||||
## 3. Layer Philosophy
|
||||
|
||||
The PCB follows this hierarchy:
|
||||
|
||||
```text
|
||||
L1 HIGH-SPEED / CRITICAL SIGNALS
|
||||
L2 GND
|
||||
L3 SLOW SIGNALS / CONTROL
|
||||
L4 POWER
|
||||
L5 GND
|
||||
L6 SECONDARY / SLOW SIGNALS
|
||||
|
||||
The fundamental principle is:
|
||||
|
||||
Keep high-speed and sensitive signals on the outer layers, directly adjacent to a solid GND reference plane.
|
||||
|
||||
L1 is therefore treated as the primary high-speed routing layer.
|
||||
|
||||
L6 may be used for secondary and slow routing, with L5 providing the adjacent GND reference.
|
||||
|
||||
4. L1 — High-Speed / Critical Signals
|
||||
|
||||
L1 is the preferred layer for signals where signal integrity, edge rate, impedance or electromagnetic coupling is important.
|
||||
|
||||
Preferred signals
|
||||
I²S
|
||||
SPI
|
||||
clocks
|
||||
USB
|
||||
Ethernet
|
||||
RF
|
||||
other high-speed digital interfaces
|
||||
critical audio clocks
|
||||
Examples
|
||||
ADAU1467 audio clocks
|
||||
I²S BCLK
|
||||
I²S LRCLK / WCLK
|
||||
I²S SDATA
|
||||
SPI clock and data
|
||||
12.288 MHz audio reference
|
||||
Ethernet PHY high-speed signals
|
||||
USB signals
|
||||
RF paths
|
||||
Rule
|
||||
|
||||
High-speed signals should remain on L1 whenever practical.
|
||||
|
||||
Avoid unnecessary layer changes.
|
||||
|
||||
When a layer transition is unavoidable, provide an appropriate nearby GND stitching via to preserve the return-current path.
|
||||
|
||||
5. L2 — Ground Plane
|
||||
|
||||
L2 is the primary continuous GND reference plane.
|
||||
|
||||
It should remain as continuous and uninterrupted as possible.
|
||||
|
||||
L2 provides the primary return-current reference for signals routed on L1.
|
||||
|
||||
Rules
|
||||
Do not route ordinary signals through L2.
|
||||
Avoid unnecessary splits or voids.
|
||||
Do not create isolated copper islands without a defined purpose.
|
||||
Provide GND vias close to layer-transition vias for high-speed signals.
|
||||
Maintain particularly clean GND under clock, I²S, SPI, USB and other fast L1 routing.
|
||||
6. L3 — Slow Signals / Control
|
||||
|
||||
L3 is dedicated primarily to low-speed digital signals.
|
||||
|
||||
Typical signals include:
|
||||
|
||||
GPIO
|
||||
RESET
|
||||
ENABLE
|
||||
INTERRUPT
|
||||
power-control signals
|
||||
configuration signals
|
||||
low-speed control interfaces
|
||||
miscellaneous control lines
|
||||
other signals where controlled impedance is not required
|
||||
|
||||
L3 should not be the preferred routing layer for high-speed signals.
|
||||
|
||||
The relatively large dielectric spacing to L2 makes L3 less suitable than L1 for high-speed routing.
|
||||
|
||||
7. L4 — Power Plane
|
||||
|
||||
L4 is dedicated to power distribution.
|
||||
|
||||
Typical power domains may include:
|
||||
|
||||
3V3_DIG
|
||||
3V3_AUDIO
|
||||
1V8
|
||||
1V2
|
||||
other required regulated or switched rails
|
||||
|
||||
Power domains shall be partitioned logically according to the power architecture.
|
||||
|
||||
Power routing should avoid unnecessarily crossing sensitive signal regions.
|
||||
|
||||
The power plane must not be treated as a generic signal-routing layer unless specifically required.
|
||||
|
||||
8. L5 — Ground Plane
|
||||
|
||||
L5 is the secondary continuous GND plane.
|
||||
|
||||
It provides the primary reference for signals routed on L6.
|
||||
|
||||
L5 should remain as continuous as practical.
|
||||
|
||||
Together, L2 and L5 form the principal internal ground structure of the PCB.
|
||||
|
||||
9. L6 — Secondary / Slow Routing
|
||||
|
||||
L6 is intended primarily for:
|
||||
|
||||
I²C
|
||||
GPIO
|
||||
slow control signals
|
||||
secondary communication lines
|
||||
connections to components located on the bottom side
|
||||
signals that do not require controlled impedance
|
||||
I²C
|
||||
|
||||
I²C is preferentially routed on L6.
|
||||
|
||||
This keeps I²C away from the critical high-speed routing on L1 and allows bottom-side components to be connected without consuming valuable TOP routing space.
|
||||
|
||||
10. Communication-Signal Policy
|
||||
|
||||
Communication signals are classified according to electrical speed and sensitivity rather than simply by protocol name.
|
||||
|
||||
High-speed / critical
|
||||
|
||||
Preferred on L1:
|
||||
|
||||
I²S
|
||||
SPI
|
||||
clock signals
|
||||
USB
|
||||
Ethernet
|
||||
RF
|
||||
Low-speed / control
|
||||
|
||||
Preferred on L3 or L6:
|
||||
|
||||
I²C
|
||||
GPIO
|
||||
RESET
|
||||
ENABLE
|
||||
INTERRUPT
|
||||
power-control signals
|
||||
configuration interfaces
|
||||
Important exception
|
||||
|
||||
The layer policy is architectural, not an absolute prohibition.
|
||||
|
||||
A signal may use another layer when required by routing topology, component placement or congestion. However, deviations should be minimized and should have a clear reason.
|
||||
|
||||
11. TOP-Layer Routing Policy
|
||||
|
||||
L1 should not become a general-purpose routing layer.
|
||||
|
||||
The preferred priority is:
|
||||
|
||||
RF
|
||||
critical clocks
|
||||
I²S
|
||||
SPI
|
||||
USB / Ethernet high-speed signals
|
||||
other critical signals
|
||||
ordinary signals only when necessary
|
||||
|
||||
Slow GPIO and control signals should not normally be routed on L1.
|
||||
|
||||
This preserves the TOP layer for the signals that benefit most from the 0.10 mm L1–L2 geometry.
|
||||
|
||||
12. Layer Transition Rules
|
||||
|
||||
When a high-speed signal changes layer:
|
||||
|
||||
minimize the number of transitions;
|
||||
avoid unnecessary vias;
|
||||
provide a nearby GND stitching via;
|
||||
preserve the return-current path;
|
||||
avoid crossing GND-plane discontinuities.
|
||||
|
||||
For slow signals, layer transitions are less critical and may be used freely when useful for routing.
|
||||
|
||||
13. Placement Implications
|
||||
|
||||
Component placement shall support the layer architecture.
|
||||
|
||||
L1 placement
|
||||
|
||||
Critical components should be positioned so that their high-speed connections can be routed primarily on L1.
|
||||
|
||||
Examples:
|
||||
|
||||
ADAU1467
|
||||
audio codec
|
||||
Si4684
|
||||
BT1058
|
||||
Ethernet PHY
|
||||
USB interface
|
||||
clock sources
|
||||
Bottom placement
|
||||
|
||||
Bottom-side components should preferentially connect using L6 where practical.
|
||||
|
||||
I²C and other low-speed buses should therefore be planned around bottom-side placement where advantageous.
|
||||
|
||||
14. Design Rule
|
||||
|
||||
The following rule is the fundamental routing constraint for this PCB:
|
||||
|
||||
L1 is for high-speed and critical signals. L2 is their primary GND reference. L3 is for slow control. L4 is power. L5 is GND. L6 is for secondary and slow routing.
|
||||
|
||||
This rule should be applied consistently during placement and routing.
|
||||
|
||||
15. Final Layer Assignment
|
||||
┌──────────────────────────────────────────┐
|
||||
│ L1 F.Cu COMPONENTS / HIGH-SPEED │
|
||||
├──────────────────────────────────────────┤
|
||||
│ L2 In1 GND │
|
||||
├──────────────────────────────────────────┤
|
||||
│ L3 In2 SLOW SIGNAL / CONTROL │
|
||||
├──────────────────────────────────────────┤
|
||||
│ L4 In3 POWER │
|
||||
├──────────────────────────────────────────┤
|
||||
│ L5 In4 GND │
|
||||
├──────────────────────────────────────────┤
|
||||
│ L6 B.Cu COMPONENTS / SLOW SIGNAL │
|
||||
└──────────────────────────────────────────┘
|
||||
|
||||
Architecture status: BASELINE — use as the routing reference for placement and PCB layout.
|
||||
@@ -0,0 +1,65 @@
|
||||
# Mappatura Hardware e Pinout: ESP32-S31-WROOM-3
|
||||
|
||||
Questo documento raccoglie la configurazione completa e definitiva dei pin per il modulo **ESP32-S31-WROOM-3** utilizzata nel layout del PCB.
|
||||
|
||||
---
|
||||
|
||||
## 1. Tabella Definitiva Mappatura Hardware
|
||||
|
||||
| Periferica / Blocco | Segnale Hardware | GPIO ESP32-S31 | Pin Schema | Note e Connessioni Hardware |
|
||||
| :--- | :--- | :--- | :--- | :--- |
|
||||
| **ETHERNET (RMII / LAN8720A)** | `ETH_50MHZ_CLOCK` | **GPIO13** | **Pin 19** | Ingresso Clock 50 MHz da oscillatore |
|
||||
| | `ETH_TXD0` | **GPIO8** | **Pin 14** | Dati TX Bit 0 |
|
||||
| | `ETH_TXD1` | **GPIO9** | **Pin 15** | Dati TX Bit 1 |
|
||||
| | `ETH_TXEN` | **GPIO12** | **Pin 18** | Transmit Enable |
|
||||
| | `ETH_RXD0` | **GPIO19** | **Pin 25** | Dati RX Bit 0 |
|
||||
| | `ETH_RXD1` | **GPIO18** | **Pin 24** | Dati RX Bit 1 |
|
||||
| | `ETH_CRS_DV` | **GPIO15** | **Pin 21** | Carrier Sense / Data Valid |
|
||||
| | `ETH_MDC` | **GPIO5** | **Pin 11** | Clock Gestione PHY |
|
||||
| | `ETH_MDIO` | **GPIO6** | **Pin 12** | Dati Gestione PHY (Pull-up 1.5 kΩ ~ 4.7 kΩ) |
|
||||
| | `ETH_RST#` | **GPIO7** | **Pin 13** | Reset Hardware LAN8720A |
|
||||
| | `ETH_RXER` | **GPIO10** | **Pin 16** | Receive Error / Config. Indirizzo PHY0 |
|
||||
| | `ETH_INT#` | **GPIO4** | **Pin 10** | Interruzione PHY (Pull-up 10 kΩ) |
|
||||
| **SPI BUS (Master)** | `SPI_MOSI` | **GPIO2** | **Pin 6** | Dati in Uscita (Condiviso Si4684 + ADAU1467)[cite: 1] |
|
||||
| | `SPI_MISO` | **GPIO3** | **Pin 7** | Dati in Ingresso (Condiviso Si4684 + ADAU1467)[cite: 1] |
|
||||
| | `SPI_CLK` | **GPIO1** | **Pin 9** | Clock Serial SPI[cite: 1] |
|
||||
| | `SPI_SI4684_CS` | **GPIO16** | **Pin 22** | Chip Select Radio Si4684[cite: 1] |
|
||||
| | `SPI_ADAU1467_CS` | **GPIO17** | **Pin 23** | Chip Select DSP ADAU1467[cite: 1] |
|
||||
| **I2C BUS (Master)** | `I2C_SDA` | **GPIO50** | **Pin 60** | (Pull-up 4.7 kΩ) |
|
||||
| | `I2C_SCL` | **GPIO51** | **Pin 61** | (Pull-up 4.7 kΩ) |
|
||||
| **I2S_0 (Slave)** | `I2S0_BCLK` | **GPIO42** | **Pin 52** | Bit Clock (Ingresso da Master esterno)[cite: 1] |
|
||||
| | `I2S0_LRCLK` | **GPIO43** | **Pin 53** | Frame Sync / WS (Ingresso da Master)[cite: 1] |
|
||||
| | `I2S0_DATA` | **GPIO44** | **Pin 54** | Dati Audio 1[cite: 1] |
|
||||
| **I2S_1 (Slave)** | `I2S1_BCLK` | **GPIO46** | **Pin 56** | Bit Clock (Ingresso da Master esterno)[cite: 1] |
|
||||
| | `I2S1_LRCLK` | **GPIO47** | **Pin 57** | Frame Sync / WS (Ingresso da Master)[cite: 1] |
|
||||
| | `I2S1_DATA` | **GPIO48** | **Pin 58** | Dati Audio 2[cite: 1] |
|
||||
| **UART BT1035** | `BT_TX` | **GPIO52** | **Pin 62** | Collegare a **RXD** del modulo BT1035 |
|
||||
| | `BT_RX` | **GPIO53** | **Pin 63** | Collegare a **TXD** del modulo BT1035 |
|
||||
| | `BT_RTS` *(Opz.)* | **GPIO54** | **Pin 64** | Controllo di flusso (Collegare a **CTS** del BT1035) |
|
||||
| | `BT_CTS` *(Opz.)* | **GPIO55** | **Pin 65** | Controllo di flusso (Collegare a **RTS** del BT1035) |
|
||||
| **INTERRUPTS & IO** | `PCA_POWER_INT` | **GPIO11** | **Pin 17** | Interruzione da espansore I2C PCA9555 (Power Unit)[cite: 1] |
|
||||
| | `SPARE_IO0` | **GPIO16** | **Pin 22** | GPIO libero / Riserva[cite: 1] |
|
||||
| | `SPARE_IO1` | **GPIO17** | **Pin 23** | GPIO libero / Riserva[cite: 1] |
|
||||
| **SYSTEM & BOOT** | `ESP_EN` | **EN** | **Pin 5** | Reset Hardware (Pull-up 10 kΩ + Cap 1 µF verso GND)[cite: 1] |
|
||||
| | `ESP_BOOT` | **GPIO61** | **Pin 71** | Strapping Pin / Pulsante BOOT (Pull-up interno)[cite: 1] |
|
||||
| | `USB_DP` | **USB_DP** | **Pin 40** | USB Data+ (Coppia differenziale 90 Ω)[cite: 1] |
|
||||
| | `USB_DM` | **USB_DM** | **Pin 41** | USB Data- (Coppia differenziale 90 Ω)[cite: 1] |
|
||||
|
||||
---
|
||||
|
||||
## 2. Note di Progettazione Hardware
|
||||
|
||||
### USB Serial / JTAG Integrato
|
||||
* Per programmazione e debug è sufficiente un singolo connettore **USB Type-C** direttamente collegato a `USB_DP` (Pin 40) e `USB_DM` (Pin 41)[cite: 1].
|
||||
* Inserire **due resistenze da 5.1 kΩ** su CC1 e CC2 verso GND sul connettore Type-C.
|
||||
|
||||
### Bus SPI
|
||||
* I dispositivi controllati in SPI sono 2: **Si4684** (`CS0` su `GPIO13`) e **ADAU1467** (`CS1` su `GPIO14`)[cite: 1].
|
||||
* Aggiungere resistori di **pull-up esterni da 10 kΩ a 3.3V** sulle linee CS per garantire lo stato HIGH durante il boot.
|
||||
|
||||
### Bus I2C
|
||||
* Il codec **TLV320AIC3104** (indirizzo `0x18`) è controllato via I2C (`GPIO50` per SDA e `GPIO51` per SCL).
|
||||
* Prevedere due resistori di pull-up esterni da **2.2 kΩ a 4.7 kΩ** verso 3.3V.
|
||||
|
||||
### Interfacce I2S Audio
|
||||
* Entrambi i canali I2S sono configurati in modalità **Slave**. I segnali di clock `BCLK` e `LRCLK` provengono dai rispettivi dispositivi Master esterni[cite: 1].
|
||||
@@ -0,0 +1,506 @@
|
||||
# HubAudio PCB Floor Plan
|
||||
|
||||
- Status: Draft
|
||||
- Date: 2026-08-01
|
||||
- Document Type: Hardware Architecture
|
||||
|
||||
|
||||
# 1. Overview
|
||||
|
||||
This document defines the preliminary PCB floor plan for the HubAudio
|
||||
single-board audio platform.
|
||||
|
||||
The PCB integrates:
|
||||
|
||||
- System Controller
|
||||
- Audio Processor
|
||||
- Radio Receiver
|
||||
- Wireless Audio Interfaces
|
||||
- Digital Audio Interfaces
|
||||
- Power Management
|
||||
- Battery Operation Support
|
||||
|
||||
|
||||
The floor plan follows the fundamental HubAudio architecture:
|
||||
|
||||
|
||||
ESP32-S3 manages the Control Domain.
|
||||
|
||||
ADAU1467 manages the Audio Domain.
|
||||
|
||||
The Clock Distribution Layer provides synchronization
|
||||
for digital audio peripherals.
|
||||
|
||||
|
||||
The PCB layout must preserve separation between:
|
||||
|
||||
- Control Domain
|
||||
- Audio Domain
|
||||
- Clock Domain
|
||||
- Power Domain
|
||||
|
||||
|
||||
The objective is to create a compact portable audio platform while
|
||||
maintaining:
|
||||
|
||||
- audio signal integrity
|
||||
- clock stability
|
||||
- RF performance
|
||||
- power efficiency
|
||||
- battery operation capability
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 2. PCB Constraints
|
||||
|
||||
|
||||
## 2.1 Target Dimensions
|
||||
|
||||
|
||||
The HubAudio board is designed as a compact single-board platform.
|
||||
|
||||
|
||||
Preferred PCB size:
|
||||
Layer 1
|
||||
Component placement
|
||||
Critical digital signals
|
||||
Audio routing
|
||||
|
||||
Layer 2
|
||||
Continuous GND plane
|
||||
|
||||
Layer 3
|
||||
Power distribution
|
||||
|
||||
Layer 4
|
||||
Control signals
|
||||
Low speed routing
|
||||
Auxiliary signals
|
||||
|
||||
|
||||
A 6-layer PCB remains an optional evolution only if required after
|
||||
routing verification.
|
||||
|
||||
|
||||
The transition to 6 layers must be justified by:
|
||||
|
||||
- routing density
|
||||
- clock integrity
|
||||
- RF isolation requirements
|
||||
- power distribution constraints
|
||||
|
||||
|
||||
The initial architecture target remains:
|
||||
4 Layer PCB
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 4. Functional PCB Zones
|
||||
|
||||
|
||||
The PCB is divided into five functional areas.
|
||||
|
||||
|
||||
## 4.1 Control Zone
|
||||
|
||||
|
||||
Contains:
|
||||
|
||||
- ESP32-S3
|
||||
- USB interface
|
||||
- programming interface
|
||||
- user interface connections
|
||||
|
||||
|
||||
Responsibilities:
|
||||
|
||||
- network connectivity
|
||||
- streaming control
|
||||
- configuration management
|
||||
- firmware updates
|
||||
|
||||
|
||||
Placement requirements:
|
||||
|
||||
- close to PCB edge
|
||||
- antenna clearance
|
||||
- separated from switching regulators
|
||||
|
||||
|
||||
---
|
||||
|
||||
## 4.2 Audio Processing Zone
|
||||
|
||||
|
||||
Contains:
|
||||
|
||||
- ADAU1467
|
||||
- Audio EEPROM
|
||||
- Clock circuitry
|
||||
- Audio domain support components
|
||||
|
||||
|
||||
The ADAU1467 is the physical center of the Audio Domain.
|
||||
|
||||
|
||||
Responsibilities:
|
||||
|
||||
- DSP processing
|
||||
- routing
|
||||
- mixing
|
||||
- synchronization
|
||||
|
||||
|
||||
Critical signals:
|
||||
|
||||
- MCLK
|
||||
- BCLK
|
||||
- LRCLK
|
||||
- I2S DATA
|
||||
|
||||
|
||||
must remain short.
|
||||
|
||||
|
||||
---
|
||||
|
||||
## 4.3 Radio Zone
|
||||
|
||||
|
||||
Contains:
|
||||
|
||||
- Si4684
|
||||
- RF interface
|
||||
- antenna related components
|
||||
|
||||
|
||||
Placement requirements:
|
||||
|
||||
- close to RF input
|
||||
- separated from switching noise
|
||||
- local power filtering
|
||||
|
||||
|
||||
The Si4684 operates as a digital audio peripheral
|
||||
inside the Audio Domain.
|
||||
|
||||
|
||||
---
|
||||
|
||||
## 4.4 Audio Interface Zone
|
||||
|
||||
|
||||
Contains:
|
||||
|
||||
- Bluetooth interfaces
|
||||
- Optical interfaces
|
||||
- CODEC/DAC stages
|
||||
|
||||
|
||||
Interfaces:
|
||||
I2S
|
||||
|
|
||||
ADAU1467
|
||||
|
||||
|
||||
Placement requirements:
|
||||
|
||||
- close to PCB edge
|
||||
- short I2S paths
|
||||
- controlled supply filtering
|
||||
|
||||
|
||||
---
|
||||
|
||||
## 4.5 Power Zone
|
||||
|
||||
|
||||
Contains:
|
||||
|
||||
- Battery input
|
||||
- USB power input
|
||||
- Charger
|
||||
- PMIC
|
||||
- Regulators
|
||||
- Filtering components
|
||||
|
||||
|
||||
Placement:
|
||||
|
||||
PCB edge area
|
||||
|
||||
|
||||
Power path:
|
||||
|
||||
Battery / USB
|
||||
|
||||
|
|
||||
|
||||
Protection
|
||||
|
||||
|
|
||||
|
||||
Charger
|
||||
|
||||
|
|
||||
|
||||
PMIC
|
||||
|
||||
|
|
||||
|
||||
Regulators
|
||||
|
||||
|
|
||||
|
||||
Digital / Analog domains
|
||||
|
||||
|
||||
|
||||
The Power Zone must remain physically separated from:
|
||||
|
||||
- clock circuitry
|
||||
- RF section
|
||||
- sensitive audio signals
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 5. Preliminary Floor Plan
|
||||
|
||||
|
||||
Conceptual arrangement:
|
||||
|
||||
|
||||
|
||||
+--------------------------------+
|
||||
| |
|
||||
| ESP32-S3 Si4684 |
|
||||
| CONTROL RADIO |
|
||||
| |
|
||||
| |
|
||||
| CLOCK |
|
||||
| BUFFER |
|
||||
| | |
|
||||
| | |
|
||||
| ADAU1467 |
|
||||
| AUDIO PROCESSOR |
|
||||
| |
|
||||
| |
|
||||
| BT RX SPDIF CODEC BT TX |
|
||||
| AUDIO INTERFACE |
|
||||
|
||||
|
||||
|
||||
BATTERY / PMIC / CHARGER
|
||||
POWER DOMAIN
|
||||
|
||||
+--------------------------------+
|
||||
|
||||
PCB TARGET:
|
||||
|
||||
90 mm x 70 mm
|
||||
|
||||
|
||||
|
||||
This arrangement keeps the ADAU1467 physically central.
|
||||
|
||||
The placement minimizes:
|
||||
|
||||
- I2S length
|
||||
- clock distribution length
|
||||
- audio routing complexity
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 6. ADAU1467 Placement
|
||||
|
||||
|
||||
The ADAU1467 is the physical center of the digital audio subsystem.
|
||||
|
||||
|
||||
This follows the architecture decision:
|
||||
|
||||
|
||||
|
||||
ADAU1467 = Audio Domain Master
|
||||
|
||||
|
||||
|
||||
Placement rules:
|
||||
|
||||
- central PCB position
|
||||
- shortest clock paths
|
||||
- shortest I2S paths
|
||||
- local decoupling network
|
||||
- separated from switching regulators
|
||||
|
||||
|
||||
The ADAU1467 area includes:
|
||||
|
||||
- DSP processor
|
||||
- clock interface
|
||||
- SPI configuration interface
|
||||
- audio EEPROM
|
||||
|
||||
|
||||
Critical signals:
|
||||
|
||||
|
||||
MCLK
|
||||
BCLK
|
||||
LRCLK
|
||||
I2S DATA
|
||||
|
||||
|
||||
|
||||
must be routed with priority.
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 7. ESP32-S3 Placement
|
||||
|
||||
|
||||
The ESP32-S3 belongs to the Control Domain.
|
||||
|
||||
|
||||
Placement rules:
|
||||
|
||||
- PCB edge placement
|
||||
- antenna keep-out area
|
||||
- USB accessibility
|
||||
- separation from analog audio
|
||||
|
||||
|
||||
The ESP32-S3 interfaces:
|
||||
|
||||
Control:
|
||||
|
||||
|
||||
SPI
|
||||
|
||||
|
||||
|
||||
Audio:
|
||||
|
||||
|
||||
I2S Source
|
||||
|
||||
|
||||
|
||||
The ESP32-S3 is not the audio clock master.
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 8. Clock Distribution Placement
|
||||
|
||||
|
||||
The Clock Distribution Layer provides:
|
||||
|
||||
- MCLK
|
||||
- BCLK
|
||||
- LRCLK
|
||||
|
||||
|
||||
Architecture:
|
||||
|
||||
|
||||
ADAU1467
|
||||
|
||||
Audio Clock Master
|
||||
|
||||
|
|
||||
|
||||
Clock Buffer
|
||||
|
||||
|
|
||||
|
||||
+-----------+-----------+
|
||||
|
||||
| | |
|
||||
|
||||
CODEC Si4684 BT
|
||||
|
||||
|
||||
|
||||
Clock traces must have priority routing.
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 9. Routing Priorities
|
||||
|
||||
|
||||
Routing priority:
|
||||
|
||||
|
||||
1. Clock signals
|
||||
|
||||
|
||||
MCLK
|
||||
BCLK
|
||||
LRCLK
|
||||
|
||||
|
||||
|
||||
2. I2S audio buses
|
||||
|
||||
|
||||
3. SPI control
|
||||
|
||||
|
||||
4. Power distribution
|
||||
|
||||
|
||||
5. Low-speed signals
|
||||
|
||||
|
||||
Clock and audio signals must avoid:
|
||||
|
||||
- switching regulator nodes
|
||||
- RF traces
|
||||
- high current battery paths
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 10. Summary
|
||||
|
||||
|
||||
The HubAudio PCB follows the architectural separation:
|
||||
|
||||
|
||||
|
||||
CONTROL DOMAIN
|
||||
|
||||
ESP32-S3
|
||||
|
||||
SPI
|
||||
|
||||
AUDIO DOMAIN
|
||||
|
||||
ADAU1467
|
||||
|
||||
I2S
|
||||
|
||||
CLOCK DOMAIN
|
||||
|
||||
Clock Distribution
|
||||
|
||||
POWER DOMAIN
|
||||
|
||||
Battery / PMIC / Regulators
|
||||
|
||||
|
||||
|
||||
The floor plan defines a compact single-board implementation
|
||||
optimized for:
|
||||
|
||||
- portability
|
||||
- battery operation
|
||||
- audio integrity
|
||||
- future expansion
|
||||
@@ -1,294 +1,176 @@
|
||||
# HubAudio SPI Control Architecture
|
||||
# HubAudio — SPI Bus Map
|
||||
|
||||
- Status: Draft
|
||||
- Date: 2026-08-01
|
||||
- Document Type: Architecture Specification
|
||||
**Progetto:** HubAudio
|
||||
**Revisione:** definitiva
|
||||
**Data:** 2026-08-23
|
||||
|
||||
## SPI Bus Architecture
|
||||
|
||||
# 1. Overview
|
||||
HubAudio utilizza un bus SPI principale con ESP32-S31-WROOM-3 come master.
|
||||
|
||||
The HubAudio system separates the control communication layer from the audio
|
||||
signal layer.
|
||||
|
||||
SPI is used exclusively for:
|
||||
|
||||
- device configuration
|
||||
- initialization
|
||||
- status monitoring
|
||||
- firmware loading procedures
|
||||
- parameter management
|
||||
|
||||
SPI is not used for real-time audio transport.
|
||||
|
||||
|
||||
The control architecture is based on independent SPI domains.
|
||||
|
||||
|
||||
CONTROL PLANE
|
||||
|
||||
System Controller
|
||||
|
||||
System Controller
|
||||
|
||||
|
|
||||
|
|
||||
SPI Control Bus
|
||||
|
||||
+-----------+-----------+
|
||||
| |
|
||||
|
||||
Audio Processor Radio Receiver
|
||||
|
||||
Audio Processor Radio Receiver
|
||||
Il bus principale condivide:
|
||||
|
||||
- `SPI_SCLK`
|
||||
- `SPI_MOSI`
|
||||
- `SPI_MISO`
|
||||
|
||||
Ogni slave dispone di una propria linea Chip Select (`CS`).
|
||||
|
||||
---
|
||||
|
||||
# 2. System Controller Control Domain
|
||||
## SPI Main Bus
|
||||
|
||||
The System Controller is the system supervisor.
|
||||
| IC | Dispositivo | Ruolo | CS |
|
||||
|---|---|---|---|
|
||||
| U5 | XTAC5212IRGER | Audio Codec | `SPI_CODEC_CS` |
|
||||
| U34 | MCP23S17-E/ML | Device Manager A | `SPI_DEV_MAN_A_CS` |
|
||||
| U36 | MCP23S17-E/ML | Device Manager B | `SPI_DEV_MAN_B_CS` |
|
||||
| U18 | ADAU1467WBCPZ300R | Audio DSP | `SPI_ADAU1467_CS` |
|
||||
| U12 | Si4684-A10-GM | Radio | `SPI_SI4684_CS` |
|
||||
| U10 | W25Q128JVS | Flash | `SPI_W25Q128_CS` |
|
||||
| U30 | SC16IS740IPW,128 | UART Bridge | `SPI_UART_CS` |
|
||||
|
||||
Its responsibilities are:
|
||||
### Shared SPI Signals
|
||||
|
||||
- system startup
|
||||
- peripheral initialization
|
||||
- configuration management
|
||||
- communication with external devices
|
||||
- firmware update coordination
|
||||
| Segnale | Funzione |
|
||||
|---|---|
|
||||
| `SPI_SCLK` | SPI Clock |
|
||||
| `SPI_MOSI` | Master Out / Slave In |
|
||||
| `SPI_MISO` | Master In / Slave Out |
|
||||
|
||||
Il master SPI è l'**ESP32-S31-WROOM-3 (U11)**.
|
||||
|
||||
The System Controller owns the main control SPI interface.
|
||||
|
||||
System Controller
|
||||
|
||||
SPI MASTER
|
||||
|
||||
|
|
||||
+---------+---------+
|
||||
| |
|
||||
|
||||
Audio Processor Radio Receiver
|
||||
|
||||
SPI SLAVE SPI SLAVE
|
||||
|
||||
|
||||
The control bus is independent from all audio data paths.
|
||||
Le linee `SPI_SCLK`, `SPI_MOSI` e `SPI_MISO` sono condivise tra gli slave
|
||||
del bus principale.
|
||||
|
||||
Le linee `CS` sono indipendenti e vengono utilizzate per selezionare
|
||||
un singolo slave alla volta.
|
||||
|
||||
---
|
||||
|
||||
# 3. Audio Processor SPI Domain
|
||||
|
||||
The Audio Processor contains its own SPI interface for external control.
|
||||
|
||||
The System Controller uses this interface for:
|
||||
|
||||
- DSP configuration
|
||||
- parameter updates
|
||||
- operational control
|
||||
- status reading
|
||||
|
||||
|
||||
The Audio Processor also manages its external program memory.
|
||||
|
||||
Audio Processor
|
||||
|
||||
+----------------------+
|
||||
|
|
||||
| SPI MASTER
|
||||
|
|
||||
v
|
||||
|
||||
Audio EEPROM
|
||||
|
||||
DSP Program Memory
|
||||
|
||||
|
||||
The System Controller does not directly access the EEPROM during normal operation.
|
||||
|
||||
The Audio Processor is responsible for loading its DSP configuration.
|
||||
## Chip Select
|
||||
|
||||
| CS | Slave |
|
||||
|---|---|
|
||||
| `SPI_CODEC_CS` | U5 — TAC5212 |
|
||||
| `SPI_DEV_MAN_A_CS` | U34 — MCP23S17 |
|
||||
| `SPI_DEV_MAN_B_CS` | U36 — MCP23S17 |
|
||||
| `SPI_ADAU1467_CS` | U18 — ADAU1467 |
|
||||
| `SPI_SI4684_CS` | U12 — Si4684 |
|
||||
| `SPI_W25Q128_CS` | U10 — W25Q128JVS |
|
||||
| `SPI_UART_CS` | U30 — SC16IS740 |
|
||||
|
||||
---
|
||||
|
||||
# 4. Radio Receiver SPI Domain
|
||||
# Private SPI Buses
|
||||
|
||||
The Radio Receiver is controlled by the System Controller through its SPI slave interface.
|
||||
Alcuni dispositivi dispongono di una memoria SPI dedicata e non fanno
|
||||
parte del bus SPI principale dell'ESP32.
|
||||
|
||||
The System Controller manages:
|
||||
## ADAU1467 — Private SPI
|
||||
|
||||
- initialization sequence
|
||||
- command exchange
|
||||
- configuration
|
||||
- firmware loading procedure
|
||||
| Master | Slave | Dispositivo |
|
||||
|---|---|---|
|
||||
| U18 | U24 | 25AA1024-I/SM |
|
||||
|
||||
**Master:** ADAU1467
|
||||
**Slave:** 25AA1024 SPI EEPROM
|
||||
|
||||
System Controller
|
||||
|
||||
SPI MASTER
|
||||
|
||||
|
|
||||
|
||||
Radio Receiver
|
||||
|
||||
|
|
||||
|
||||
Internal Firmware Management
|
||||
|
||||
|
|
||||
|
||||
Internal RAM
|
||||
|
||||
|
||||
The Radio Receiver remains responsible for its internal operational memory.
|
||||
La memoria U24 utilizza il bus SPI privato dell'ADAU1467.
|
||||
|
||||
U24 **non** è uno slave del bus SPI principale dell'ESP32 e pertanto non
|
||||
possiede una linea `CS` appartenente al namespace `SPI_*` del bus principale.
|
||||
|
||||
---
|
||||
|
||||
# 5. SPI Bus Isolation Principle
|
||||
## Si4684 — Private SPI
|
||||
|
||||
The HubAudio architecture intentionally avoids a single shared SPI bus.
|
||||
| Master | Slave | Dispositivo |
|
||||
|---|---|---|
|
||||
| U12 | U27 | W25Q16JW |
|
||||
|
||||
The design uses:
|
||||
**Master:** Si4684
|
||||
**Slave:** W25Q16JW SPI Flash
|
||||
|
||||
System Controller
|
||||
|
||||
+-------------+
|
||||
|
||||
| |
|
||||
|
||||
SPI-A SPI-B
|
||||
|
||||
| |
|
||||
|
||||
Audio Processor Radio Receiver
|
||||
|
||||
|
||||
Advantages:
|
||||
|
||||
- no chip-select conflicts
|
||||
- independent timing
|
||||
- reduced electrical loading
|
||||
- easier firmware management
|
||||
- simpler debugging
|
||||
La memoria U27 utilizza il bus SPI privato del Si4684.
|
||||
|
||||
U27 **non** è uno slave del bus SPI principale dell'ESP32 e pertanto non
|
||||
possiede una linea `CS` appartenente al namespace `SPI_*` del bus principale.
|
||||
|
||||
---
|
||||
|
||||
# 6. Boot Sequence
|
||||
# SPI Topology
|
||||
|
||||
The expected startup sequence is:
|
||||
```text
|
||||
ESP32-S31-WROOM-3
|
||||
U11
|
||||
│
|
||||
┌─────────────┼─────────────┐
|
||||
│ │ │
|
||||
SPI_SCLK SPI_MOSI SPI_MISO
|
||||
│ │ │
|
||||
┌─────────┴─────────────┴─────────────┴─────────┐
|
||||
│ SPI MAIN BUS │
|
||||
│ │
|
||||
├── U5 TAC5212 ← SPI_CODEC_CS │
|
||||
├── U34 MCP23S17 ← SPI_DEV_MAN_A_CS │
|
||||
├── U36 MCP23S17 ← SPI_DEV_MAN_B_CS │
|
||||
├── U18 ADAU1467 ← SPI_ADAU1467_CS │
|
||||
├── U12 Si4684 ← SPI_SI4684_CS │
|
||||
├── U10 W25Q128JVS ← SPI_W25Q128_CS │
|
||||
└── U30 SC16IS740 ← SPI_UART_CS │
|
||||
│
|
||||
└────────────────────────────────────────────────┘
|
||||
|
||||
|
||||
PRIVATE SPI BUS PRIVATE SPI BUS
|
||||
ADAU1467 Si4684
|
||||
U18 U12
|
||||
│ │
|
||||
│ SPI │ SPI
|
||||
▼ ▼
|
||||
U24 25AA1024 U27 W25Q16JW
|
||||
SPI Slave Summary
|
||||
Bus Master Slave Device
|
||||
Main SPI ESP32 U11 U5 TAC5212
|
||||
Main SPI ESP32 U11 U34 MCP23S17
|
||||
Main SPI ESP32 U11 U36 MCP23S17
|
||||
Main SPI ESP32 U11 U18 ADAU1467
|
||||
Main SPI ESP32 U11 U12 Si4684
|
||||
Main SPI ESP32 U11 U10 W25Q128JVS
|
||||
Main SPI ESP32 U11 U30 SC16IS740
|
||||
Private SPI ADAU1467 U18 U24 25AA1024
|
||||
Private SPI Si4684 U12 U27 W25Q16JW
|
||||
Design Rules
|
||||
SPI_SCLK, SPI_MOSI e SPI_MISO del bus principale sono condivisi tra
|
||||
tutti gli slave del bus.
|
||||
Ogni slave del bus principale deve avere una propria linea CS.
|
||||
Deve essere attivo un solo CS alla volta durante una transazione SPI.
|
||||
U24 e U27 non appartengono al bus SPI principale.
|
||||
U24 è controllata direttamente dall'ADAU1467.
|
||||
U27 è controllata direttamente dal Si4684.
|
||||
I Chip Select dei bus privati non devono essere confusi con i CS
|
||||
del bus SPI principale dell'ESP32.
|
||||
La nomenclatura SPI_*_CS identifica esclusivamente le linee Chip Select
|
||||
del bus SPI principale.
|
||||
Main SPI Chip Select Map
|
||||
SPI_CODEC_CS → U5 TAC5212
|
||||
SPI_DEV_MAN_A_CS → U34 MCP23S17
|
||||
SPI_DEV_MAN_B_CS → U36 MCP23S17
|
||||
SPI_ADAU1467_CS → U18 ADAU1467
|
||||
SPI_SI4684_CS → U12 Si4684
|
||||
SPI_W25Q128_CS → U10 W25Q128JVS
|
||||
SPI_UART_CS → U30 SC16IS740
|
||||
Stato
|
||||
|
||||
Power ON
|
||||
SPI principale: 7 slave.
|
||||
|
||||
|
|
||||
SPI privato ADAU1467: 1 slave.
|
||||
|
||||
System Controller boot
|
||||
SPI privato Si4684: 1 slave.
|
||||
|
||||
|
|
||||
Totale dispositivi SPI: 9.
|
||||
|
||||
Initialize SPI buses
|
||||
Master SPI principale: ESP32-S31-WROOM-3.
|
||||
|
||||
|
|
||||
|
||||
Configure Audio Processor
|
||||
|
||||
|
|
||||
+--> ADAU loads DSP program from Audio EEPROM
|
||||
|
||||
|
|
||||
|
||||
Configure Radio Receiver
|
||||
|
||||
|
|
||||
+--> Firmware initialization
|
||||
|
||||
|
|
||||
|
||||
Enable Audio Domain
|
||||
|
||||
|
|
||||
|
||||
Audio Processor starts audio processing
|
||||
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 7. Separation Between Domains
|
||||
|
||||
|
||||
## Control Domain
|
||||
|
||||
|
||||
System Controller
|
||||
|
||||
|
|
||||
|
|
||||
|
||||
SPI
|
||||
|
||||
|
|
||||
|
||||
Peripheral configuration
|
||||
|
||||
|
||||
|
||||
## Audio Domain
|
||||
|
||||
|
||||
Audio Sources
|
||||
|
||||
|
|
||||
|
|
||||
|
||||
I2S
|
||||
|
||||
|
|
||||
|
||||
Audio Processor
|
||||
|
||||
|
|
||||
|
||||
Audio Outputs
|
||||
|
||||
|
||||
|
||||
The two domains interact only through configuration and status information.
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 8. Design Rules
|
||||
|
||||
SPI signals require:
|
||||
|
||||
- controlled routing
|
||||
- clean reference plane
|
||||
- appropriate termination where required
|
||||
- separation from high-speed clock signals
|
||||
|
||||
|
||||
Critical signals:
|
||||
|
||||
- SCLK
|
||||
- MOSI
|
||||
- MISO
|
||||
- CS
|
||||
|
||||
|
||||
---
|
||||
|
||||
# 9. Design Philosophy
|
||||
|
||||
The System Controller is the system coordinator.
|
||||
|
||||
The Audio Processor is the audio processor.
|
||||
|
||||
The Radio Receiver is a specialized audio peripheral.
|
||||
|
||||
Each component controls its own functional domain while remaining part of the
|
||||
complete HubAudio system.
|
||||
Master SPI privati: ADAU1467 e Si4684.
|
||||
|
||||
@@ -0,0 +1,96 @@
|
||||
# HubAudio — I²C Bus Map
|
||||
|
||||
**Progetto:** HubAudio
|
||||
**Revisione:** definitiva
|
||||
**Data:** 2026-08-23
|
||||
|
||||
## Dispositivi I²C
|
||||
|
||||
| IC | Componente | Configurazione indirizzo | Indirizzo I²C (7-bit) |
|
||||
|---|---|---|---:|
|
||||
| U1 | BQ25896RTWR | Indirizzo fisso | `0x6B` |
|
||||
| U2 | BQ27441DRZR-G1B | Indirizzo fisso | `0x55` |
|
||||
| U4 | INA228AQDGSRQ1 | A0 = 0, A1 = 0 | `0x40` |
|
||||
| U8 | INA228AQDGSRQ1 | A0 = 0, A1 = 1 | `0x41` |
|
||||
| U17 | 24AA025E64 | A2 = 0, A1 = 0, A0 = 0 | `0x50` |
|
||||
| U20 | TPS22994RUKT | ADDR3 = 0, ADDR2 = 0, ADDR1 = 0 | `0x20` |
|
||||
| U23 | TPS22994RUKT | ADDR3 = 0, ADDR2 = 0, ADDR1 = 1 | `0x21` |
|
||||
| U31 | TMP117NAIDRVR | ADDR = GND | `0x48` |
|
||||
| U32 | TMP117NAIDRVR | ADDR = VCC | `0x49` |
|
||||
| U33 | TMP117NAIDRVR | ADDR = SDA | `0x4A` |
|
||||
| U37 | TMP117NAIDRVR | ADDR = SCL | `0x4B` |
|
||||
|
||||
## Address Map
|
||||
|
||||
| Indirizzo | IC | Dispositivo |
|
||||
|---:|---|---|
|
||||
| `0x20` | U20 | TPS22994 |
|
||||
| `0x21` | U23 | TPS22994 |
|
||||
| `0x40` | U4 | INA228 — Analog |
|
||||
| `0x41` | U8 | INA228 — Digital |
|
||||
| `0x48` | U31 | TMP117 — Power |
|
||||
| `0x49` | U32 | TMP117 — ESP32 |
|
||||
| `0x4A` | U33 | TMP117 — DSP |
|
||||
| `0x4B` | U37 | TMP117 — Codec |
|
||||
| `0x50` | U17 | 24AA025E64 |
|
||||
| `0x55` | U2 | BQ27441 |
|
||||
| `0x6B` | U1 | BQ25896 |
|
||||
|
||||
## TMP117
|
||||
|
||||
I quattro TMP117 utilizzano tutte le quattro configurazioni disponibili del
|
||||
pin `ADDR`:
|
||||
|
||||
- **U31 — Power:** `ADDR → GND` → `0x48`
|
||||
- **U32 — ESP32:** `ADDR → VCC` → `0x49`
|
||||
- **U33 — DSP:** `ADDR → SDA` → `0x4A`
|
||||
- **U37 — Codec:** `ADDR → SCL` → `0x4B`
|
||||
|
||||
Ogni TMP117 dispone di un condensatore di bypass locale da **100 nF**.
|
||||
|
||||
## INA228
|
||||
|
||||
- **U4 — Analog:** A0 = 0, A1 = 0 → `0x40`
|
||||
- **U8 — Digital:** A0 = 0, A1 = 1 → `0x41`
|
||||
|
||||
## TPS22994
|
||||
|
||||
- **U20:** ADDR3 = 0, ADDR2 = 0, ADDR1 = 0 → `0x20`
|
||||
- **U23:** ADDR3 = 0, ADDR2 = 0, ADDR1 = 1 → `0x21`
|
||||
|
||||
## EEPROM
|
||||
|
||||
**U17 — 24AA025E64**
|
||||
|
||||
```text
|
||||
A2 = GND
|
||||
A1 = GND
|
||||
A0 = GND
|
||||
|
||||
→ 0x50
|
||||
|
||||
Indirizzi fissi
|
||||
|
||||
U1 — BQ25896: 0x6B
|
||||
|
||||
U2 — BQ27441: 0x55
|
||||
|
||||
Verifica collisioni
|
||||
|
||||
Non risultano collisioni tra gli indirizzi I²C assegnati.
|
||||
|
||||
Totale dispositivi I²C: 11
|
||||
|
||||
Indirizzi utilizzati: 11
|
||||
|
||||
0x20
|
||||
0x21
|
||||
0x40
|
||||
0x41
|
||||
0x48
|
||||
0x49
|
||||
0x4A
|
||||
0x4B
|
||||
0x50
|
||||
0x55
|
||||
0x6B
|
||||
@@ -0,0 +1,9 @@
|
||||
# KiCad lock / temporary files
|
||||
*.lck
|
||||
*.kicad_prl
|
||||
|
||||
# KiCad history
|
||||
.history/
|
||||
|
||||
# KiCad automatic restore/backup directories
|
||||
_restore_backup_*/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,962 @@
|
||||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"apply_defaults_to_fp_barcodes": false,
|
||||
"apply_defaults_to_fp_dimensions": false,
|
||||
"apply_defaults_to_fp_fields": false,
|
||||
"apply_defaults_to_fp_shapes": false,
|
||||
"apply_defaults_to_fp_text": false,
|
||||
"board_outline_line_width": 0.05,
|
||||
"copper_line_width": 0.2,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.05,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": true,
|
||||
"text_position": 0,
|
||||
"units_format": 0
|
||||
},
|
||||
"fab_line_width": 0.1,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.1,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 2.2,
|
||||
"height": 2.2,
|
||||
"width": 2.2
|
||||
},
|
||||
"silk_line_width": 0.1,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.1,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"border_display_style": 2,
|
||||
"border_hatch_pitch": 0.5,
|
||||
"corner_radius": 0.0,
|
||||
"corner_smoothing": 0,
|
||||
"fill_mode": 0,
|
||||
"hatch_gap": 1.5,
|
||||
"hatch_orientation": 0.0,
|
||||
"hatch_smoothing_level": 0,
|
||||
"hatch_smoothing_value": 0.1,
|
||||
"hatch_thickness": 1.0,
|
||||
"min_clearance": 0.0,
|
||||
"min_island_area": 10.0,
|
||||
"min_thickness": 0.25,
|
||||
"pad_connection": 1,
|
||||
"remove_islands": 0,
|
||||
"thermal_relief_gap": 0.5,
|
||||
"thermal_relief_spoke_width": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"creepage": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_filters_mismatch": "ignore",
|
||||
"footprint_symbol_field_mismatch": "warning",
|
||||
"footprint_symbol_mismatch": "warning",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_to_hole": "warning",
|
||||
"holes_co_located": "warning",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"mirrored_text_on_front_layer": "warning",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"missing_tuning_profile": "warning",
|
||||
"net_conflict": "warning",
|
||||
"nonmirrored_text_on_back_layer": "warning",
|
||||
"npth_inside_courtyard": "error",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "error",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
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||||
"text_on_edge_cuts": "error",
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||||
"text_thickness": "warning",
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||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_angle": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_not_centered_on_via": "ignore",
|
||||
"track_on_post_machined_layer": "error",
|
||||
"track_segment_length": "error",
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||||
"track_width": "error",
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||||
"tracks_crossing": "error",
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||||
"tuning_profile_track_geometries": "ignore",
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||||
"unconnected_items": "error",
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||||
"unresolved_variable": "error",
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||||
"via_dangling": "warning",
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||||
"zones_intersect": "error"
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||||
},
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||||
"rules": {
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||||
"max_error": 0.005,
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||||
"min_clearance": 0.0,
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||||
"min_connection": 0.0,
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||||
"min_copper_edge_clearance": 0.5,
|
||||
"min_groove_width": 0.0,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
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||||
"min_microvia_diameter": 0.2,
|
||||
"min_microvia_drill": 0.1,
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||||
"min_resolved_spokes": 2,
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||||
"min_silk_clearance": 0.0,
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||||
"min_text_height": 0.8,
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||||
"min_text_thickness": 0.08,
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||||
"min_through_hole_diameter": 0.3,
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||||
"min_track_width": 0.2,
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||||
"min_via_annular_width": 0.1,
|
||||
"min_via_diameter": 0.5,
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||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
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||||
},
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||||
"teardrop_options": [
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||||
{
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||||
"td_onpthpad": true,
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||||
"td_onroundshapesonly": false,
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||||
"td_onsmdpad": true,
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||||
"td_ontrackend": false,
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||||
"td_onvia": true
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||||
}
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||||
],
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||||
"teardrop_parameters": [
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||||
{
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||||
"td_allow_use_two_tracks": true,
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||||
"td_curve_segcount": 0,
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||||
"td_height_ratio": 1.0,
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||||
"td_length_ratio": 0.5,
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||||
"td_maxheight": 2.0,
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||||
"td_maxlen": 1.0,
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||||
"td_on_pad_in_zone": false,
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||||
"td_target_name": "td_round_shape",
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||||
"td_width_to_size_filter_ratio": 0.9
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||||
},
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||||
{
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||||
"td_allow_use_two_tracks": true,
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||||
"td_curve_segcount": 0,
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||||
"td_height_ratio": 1.0,
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||||
"td_length_ratio": 0.5,
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||||
"td_maxheight": 2.0,
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||||
"td_maxlen": 1.0,
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||||
"td_on_pad_in_zone": false,
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||||
"td_target_name": "td_rect_shape",
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||||
"td_width_to_size_filter_ratio": 0.9
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||||
},
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||||
{
|
||||
"td_allow_use_two_tracks": true,
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||||
"td_curve_segcount": 0,
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||||
"td_height_ratio": 1.0,
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||||
"td_length_ratio": 0.5,
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||||
"td_maxheight": 2.0,
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||||
"td_maxlen": 1.0,
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||||
"td_on_pad_in_zone": false,
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||||
"td_target_name": "td_track_end",
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||||
"td_width_to_size_filter_ratio": 0.9
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||||
}
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||||
],
|
||||
"track_widths": [],
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||||
"tuning_pattern_settings": {
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||||
"diff_pair_defaults": {
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||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
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||||
"spacing": 1.0
|
||||
},
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||||
"diff_pair_skew_defaults": {
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||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
},
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||||
"single_track_defaults": {
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||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
}
|
||||
},
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"ipc2581": {
|
||||
"bom_rev": "",
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": "",
|
||||
"sch_revision": ""
|
||||
},
|
||||
"layer_pairs": [],
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"component_class_settings": {
|
||||
"assignments": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
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||||
"sheet_component_classes": {
|
||||
"enabled": false
|
||||
}
|
||||
},
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [
|
||||
[
|
||||
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||||
""
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||||
],
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||||
[
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||||
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||||
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[
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||||
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||||
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||||
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||||
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||||
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""
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
[
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
(type solid)
|
||||
)
|
||||
(fill
|
||||
(color 0 0 0 0)
|
||||
)
|
||||
(uuid "e2542609-1b92-4554-8024-978841ad00fe")
|
||||
(property "Sheetname" "DeviceManager"
|
||||
(at 85.09 102.1584 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left bottom)
|
||||
)
|
||||
)
|
||||
(property "Sheetfile" "device-manager.kicad_sch"
|
||||
(at 85.09 127.5846 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left top)
|
||||
)
|
||||
)
|
||||
(instances
|
||||
(project "HubAudio"
|
||||
(path "/841d8022-3a94-443e-97aa-a99a12889684"
|
||||
(page "13")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(sheet
|
||||
(at 186.69 25.4)
|
||||
(size 39.37 24.13)
|
||||
(exclude_from_sim no)
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(dnp no)
|
||||
(fields_autoplaced yes)
|
||||
(stroke
|
||||
(width 0.1524)
|
||||
(type solid)
|
||||
)
|
||||
(fill
|
||||
(color 0 0 0 0)
|
||||
)
|
||||
(uuid "f8fd2832-13ed-4270-9e98-2ba7eddd8eec")
|
||||
(property "Sheetname" "Main Controller"
|
||||
(at 186.69 24.6884 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left bottom)
|
||||
)
|
||||
)
|
||||
(property "Sheetfile" "main-controller.kicad_sch"
|
||||
(at 186.69 50.1146 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left top)
|
||||
)
|
||||
)
|
||||
(instances
|
||||
(project "HubAudio"
|
||||
(path "/841d8022-3a94-443e-97aa-a99a12889684"
|
||||
(page "5")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(sheet_instances
|
||||
(path "/"
|
||||
(page "1")
|
||||
)
|
||||
)
|
||||
(embedded_fonts no)
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Executable
+177
@@ -0,0 +1,177 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import csv
|
||||
import sys
|
||||
from pathlib import Path
|
||||
|
||||
|
||||
def norm(value):
|
||||
return (value or "").strip().strip('"').strip()
|
||||
|
||||
|
||||
def read_kicad_bom(path):
|
||||
with open(path, "r", encoding="utf-8-sig", newline="") as f:
|
||||
return list(csv.DictReader(f))
|
||||
|
||||
|
||||
def read_lcsc_export(path):
|
||||
with open(path, "r", encoding="utf-8-sig", newline="") as f:
|
||||
lines = f.readlines()
|
||||
|
||||
header = None
|
||||
|
||||
for i, line in enumerate(lines):
|
||||
if line.startswith("LCSC#;"):
|
||||
header = i
|
||||
break
|
||||
|
||||
if header is None:
|
||||
raise RuntimeError("Non trovo la sezione 'LCSC Matching Results'.")
|
||||
|
||||
return list(
|
||||
csv.DictReader(
|
||||
lines[header:],
|
||||
delimiter=";"
|
||||
)
|
||||
)
|
||||
|
||||
|
||||
def build_lcsc_map(rows):
|
||||
result = {}
|
||||
|
||||
for row in rows:
|
||||
mpn = norm(row.get("Mrf#", ""))
|
||||
lcsc = norm(row.get("LCSC#", ""))
|
||||
status = norm(row.get("Matched status", ""))
|
||||
url = norm(row.get("Product Link", ""))
|
||||
|
||||
if not mpn:
|
||||
continue
|
||||
|
||||
# IMPORTANTE:
|
||||
# accettiamo automaticamente solo Exact Matches
|
||||
if status == "Exact Matches" and lcsc:
|
||||
result[mpn] = {
|
||||
"lcsc": lcsc,
|
||||
"status": status,
|
||||
"url": url,
|
||||
}
|
||||
|
||||
return result
|
||||
|
||||
|
||||
def main():
|
||||
|
||||
if len(sys.argv) != 3:
|
||||
print()
|
||||
print("Uso:")
|
||||
print(
|
||||
" python3 add_lcsc_to_bom.py "
|
||||
"HubAudio.csv export_project_20260822_065729.csv"
|
||||
)
|
||||
print()
|
||||
sys.exit(1)
|
||||
|
||||
bom_file = Path(sys.argv[1])
|
||||
lcsc_file = Path(sys.argv[2])
|
||||
|
||||
if not bom_file.exists():
|
||||
print(f"ERRORE: BOM non trovata: {bom_file}")
|
||||
sys.exit(1)
|
||||
|
||||
if not lcsc_file.exists():
|
||||
print(f"ERRORE: export LCSC non trovato: {lcsc_file}")
|
||||
sys.exit(1)
|
||||
|
||||
print("Leggo BOM KiCad...")
|
||||
bom = read_kicad_bom(bom_file)
|
||||
|
||||
print("Leggo export LCSC...")
|
||||
lcsc_rows = read_lcsc_export(lcsc_file)
|
||||
|
||||
lcsc_map = build_lcsc_map(lcsc_rows)
|
||||
|
||||
# Manteniamo tutte le colonne originali di KiCad
|
||||
columns = list(bom[0].keys())
|
||||
|
||||
for column in [
|
||||
"LCSC#",
|
||||
"LCSC_Status",
|
||||
"LCSC_URL",
|
||||
]:
|
||||
if column not in columns:
|
||||
columns.append(column)
|
||||
|
||||
exact = 0
|
||||
missing = 0
|
||||
|
||||
for row in bom:
|
||||
|
||||
# Prima scelta: PNM
|
||||
mpn = norm(row.get("PNM", ""))
|
||||
|
||||
# Fallback: Value
|
||||
if not mpn:
|
||||
mpn = norm(row.get("Value", ""))
|
||||
|
||||
match = lcsc_map.get(mpn)
|
||||
|
||||
if match:
|
||||
|
||||
row["LCSC#"] = match["lcsc"]
|
||||
row["LCSC_Status"] = "Exact Matches"
|
||||
row["LCSC_URL"] = match["url"]
|
||||
|
||||
exact += 1
|
||||
|
||||
else:
|
||||
|
||||
row["LCSC#"] = ""
|
||||
row["LCSC_Status"] = ""
|
||||
row["LCSC_URL"] = ""
|
||||
|
||||
missing += 1
|
||||
|
||||
output = bom_file.with_name(
|
||||
bom_file.stem + "_Pinscope_BOM.csv"
|
||||
)
|
||||
|
||||
with open(
|
||||
output,
|
||||
"w",
|
||||
encoding="utf-8-sig",
|
||||
newline=""
|
||||
) as f:
|
||||
|
||||
writer = csv.DictWriter(
|
||||
f,
|
||||
fieldnames=columns,
|
||||
quoting=csv.QUOTE_ALL
|
||||
)
|
||||
|
||||
writer.writeheader()
|
||||
writer.writerows(bom)
|
||||
|
||||
print()
|
||||
print("=" * 50)
|
||||
print(" LCSC → PINSCOPE BOM")
|
||||
print("=" * 50)
|
||||
print()
|
||||
print(f"BOM originale : {bom_file.name}")
|
||||
print(f"Export LCSC : {lcsc_file.name}")
|
||||
print(f"Output : {output.name}")
|
||||
print()
|
||||
print(f"Righe BOM : {len(bom)}")
|
||||
print(f"Exact Match : {exact}")
|
||||
print(f"Senza LCSC : {missing}")
|
||||
print()
|
||||
print("Solo 'Exact Matches' sono stati accettati.")
|
||||
print("Partial Matches NON sono stati inseriti.")
|
||||
print("No Matches NON sono stati inseriti.")
|
||||
print()
|
||||
print(f"FILE CREATO: {output}")
|
||||
print()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,4 @@
|
||||
(sym_lib_table
|
||||
(version 7)
|
||||
(lib (name "HubAudio") (type "KiCad") (uri "/Users/michelebigi/Development/HubAudio/hardware/kicad/HubAudio/") (options "") (descr ""))
|
||||
)
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user