schema completato

README.md

@@ -1,2 +1,151 @@
-# HubAudio# HubAudio
 # HubAudio
+
+## Professional Embedded Audio Platform
+
+HubAudio is a modular embedded audio platform designed around a clear separation of hardware domains:
+
+- System control
+- Audio processing
+- Digital radio
+- Wireless audio
+- Clock management
+- Power management
+
+The primary design objective is maintainability.
+
+The architecture follows the principle:
+
+> Code and hardware design must fit in the engineer's head.
+
+Complexity is introduced only when it provides a measurable improvement in reliability, flexibility or performance.
+
+---
+
+# Project Goals
+
+HubAudio is intended to provide:
+
+- High quality digital audio routing
+- Multiple audio sources and destinations
+- Expandable DSP processing
+- Robust embedded operation
+- Professional PCB architecture
+- Long-term maintainability
+
+---
+
+# Core Architecture
+
+## Main Domains
+
+                SYSTEM DOMAIN
+
+                ESP32-S3
+                   |
+          Control / Network / UI
+                   |
+                   |
+            AUDIO CONTROL BUS
+
+
+                AUDIO DOMAIN
+
+               ADAU1467
+
+    +-------------+-------------+
+    |             |             |
+  I2S          SPDIF        Bluetooth
+    |             |             |
+Si4684        IO Codec      BT Module
+ Radio
+
+---
+
+# Hardware Philosophy
+
+The system is divided into independent domains:
+
+## System Domain
+
+Responsible for:
+
+- Connectivity
+- User interface
+- Configuration
+- Network services
+- OTA updates
+
+Main component:
+
+- ESP32-S3
+
+
+## Audio Domain
+
+Responsible for:
+
+- Routing
+- DSP processing
+- Mixing
+- Sample rate management
+
+Main component:
+
+- Analog Devices ADAU1467
+
+
+## RF Domain
+
+Responsible for:
+
+- Digital radio reception
+- Wireless communication
+
+
+## Power Domain
+
+Responsible for:
+
+- Battery operation
+- USB power
+- Voltage regulation
+- Monitoring
+
+
+---
+
+# Repository Structure
+
+
+HubAudio/
+
+├── docs/
+│
+├── hardware/
+│
+├── firmware/
+│
+├── simulation/
+│
+├── research/
+│
+└── tools/
+
+
+---
+
+# Design Rules
+
+1. Prefer simple architectures.
+2. Avoid unnecessary abstraction.
+3. Separate noisy and sensitive domains.
+4. Document every architectural decision.
+5. Choose components for lifecycle, not only price.
+
+---
+
+# Status
+
+Architecture phase.
+
+Hardware implementation follows documented decisions.

docs/adr/ADR-001-ADAU1467-Audio-Domain-Master.md

@@ -37,13 +37,14 @@ The  Audio Processor is responsible for:
 - audio clock generation
 - synchronization of external audio peripherals
 
-The  Audio Processor is considered the audio domain master.
+The Audio Processor is the sole timing and routing master of the Audio Domain.
 
 The System Controller participates in the Audio Domain as a digital audio source. It does not act as the audio timing master or routing controller. Its role inside the audio domain is equivalent to other digital audio sources.
+
 The System Controller has a dual role:
 
 - audio source inside the Audio Domain
-system supervisor inside the Control Domain
+- system supervisor inside the Control Domain
 
 It operates as system supervisor and is responsible for:
 

docs/adr/ADR-002-SPI-Control-Architecture.md

@@ -23,7 +23,7 @@ audio transport interface.
 
 ## Decision
 
-The SPI architecture is divided into independent functional domains.
+The SPI architecture is divided into independent control domains.
 
 The System Controller operates as the master of the system control SPI bus.
 
@@ -88,8 +88,7 @@ commands exchanged on the external SPI control interface.
 
          Internal RAM
 
-The System Controller controls the initialization process but does not directly access
+The System Controller supervises the Radio Receiver initialization process. Internal firmware loading remains under the responsibility of the Radio Receiver boot architecture.
-the internal operational memory of the Radio Receiver.
 
 ## Consequences
 

docs/adr/ADR-003-I2S-Audio-Routing-Architecture.md

@@ -41,13 +41,15 @@ External audio devices operate as I2S slaves whenever supported.
 
 ## Audio Input Allocation
 
-| Audio Processor Port | Device | Function |
+|| Audio Processor Input | Device | Function |
 |---|---|---|
 | SDATA_IN0 | System Controller | Network audio stream |
 | SDATA_IN1 | Radio Receiver | Radio audio |
-| SDATA_IN2 | DECODEC | Optical digital input |
+| SPDIFIN | Optical Interface | Optical digital audio input |
-| SDATA_IN3 | Bluetooth RX | Wireless audio input |
+| SDATA_IN2 | Bluetooth RX | Wireless audio input |
 
+The ADAU1467 internal audio routing matrix allows any digital audio input
+to be routed to the DSP core, ASRCs, serial outputs or SPDIF output.
 
 System Controller --------
 Radio Receiver ---------
@@ -57,11 +59,13 @@ BT RX ---------/
 
 ## Audio Output Allocation
 
-| Audio Processor Port | Device | Function |
+## Audio Output Allocation
+
+| Audio Processor Output | Device | Function |
 |---|---|---|
 | SDATA_OUT0 | CODEC/DAC | Analog audio output |
 | SDATA_OUT1 | Bluetooth TX | Wireless audio output |
-| SDATA_OUT2 | ENCODEC | Optical digital output |
+| SPDIFOUT | Optical Interface | Optical digital audio output |
 | SDATA_OUT3 | Reserved | Future expansion |
 
              Audio Processor

docs/adr/ADR-004-Power-Domain-Architecture.md

@@ -1,7 +1,7 @@
 # ADR-004 – Power Domain Architecture
 
 - **Status:** Accepted
-- **Date:** YYYY-MM-DD
+- **Date:** 2026-08-02
 
 # Context
 

docs/architecture/HubAudio-PCB-Floor-Plan.md

@@ -0,0 +1,506 @@
+# HubAudio PCB Floor Plan
+
+- Status: Draft
+- Date: 2026-08-01
+- Document Type: Hardware Architecture
+
+
+# 1. Overview
+
+This document defines the preliminary PCB floor plan for the HubAudio
+single-board audio platform.
+
+The PCB integrates:
+
+- System Controller
+- Audio Processor
+- Radio Receiver
+- Wireless Audio Interfaces
+- Digital Audio Interfaces
+- Power Management
+- Battery Operation Support
+
+
+The floor plan follows the fundamental HubAudio architecture:
+
+
+ESP32-S3 manages the Control Domain.
+
+ADAU1467 manages the Audio Domain.
+
+The Clock Distribution Layer provides synchronization
+for digital audio peripherals.
+
+
+The PCB layout must preserve separation between:
+
+- Control Domain
+- Audio Domain
+- Clock Domain
+- Power Domain
+
+
+The objective is to create a compact portable audio platform while
+maintaining:
+
+- audio signal integrity
+- clock stability
+- RF performance
+- power efficiency
+- battery operation capability
+
+
+---
+
+# 2. PCB Constraints
+
+
+## 2.1 Target Dimensions
+
+
+The HubAudio board is designed as a compact single-board platform.
+
+
+Preferred PCB size:
+Layer 1
+Component placement
+Critical digital signals
+Audio routing
+
+Layer 2
+Continuous GND plane
+
+Layer 3
+Power distribution
+
+Layer 4
+Control signals
+Low speed routing
+Auxiliary signals
+
+
+A 6-layer PCB remains an optional evolution only if required after
+routing verification.
+
+
+The transition to 6 layers must be justified by:
+
+- routing density
+- clock integrity
+- RF isolation requirements
+- power distribution constraints
+
+
+The initial architecture target remains:
+4 Layer PCB
+
+
+---
+
+# 4. Functional PCB Zones
+
+
+The PCB is divided into five functional areas.
+
+
+## 4.1 Control Zone
+
+
+Contains:
+
+- ESP32-S3
+- USB interface
+- programming interface
+- user interface connections
+
+
+Responsibilities:
+
+- network connectivity
+- streaming control
+- configuration management
+- firmware updates
+
+
+Placement requirements:
+
+- close to PCB edge
+- antenna clearance
+- separated from switching regulators
+
+
+---
+
+## 4.2 Audio Processing Zone
+
+
+Contains:
+
+- ADAU1467
+- Audio EEPROM
+- Clock circuitry
+- Audio domain support components
+
+
+The ADAU1467 is the physical center of the Audio Domain.
+
+
+Responsibilities:
+
+- DSP processing
+- routing
+- mixing
+- synchronization
+
+
+Critical signals:
+
+- MCLK
+- BCLK
+- LRCLK
+- I2S DATA
+
+
+must remain short.
+
+
+---
+
+## 4.3 Radio Zone
+
+
+Contains:
+
+- Si4684
+- RF interface
+- antenna related components
+
+
+Placement requirements:
+
+- close to RF input
+- separated from switching noise
+- local power filtering
+
+
+The Si4684 operates as a digital audio peripheral
+inside the Audio Domain.
+
+
+---
+
+## 4.4 Audio Interface Zone
+
+
+Contains:
+
+- Bluetooth interfaces
+- Optical interfaces
+- CODEC/DAC stages
+
+
+Interfaces:
+I2S
+|
+ADAU1467
+
+
+Placement requirements:
+
+- close to PCB edge
+- short I2S paths
+- controlled supply filtering
+
+
+---
+
+## 4.5 Power Zone
+
+
+Contains:
+
+- Battery input
+- USB power input
+- Charger
+- PMIC
+- Regulators
+- Filtering components
+
+
+Placement:
+
+PCB edge area
+
+
+Power path:
+
+Battery / USB
+
+  |
+
+Protection
+
+  |
+
+Charger
+
+  |
+
+PMIC
+
+  |
+
+Regulators
+
+  |
+
+Digital / Analog domains
+
+
+
+The Power Zone must remain physically separated from:
+
+- clock circuitry
+- RF section
+- sensitive audio signals
+
+
+---
+
+# 5. Preliminary Floor Plan
+
+
+Conceptual arrangement:
+
+
+
++--------------------------------+
+| |
+| ESP32-S3 Si4684 |
+| CONTROL RADIO |
+| |
+| |
+| CLOCK |
+| BUFFER |
+| | |
+| | |
+| ADAU1467 |
+| AUDIO PROCESSOR |
+| |
+| |
+| BT RX SPDIF CODEC BT TX |
+| AUDIO INTERFACE |
+
+
+
+BATTERY / PMIC / CHARGER
+POWER DOMAIN
+
++--------------------------------+
+
+PCB TARGET:
+
+90 mm x 70 mm
+
+
+
+This arrangement keeps the ADAU1467 physically central.
+
+The placement minimizes:
+
+- I2S length
+- clock distribution length
+- audio routing complexity
+
+
+---
+
+# 6. ADAU1467 Placement
+
+
+The ADAU1467 is the physical center of the digital audio subsystem.
+
+
+This follows the architecture decision:
+
+
+
+ADAU1467 = Audio Domain Master
+
+
+
+Placement rules:
+
+- central PCB position
+- shortest clock paths
+- shortest I2S paths
+- local decoupling network
+- separated from switching regulators
+
+
+The ADAU1467 area includes:
+
+- DSP processor
+- clock interface
+- SPI configuration interface
+- audio EEPROM
+
+
+Critical signals:
+
+
+MCLK
+BCLK
+LRCLK
+I2S DATA
+
+
+
+must be routed with priority.
+
+
+---
+
+# 7. ESP32-S3 Placement
+
+
+The ESP32-S3 belongs to the Control Domain.
+
+
+Placement rules:
+
+- PCB edge placement
+- antenna keep-out area
+- USB accessibility
+- separation from analog audio
+
+
+The ESP32-S3 interfaces:
+
+Control:
+
+
+SPI
+
+
+
+Audio:
+
+
+I2S Source
+
+
+
+The ESP32-S3 is not the audio clock master.
+
+
+---
+
+# 8. Clock Distribution Placement
+
+
+The Clock Distribution Layer provides:
+
+- MCLK
+- BCLK
+- LRCLK
+
+
+Architecture:
+
+
+         ADAU1467
+
+      Audio Clock Master
+
+             |
+
+      Clock Buffer
+
+             |
+
+ +-----------+-----------+
+
+ |           |           |
+
+CODEC Si4684 BT
+
+
+
+Clock traces must have priority routing.
+
+
+---
+
+# 9. Routing Priorities
+
+
+Routing priority:
+
+
+1. Clock signals
+
+
+MCLK
+BCLK
+LRCLK
+
+
+
+2. I2S audio buses
+
+
+3. SPI control
+
+
+4. Power distribution
+
+
+5. Low-speed signals
+
+
+Clock and audio signals must avoid:
+
+- switching regulator nodes
+- RF traces
+- high current battery paths
+
+
+---
+
+# 10. Summary
+
+
+The HubAudio PCB follows the architectural separation:
+
+
+
+CONTROL DOMAIN
+
+ESP32-S3
+
+    SPI
+
+AUDIO DOMAIN
+
+ADAU1467
+
+    I2S
+
+CLOCK DOMAIN
+
+Clock Distribution
+
+POWER DOMAIN
+
+Battery / PMIC / Regulators
+
+
+
+The floor plan defines a compact single-board implementation
+optimized for:
+
+- portability
+- battery operation
+- audio integrity
+- future expansion

docs/architecture/I2C-Addressing

@@ -0,0 +1,13 @@
+# Tabella Indirizzi I2C
+
+| Dispositivo       | Funzione / Nome   | Configurazione Pin Indirizzo   | Indirizzo I2C (Hex)   |
+|:------------------|:------------------|:-------------------------------|:----------------------|
+| TCA9555 #1        | POWER_CONTROLLER  | A2=GND, A1=GND, A0=GND         | 0x20                  |
+| TCA9555 #2        | AUDIO_CONTROL     | A2=GND, A1=GND, A0=VCC         | 0x21                  |
+| INA228            | DIGITAL           | A1=GND, A0=GND                 | 0x40                  |
+| INA228            | AUDIO             | A1=GND, A0=VCC                 | 0x41                  |
+| EEPROM 24AA025E48 | Memoria           | A2=GND, A1=GND, A0=GND         | 0x50                  |
+| TLV320AIC3104     | Audio Codec       | ADDR = GND                     | 0x18                  |
+| SC16IS740         | RX                | A1=GND, A0=GND                 | 0x48                  |
+| SC16IS740         | TX                | A1=GND, A0=VCC                 | 0x49                  |
+| BQ27441           | Fuel Gauge        | Indirizzo fisso                | 0x55                  |