schema completato
This commit is contained in:
@@ -37,13 +37,14 @@ The Audio Processor is responsible for:
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- audio clock generation
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- synchronization of external audio peripherals
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The Audio Processor is considered the audio domain master.
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The Audio Processor is the sole timing and routing master of the Audio Domain.
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The System Controller participates in the Audio Domain as a digital audio source. It does not act as the audio timing master or routing controller. Its role inside the audio domain is equivalent to other digital audio sources.
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The System Controller has a dual role:
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- audio source inside the Audio Domain
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system supervisor inside the Control Domain
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- system supervisor inside the Control Domain
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It operates as system supervisor and is responsible for:
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@@ -23,7 +23,7 @@ audio transport interface.
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## Decision
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The SPI architecture is divided into independent functional domains.
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The SPI architecture is divided into independent control domains.
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The System Controller operates as the master of the system control SPI bus.
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@@ -88,8 +88,7 @@ commands exchanged on the external SPI control interface.
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Internal RAM
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The System Controller controls the initialization process but does not directly access
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the internal operational memory of the Radio Receiver.
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The System Controller supervises the Radio Receiver initialization process. Internal firmware loading remains under the responsibility of the Radio Receiver boot architecture.
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## Consequences
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@@ -41,13 +41,15 @@ External audio devices operate as I2S slaves whenever supported.
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## Audio Input Allocation
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| Audio Processor Port | Device | Function |
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|| Audio Processor Input | Device | Function |
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|---|---|---|
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| SDATA_IN0 | System Controller | Network audio stream |
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| SDATA_IN1 | Radio Receiver | Radio audio |
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| SDATA_IN2 | DECODEC | Optical digital input |
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| SDATA_IN3 | Bluetooth RX | Wireless audio input |
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| SPDIFIN | Optical Interface | Optical digital audio input |
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| SDATA_IN2 | Bluetooth RX | Wireless audio input |
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The ADAU1467 internal audio routing matrix allows any digital audio input
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to be routed to the DSP core, ASRCs, serial outputs or SPDIF output.
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System Controller --------
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Radio Receiver ---------
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@@ -57,11 +59,13 @@ BT RX ---------/
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## Audio Output Allocation
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| Audio Processor Port | Device | Function |
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## Audio Output Allocation
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| Audio Processor Output | Device | Function |
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|---|---|---|
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| SDATA_OUT0 | CODEC/DAC | Analog audio output |
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| SDATA_OUT1 | Bluetooth TX | Wireless audio output |
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| SDATA_OUT2 | ENCODEC | Optical digital output |
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| SPDIFOUT | Optical Interface | Optical digital audio output |
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| SDATA_OUT3 | Reserved | Future expansion |
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Audio Processor
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@@ -1,7 +1,7 @@
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# ADR-004 – Power Domain Architecture
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- **Status:** Accepted
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- **Date:** YYYY-MM-DD
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- **Date:** 2026-08-02
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# Context
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@@ -0,0 +1,506 @@
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# HubAudio PCB Floor Plan
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- Status: Draft
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- Date: 2026-08-01
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- Document Type: Hardware Architecture
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# 1. Overview
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This document defines the preliminary PCB floor plan for the HubAudio
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single-board audio platform.
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The PCB integrates:
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- System Controller
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- Audio Processor
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- Radio Receiver
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- Wireless Audio Interfaces
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- Digital Audio Interfaces
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- Power Management
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- Battery Operation Support
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The floor plan follows the fundamental HubAudio architecture:
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ESP32-S3 manages the Control Domain.
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ADAU1467 manages the Audio Domain.
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The Clock Distribution Layer provides synchronization
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for digital audio peripherals.
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The PCB layout must preserve separation between:
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- Control Domain
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- Audio Domain
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- Clock Domain
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- Power Domain
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The objective is to create a compact portable audio platform while
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maintaining:
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- audio signal integrity
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- clock stability
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- RF performance
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- power efficiency
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- battery operation capability
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---
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# 2. PCB Constraints
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## 2.1 Target Dimensions
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The HubAudio board is designed as a compact single-board platform.
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Preferred PCB size:
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Layer 1
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Component placement
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Critical digital signals
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Audio routing
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Layer 2
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Continuous GND plane
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Layer 3
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Power distribution
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Layer 4
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Control signals
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Low speed routing
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Auxiliary signals
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A 6-layer PCB remains an optional evolution only if required after
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routing verification.
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The transition to 6 layers must be justified by:
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- routing density
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- clock integrity
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- RF isolation requirements
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- power distribution constraints
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The initial architecture target remains:
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4 Layer PCB
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---
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# 4. Functional PCB Zones
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The PCB is divided into five functional areas.
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## 4.1 Control Zone
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Contains:
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- ESP32-S3
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- USB interface
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- programming interface
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- user interface connections
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Responsibilities:
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- network connectivity
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- streaming control
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- configuration management
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- firmware updates
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Placement requirements:
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- close to PCB edge
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- antenna clearance
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- separated from switching regulators
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---
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## 4.2 Audio Processing Zone
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Contains:
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- ADAU1467
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- Audio EEPROM
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- Clock circuitry
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- Audio domain support components
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The ADAU1467 is the physical center of the Audio Domain.
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Responsibilities:
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- DSP processing
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- routing
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- mixing
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- synchronization
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Critical signals:
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- MCLK
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- BCLK
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- LRCLK
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- I2S DATA
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must remain short.
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---
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## 4.3 Radio Zone
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Contains:
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- Si4684
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- RF interface
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- antenna related components
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Placement requirements:
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- close to RF input
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- separated from switching noise
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- local power filtering
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The Si4684 operates as a digital audio peripheral
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inside the Audio Domain.
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---
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## 4.4 Audio Interface Zone
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Contains:
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- Bluetooth interfaces
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- Optical interfaces
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- CODEC/DAC stages
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Interfaces:
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I2S
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ADAU1467
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Placement requirements:
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- close to PCB edge
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- short I2S paths
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- controlled supply filtering
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---
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## 4.5 Power Zone
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Contains:
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- Battery input
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- USB power input
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- Charger
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- PMIC
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- Regulators
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- Filtering components
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Placement:
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PCB edge area
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Power path:
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Battery / USB
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Protection
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Charger
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PMIC
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Regulators
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Digital / Analog domains
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The Power Zone must remain physically separated from:
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- clock circuitry
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- RF section
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- sensitive audio signals
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---
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# 5. Preliminary Floor Plan
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Conceptual arrangement:
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+--------------------------------+
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| |
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| ESP32-S3 Si4684 |
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| CONTROL RADIO |
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| |
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| |
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| CLOCK |
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| BUFFER |
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| | |
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| ADAU1467 |
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| AUDIO PROCESSOR |
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| |
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| BT RX SPDIF CODEC BT TX |
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| AUDIO INTERFACE |
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BATTERY / PMIC / CHARGER
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POWER DOMAIN
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+--------------------------------+
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PCB TARGET:
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90 mm x 70 mm
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This arrangement keeps the ADAU1467 physically central.
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The placement minimizes:
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- I2S length
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- clock distribution length
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- audio routing complexity
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---
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# 6. ADAU1467 Placement
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The ADAU1467 is the physical center of the digital audio subsystem.
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This follows the architecture decision:
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ADAU1467 = Audio Domain Master
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Placement rules:
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- central PCB position
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- shortest clock paths
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- shortest I2S paths
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- local decoupling network
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- separated from switching regulators
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The ADAU1467 area includes:
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- DSP processor
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- clock interface
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- SPI configuration interface
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- audio EEPROM
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Critical signals:
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MCLK
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BCLK
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LRCLK
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I2S DATA
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must be routed with priority.
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---
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# 7. ESP32-S3 Placement
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The ESP32-S3 belongs to the Control Domain.
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Placement rules:
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- PCB edge placement
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- antenna keep-out area
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- USB accessibility
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- separation from analog audio
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The ESP32-S3 interfaces:
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Control:
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SPI
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Audio:
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I2S Source
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The ESP32-S3 is not the audio clock master.
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---
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# 8. Clock Distribution Placement
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The Clock Distribution Layer provides:
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- MCLK
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- BCLK
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- LRCLK
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Architecture:
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ADAU1467
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Audio Clock Master
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Clock Buffer
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+-----------+-----------+
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CODEC Si4684 BT
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Clock traces must have priority routing.
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---
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# 9. Routing Priorities
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Routing priority:
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1. Clock signals
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MCLK
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BCLK
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LRCLK
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2. I2S audio buses
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3. SPI control
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4. Power distribution
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5. Low-speed signals
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Clock and audio signals must avoid:
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- switching regulator nodes
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- RF traces
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- high current battery paths
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---
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# 10. Summary
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The HubAudio PCB follows the architectural separation:
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CONTROL DOMAIN
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ESP32-S3
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SPI
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AUDIO DOMAIN
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ADAU1467
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I2S
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CLOCK DOMAIN
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Clock Distribution
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POWER DOMAIN
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Battery / PMIC / Regulators
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The floor plan defines a compact single-board implementation
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||||
optimized for:
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||||
|
||||
- portability
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||||
- battery operation
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- audio integrity
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- future expansion
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||||
@@ -0,0 +1,13 @@
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# Tabella Indirizzi I2C
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| Dispositivo | Funzione / Nome | Configurazione Pin Indirizzo | Indirizzo I2C (Hex) |
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|:------------------|:------------------|:-------------------------------|:----------------------|
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| TCA9555 #1 | POWER_CONTROLLER | A2=GND, A1=GND, A0=GND | 0x20 |
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| TCA9555 #2 | AUDIO_CONTROL | A2=GND, A1=GND, A0=VCC | 0x21 |
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| INA228 | DIGITAL | A1=GND, A0=GND | 0x40 |
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| INA228 | AUDIO | A1=GND, A0=VCC | 0x41 |
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| EEPROM 24AA025E48 | Memoria | A2=GND, A1=GND, A0=GND | 0x50 |
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| TLV320AIC3104 | Audio Codec | ADDR = GND | 0x18 |
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| SC16IS740 | RX | A1=GND, A0=GND | 0x48 |
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| SC16IS740 | TX | A1=GND, A0=VCC | 0x49 |
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| BQ27441 | Fuel Gauge | Indirizzo fisso | 0x55 |
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