micheleandClaude Sonnet 5
8b8ca239ca
The repository had accumulated multiple, contradictory "current state" documents for V2 hardware: an old V1 IT/EN datasheet copy nested inside hardware/v2/docs/datasheet/, a stray untracked duplicate at repo root (docs/DatasheetLatex/), and a second, much older documentation track (hardware/v2/docs/*.md: PRE_PCB_VERIFICATION.md, PRE_PCB_CLOSURE_4POINT.md, MEMORY_UPGRADE_64MB_N8.md, and 10 more) describing an earlier PSRAM/ N_SLOTS<=2 milestone alongside the real, current SDRAM/N_SLOTS=4 board. The LaTeX datasheet's own front matter (features/pinout cover pages) and chapter 9 (benchmarks) were themselves still describing that obsolete architecture, contradicting the real, current chapters 5/7/10 elsewhere in the same document. This commit: - Flattens hardware/v2/docs/datasheet/files/docs/datasheet/v2-en/* up to hardware/v2/docs/datasheet/ (was 4 levels of redundant nesting). - Removes the old V1 IT/EN LaTeX copies and the stray root-level duplicate entirely (recoverable from git history, not from disk). - Preserves the real component reference PDFs (ECP5 eval board, ISSI PSRAM, programming cables) under datasheet/references/. - Removes 13 superseded hardware/v2/docs/*.md status documents after folding every real, unique fact they contained into the datasheet: SPI max verified clock (12MHz, exact 12.8MHz CDC edge), SDRAM directed boundary test (21/21 PASS), 16MHz oscillator MPN (ECS-3225MV-160-BN-TR), and the real FPGA<->SDRAM ball mapping cross-check. - Rewrites the datasheet's own front matter, ch.4 (parameters), ch.8 (top-level module -- was documenting the wrong, non-physical top entirely), and ch.9 (benchmarks) to describe the current, real SDRAM/ N_SLOTS=4 production board, while keeping the real PSRAM-era chapters as clearly-labeled history rather than deleting correctly-measured work. - Fixes a title-page tikzpicture that was clipped off the page edge (pre-existing, unrelated to this change) by scaling it to fit. Net: 85 files changed, -8814/+498 lines. hardware/v2/docs/ now contains exactly one current datasheet plus FIRST_POWER_ON.md (a bring-up runbook, not a duplicate spec). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
68 lines
2.9 KiB
TeX
68 lines
2.9 KiB
TeX
\thispagestyle{plain}
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\noindent
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\begin{tikzpicture}
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\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt,
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minimum width=\textwidth,anchor=west]
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{\large\bfseries Pinout summary --- real, board-verified};
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\end{tikzpicture}
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\vspace{6pt}
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\noindent
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{\footnotesize
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V2's top-level module, \code{fpga\_neural\_v2\_top.v}, has a complete,
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real ball assignment: every signal --- SDRAM bus, SPI host transport,
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clock/reset, \code{FPGA\_DATA\_READY}, JTAG, configuration mode straps,
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and the boot flash's dedicated MSPI pins --- carries a real CABGA381 ball
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site, sourced from the official Lattice pinout CSV (rev 3.0) and
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cross-checked against Project Trellis's own \code{iodb.json}. This
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supersedes an earlier V2 milestone in which the board-level top had been
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placed only \textbf{unconstrained}; a full, constrained \code{.lpf} now
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exists (\code{hardware/v2/constraints/v2\_board\_top.lpf}) and every
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Fmax number in this datasheet (\S\ref{sec:clock-closure-current}) is
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measured against it.
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}
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\vspace{6pt}
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\begin{fnnote}[What is real]
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Every ball in the summary table below is placed, P\&R-confirmed, and
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cross-checked against a real, exported KiCad schematic and BOM
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(\S\ref{sec:schematic-capture}--\ref{sec:bom}) --- not a simulation-only
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placeholder. No PSRAM signals exist anywhere in this revision: the
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single external memory is SDR SDRAM (\S\ref{sec:sdram-mem-addendum}).
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\end{fnnote}
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\begin{fnwarn}[What remains open]
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FPGA dynamic power/current draw has not been measured post-implementation
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(no ECP5 power estimator is available in this toolchain), so exact
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decoupling/regulator sizing uses datasheet-based engineering margin, not
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a computed budget. Hold-time closure is a genuine tool-chain limitation
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(no min-delay analysis path available) --- setup timing is fully
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verified. See ch.~\ref{ch:hw} for the complete, disclosed list.
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\end{fnwarn}
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\vspace{6pt}
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\noindent
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{\small\color{fnDark}\bfseries Ball summary (see ch.~\ref{ch:hw} for the
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complete, per-signal table)}
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\vspace{2pt}
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\noindent
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\begin{tabularx}{\textwidth}{L{3.4cm}L{2.4cm}Y}
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\toprule
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\rowh \thd{Interface} & \thd{Ball count} & \thd{Notes} \\
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\midrule
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SDRAM bus (A[0:12], BA[0:1], DQ[0:15], DQM[0:1], CKE/CS\#/RAS\#/CAS\#/WE\#) & 35 & Bank 6/7, real, P\&R-confirmed \\
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\rowa SPI host transport (\code{sclk}/\code{mosi}/\code{miso}/\code{cs\_n}) & 4 & Bank 6/7, plain GPIO \\
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\code{FPGA\_DATA\_READY}, \code{osc\_clk}, \code{ext\_rst\_n}, \code{sdram\_clk}, \code{pll\_locked} & 5 & Bank 6/7 \\
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\rowa JTAG (TCK/TMS/TDI/TDO) & 4 & Bank 40, to ESP32 \\
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Config control (PROGRAMN/INITN/DONE) + CFG[2:0] straps & 6 & Bank 8 \\
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\rowa Boot-flash dedicated MSPI (CSSPIN/MCLK/D0/D1) & 4 & Bank 8, dual-function \\
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\bottomrule
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\end{tabularx}
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\vspace{4pt}
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\noindent
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{\footnotesize\color{fnGrey}
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Complete per-signal ball tables and the real KiCad schematic/BOM: ch.~\ref{ch:hw}.
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Logical (not physical) register-level port list: ch.~\ref{ch:regs}.\par}
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