micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
200 lines
10 KiB
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200 lines
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 281/43848 0%
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Info: logic LUTs: 77/43848 0%
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Info: carry LUTs: 204/43848 0%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 561/43848 1%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 212 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0xe4bf0be0
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Info: Device utilisation:
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Info: TRELLIS_IO: 192/ 245 78%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 8/ 72 11%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 561/ 43848 1%
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Info: TRELLIS_COMB: 319/ 43848 0%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 424 cells, random placement wirelen = 50455.
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Info: at initial placer iter 0, wirelen = 12005
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Info: at initial placer iter 1, wirelen = 11180
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Info: at initial placer iter 2, wirelen = 11007
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Info: at initial placer iter 3, wirelen = 11030
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Info: Running main analytical placer, max placement attempts per cell = 146070.
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Info: at iteration #1, type ALL: wirelen solved = 11022, spread = 14876, legal = 16032; time = 0.01s
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Info: at iteration #2, type ALL: wirelen solved = 11185, spread = 13525, legal = 14773; time = 0.01s
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Info: at iteration #3, type ALL: wirelen solved = 11171, spread = 14157, legal = 15687; time = 0.01s
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Info: at iteration #4, type ALL: wirelen solved = 11247, spread = 13660, legal = 15080; time = 0.01s
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Info: at iteration #5, type ALL: wirelen solved = 11256, spread = 14501, legal = 16195; time = 0.01s
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Info: at iteration #6, type ALL: wirelen solved = 11281, spread = 14413, legal = 15627; time = 0.01s
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Info: at iteration #7, type ALL: wirelen solved = 11322, spread = 14088, legal = 15088; time = 0.01s
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Info: HeAP Placer Time: 0.07s
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Info: of which solving equations: 0.04s
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Info: of which spreading cells: 0.01s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 131, wirelen = 14773
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Info: at iteration #5: temp = 0.000000, timing cost = 106, wirelen = 11964
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Info: at iteration #9: temp = 0.000000, timing cost = 77, wirelen = 12024
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Info: SA placement time 0.09s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 158.73 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.92 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.14 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 6200, 6477) |*+
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Info: [ 6477, 6754) |***+
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Info: [ 6754, 7031) |********+
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Info: [ 7031, 7308) |*******************************************+
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Info: [ 7308, 7585) |******************************************+
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Info: [ 7585, 7862) |************************************************************
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Info: [ 7862, 8139) |*************************+
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Info: [ 8139, 8416) |*******+
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Info: [ 8416, 8693) |******+
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Info: [ 8693, 8970) |**************+
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Info: [ 8970, 9247) |*******************+
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Info: [ 9247, 9524) |******************+
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Info: [ 9524, 9801) |**********************+
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Info: [ 9801, 10078) |**************************************+
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Info: [ 10078, 10355) |***************************************************+
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Info: [ 10355, 10632) |**********************+
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Info: [ 10632, 10909) |********+
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Info: [ 10909, 11186) |*****+
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Info: [ 11186, 11463) |***+
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Info: [ 11463, 11740) |************+
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Info: Checksum: 0x34ea3833
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 2137 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 108 891 | 108 891 | 1309| 0.20 0.20|
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Info: 2000 | 230 1654 | 122 763 | 437| 0.15 0.35|
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Info: 2450 | 244 2069 | 14 415 | 0| 0.12 0.47|
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Info: Routing complete.
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Info: Router1 time 0.47s
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Info: Checksum: 0xf8fda93b
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source GEN_NP[0].u_np.w0[4]_TRELLIS_FF_Q_3.Q
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Info: routing 1.15 1.55 Net GEN_NP[0].u_np.w0[4][3] (25,20) -> (27,22)
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Info: Sink GEN_NP[0].u_np.product_comb[4]_MULT18X18D_P9.B3
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Info: Defined in:
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Info: hardware/v2/rtl/neural_processor.v:100.44-100.46
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Info: logic 3.07 4.62 Source GEN_NP[0].u_np.product_comb[4]_MULT18X18D_P9.P9
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Info: routing 0.97 5.58 Net GEN_NP[0].u_np.product_comb[4][9] (27,22) -> (27,27)
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Info: Sink GEN_NP[0].u_np.prod1[4]_TRELLIS_FF_Q_9.M
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Info: Defined in:
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Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
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Info: setup 0.00 5.58 Source GEN_NP[0].u_np.prod1[4]_TRELLIS_FF_Q_9.M
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Info: 3.46 ns logic, 2.12 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source tile_last$tr_io.O
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Info: routing 4.08 4.08 Net tile_last$TRELLIS_IO_IN (90,50) -> (19,31)
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Info: Sink job_valid_LUT4_C_Z_LUT4_Z.C
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Info: Defined in:
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Info: hardware/v2/rtl/neural_processor_array.v:43.57-43.66
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Info: logic 0.18 4.26 Source job_valid_LUT4_C_Z_LUT4_Z.F
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Info: routing 0.64 4.90 Net job_valid_LUT4_C_Z[2] (19,31) -> (18,31)
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Info: Sink result_ready_LUT4_A_Z_LUT4_B.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.08 Source result_ready_LUT4_A_Z_LUT4_B.F
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Info: routing 0.49 5.57 Net result_ready_LUT4_A_Z_LUT4_B_Z (18,31) -> (18,32)
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Info: Sink GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_2.CE
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Info: setup 0.00 5.57 Source GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_2.CE
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Info: 0.36 ns logic, 5.21 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_1.Q
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Info: routing 0.64 1.03 Net np_state[2]$TRELLIS_IO_OUT (18,32) -> (18,32)
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Info: Sink operand_ready_LUT4_Z.B
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 1.21 Source operand_ready_LUT4_Z.F
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Info: routing 4.40 5.61 Net operand_ready$TRELLIS_IO_OUT (18,32) -> (90,56)
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Info: Sink operand_ready$tr_io.I
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Info: Defined in:
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Info: hardware/v2/rtl/neural_processor_array.v:40.58-40.71
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Info: 0.57 ns logic, 5.03 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 179.08 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.57 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.61 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 6916, 7160) |**********************+
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Info: [ 7160, 7404) |************************************************************
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Info: [ 7404, 7648) |********+
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Info: [ 7648, 7892) |********+
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Info: [ 7892, 8136) |***+
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Info: [ 8136, 8380) |******+
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Info: [ 8380, 8624) |*********************+
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Info: [ 8624, 8868) |**************************************+
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Info: [ 8868, 9112) |***************************************+
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Info: [ 9112, 9356) |**********+
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Info: [ 9356, 9600) |*****************************************+
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Info: [ 9600, 9844) |*************************************+
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Info: [ 9844, 10088) |****************************************************+
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Info: [ 10088, 10332) |******************************+
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Info: [ 10332, 10576) |********+
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Info: [ 10576, 10820) |***************+
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Info: [ 10820, 11064) |***************+
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Info: [ 11064, 11308) |******+
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Info: [ 11308, 11552) |*****+
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Info: [ 11552, 11796) |**********+
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Info: Program finished normally.
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