micheleandClaude Sonnet 5
68f3c5e403
Root-causes and fixes the real, disclosed defect left open at the end of the previous STEP20 commit: the board-level SPI host interface produced wrong compute results when jobs were dispatched with realistic (widely time-separated) pacing, even though job registration itself was already confirmed correct at the dependency_manager handshake. Root cause: nms_weight_packed.v and nms_activation_replicated.v both used a REGISTERED SRAM read (rd_data_reg <= mem[addr], one full clock of latency), but nms_memory_manager_stream_wide.v's own read-ahead pipeline (its `rd_pending` bit) is designed around a COMBINATIONAL read -- a request issued this cycle produces data already valid to capture the very next cycle. A busy, multi-tile job (e.g. the STEP19 D-Stress regression, 16 tiles/neuron) never exposes the mismatch, since its own weight/activation prefetch always runs far enough ahead that any given tile has been sitting stable in the SRAM for many cycles by the time it's actually consumed. An uncontested single-tile job has zero such margin: its one tile's read fires on the exact edge the data nominally becomes ready, landing squarely on the missing cycle and permanently latching stale/zero data. Fixed by making both SRAMs' reads combinational, with an explicit same-cycle fill/read address-match bypass for the one hazard a plain combinational read alone would still miss. No FSM, arbiter, or SDRAM controller logic was touched. Verified (Verilator, per this project's own standing DEC-0004 protocol): - tb_fpga_neural_v2_top_smoke.v: 11/11 PASS -- single job, back-to-back jobs, a realistic ~85us-gap job pair, and a parametric sweep of inter-job gaps (100ns/5000ns/50000ns). - STEP19 D-Stress N=2: 49788 cycles, 256/256 bit-exact -- identical cycle count to before this fix (zero regression). - STEP19 D-Stress N=4: 49771 cycles, 256/256 bit-exact -- identical cycle count to before this fix (zero regression). - tb_sdram_unified_backend.v (40/40) and tb_spi_host_bridge.v (18/18) reconfirmed unaffected. The physical SPI host interface is now verified correct end-to-end. Real synthesis/P&R of the board-level top (fpga_neural_v2_top.v) is the deliberate next step, not yet performed this round. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
82 lines
4.0 KiB
Verilog
82 lines
4.0 KiB
Verilog
// ============================================================
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// Neural Memory System (NMS) -- STEP4/5 candidate A: REPLICATED
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// activation memory.
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//
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// One full copy of the shared activation vector's tile storage per
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// slot (N_SLOTS independent single-write/single-read BRAMs). A shared
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// fill engine broadcasts each filled tile to EVERY copy on the same
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// cycle (one PSRAM-side write, N_SLOTS on-chip writes) -- after fill,
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// every slot's own read port is completely private: zero contention,
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// ever, by construction (no arbitration logic at all on the read
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// side). Real cost is N_SLOTS x the single-copy storage; this file
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// exists to MEASURE that real DP16KD/LUT/Fmax cost against Candidate
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// B (nms_activation_banked.v) rather than assume replication is too
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// expensive a priori (EXP-0019/DEC-0019).
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// ============================================================
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module nms_activation_replicated #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter N_SLOTS = 4,
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parameter MAX_TILES = 16,
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parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES)
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)(
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input clk,
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input rst,
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// ---- fill port: one write, broadcast to every copy ----
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input fill_we,
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input [TIW-1:0] fill_addr,
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input [DATA_WIDTH*P_IN-1:0] fill_data,
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// ---- per-slot private read port ----
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input [N_SLOTS-1:0] rd_en,
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input [N_SLOTS*TIW-1:0] rd_addr_flat,
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output [N_SLOTS*DATA_WIDTH*P_IN-1:0] rd_data_flat
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);
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genvar g;
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generate
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for (g = 0; g < N_SLOTS; g = g + 1) begin : GEN_COPY
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reg [DATA_WIDTH*P_IN-1:0] mem [0:MAX_TILES-1];
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always @(posedge clk) begin
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if (fill_we)
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mem[fill_addr] <= fill_data;
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end
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// ROOT CAUSE (found via STEP20's own board-level SPI
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// integration smoke test, ERR-0025 Part B): this read used
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// to be REGISTERED (rd_data_reg <= mem[addr], gated by
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// rd_en[g]) -- a full extra clock cycle of latency beyond
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// what nms_memory_manager_stream_wide.v's own read-ahead
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// pipeline (its `rd_pending` bit) actually assumes. That
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// pipeline issues a read one cycle and captures the result
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// the VERY NEXT cycle -- correct only if this memory's own
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// read is COMBINATIONAL (address in this cycle, data
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// already valid this same cycle), not registered (address
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// in this cycle, data valid only the cycle after). A busy,
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// multi-tile job never exposes the extra cycle because its
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// own weight/activation prefetch always runs far enough
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// ahead that, by the time a given tile is actually
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// consumed, that data has been sitting stable for many
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// cycles already. An uncontested single-tile job has zero
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// such margin: its first (only) tile's read fires on the
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// exact edge the data becomes nominally "ready", and the
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// consumer captured one real cycle before the registered
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// output ever updated -- permanently latching stale
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// (all-zero, reset-value) data. Fixed by making the read
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// itself combinational, matching the consumer's actual
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// latency assumption, with NO change to any FSM timing.
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// The same-cycle fill/read-to-the-same-address case (fill_we
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// and this slot's own read targeting the identical tile on
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// the identical edge) is bypassed explicitly, since mem[]
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// itself will not show a same-edge write until the NEXT
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// cycle even with a combinational read.
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wire rd_bypass = fill_we && (fill_addr == rd_addr_flat[g*TIW +: TIW]);
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assign rd_data_flat[g*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN] =
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rd_bypass ? fill_data : mem[rd_addr_flat[g*TIW +: TIW]];
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end
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endgenerate
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endmodule
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