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FPGA-Neural/hardware/v2/nms/synthesis/act_rep_n8/nextpnr.log
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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

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Info: Logic utilisation before packing:
Info: Total LUT4s: 136/43848 0%
Info: logic LUTs: 40/43848 0%
Info: carry LUTs: 0/43848 0%
Info: RAM LUTs: 64/ 5481 1%
Info: RAMW LUTs: 32/10962 0%
Info: Total DFFs: 104/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 72 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x46141fa9
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 104/ 43848 0%
Info: TRELLIS_COMB: 138/ 43848 0%
Info: TRELLIS_RAMW: 16/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 81 cells, random placement wirelen = 9806.
Info: at initial placer iter 0, wirelen = 1338
Info: at initial placer iter 1, wirelen = 1038
Info: at initial placer iter 2, wirelen = 1036
Info: at initial placer iter 3, wirelen = 983
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info: at iteration #1, type ALL: wirelen solved = 979, spread = 1364, legal = 1395; time = 0.00s
Info: at iteration #2, type ALL: wirelen solved = 1007, spread = 1255, legal = 1274; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 971, spread = 1233, legal = 1249; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 969, spread = 1216, legal = 1250; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 1003, spread = 1255, legal = 1272; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 992, spread = 1194, legal = 1240; time = 0.00s
Info: at iteration #7, type ALL: wirelen solved = 997, spread = 1203, legal = 1245; time = 0.00s
Info: HeAP Placer Time: 0.04s
Info: of which solving equations: 0.01s
Info: of which spreading cells: 0.00s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 13, wirelen = 1240
Info: at iteration #5: temp = 0.000000, timing cost = 17, wirelen = 878
Info: at iteration #10: temp = 0.000000, timing cost = 16, wirelen = 875
Info: at iteration #13: temp = 0.000000, timing cost = 18, wirelen = 863
Info: SA placement time 0.03s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 334.56 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.27 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.16 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9511, 9623) |+
Info: [ 9623, 9735) |
Info: [ 9735, 9847) |+
Info: [ 9847, 9959) |
Info: [ 9959, 10071) |**+
Info: [ 10071, 10183) |*+
Info: [ 10183, 10295) |+
Info: [ 10295, 10407) |*******+
Info: [ 10407, 10519) |**********+
Info: [ 10519, 10631) |*************************+
Info: [ 10631, 10743) |****************************************+
Info: [ 10743, 10855) |****************+
Info: [ 10855, 10967) |*************************************+
Info: [ 10967, 11079) |************************************************************
Info: [ 11079, 11191) |*************************************************+
Info: [ 11191, 11303) |************************+
Info: [ 11303, 11415) |***************************+
Info: [ 11415, 11527) |**********+
Info: [ 11527, 11639) |******+
Info: [ 11639, 11751) |*****+
Info: Checksum: 0xe86f58c8
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 932 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 84 907 | 84 907 | 45| 0.05 0.05|
Info: 1044 | 84 952 | 0 45 | 0| 0.01 0.07|
Info: Routing complete.
Info: Router1 time 0.07s
Info: Checksum: 0x41fe45e9
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source dut.GEN_COPY[4].rd_data_reg_TRELLIS_FF_Q.Q
Info: routing 0.49 0.88 Net rd_data_flat[257] (12,24) -> (12,24)
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0_LUT4_Z_1.D
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_activation_replicated.v:34.50-34.62
Info: logic 0.18 1.06 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0_LUT4_Z_1.F
Info: routing 0.74 1.80 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_C0[3] (12,24) -> (12,27)
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_ALUT_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.98 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_ALUT_LUT4_Z.F
Info: routing 0.00 1.98 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_ALUT (12,27) -> (12,27)
Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
Info: logic 0.13 2.10 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_3_BLUT_LUT4_Z.OFX
Info: routing 0.51 2.61 Net chk_TRELLIS_FF_Q_DI[1] (12,27) -> (12,26)
Info: Sink chk_TRELLIS_FF_Q.M
Info: setup 0.00 2.61 Source chk_TRELLIS_FF_Q.M
Info: 0.88 ns logic, 1.73 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source seed[7]$tr_io.O
Info: routing 2.85 2.85 Net seed[7]$TRELLIS_IO_IN (42,0) -> (16,24)
Info: Sink seed_LUT4_B_Z_LUT4_Z_5.B
Info: Defined in:
Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:23.23-23.27
Info: logic 0.18 3.03 Source seed_LUT4_B_Z_LUT4_Z_5.F
Info: routing 0.12 3.15 Net seed_LUT4_B_Z[7] (16,24) -> (16,24)
Info: Sink lfsr_TRELLIS_FF_Q_6.DI
Info: setup 0.00 3.15 Source lfsr_TRELLIS_FF_Q_6.DI
Info: 0.18 ns logic, 2.97 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_6.Q
Info: routing 3.56 3.95 Net checksum[0]$TRELLIS_IO_OUT (10,25) -> (90,26)
Info: Sink checksum[0]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 3.56 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 382.56 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.15 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.95 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 9886, 9982) |+
Info: [ 9982, 10078) |**+
Info: [ 10078, 10174) |+
Info: [ 10174, 10270) |*+
Info: [ 10270, 10366) |
Info: [ 10366, 10462) |
Info: [ 10462, 10558) |**+
Info: [ 10558, 10654) |*****+
Info: [ 10654, 10750) |********+
Info: [ 10750, 10846) |*************+
Info: [ 10846, 10942) |*************************************************+
Info: [ 10942, 11038) |*********************************************+
Info: [ 11038, 11134) |***********************************************+
Info: [ 11134, 11230) |************************************************************
Info: [ 11230, 11326) |******************************+
Info: [ 11326, 11422) |********************************+
Info: [ 11422, 11518) |************+
Info: [ 11518, 11614) |******+
Info: [ 11614, 11710) |***+
Info: [ 11710, 11806) |****+
Info: Program finished normally.
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