FPGA-Neural

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micheleandClaude Sonnet 5 fc0130e2e2 docs: LaTeX chapters for hardware, chip architecture, and tests/timing

Three chapters (docs/latex/), sourced from the real project docs
(BOM.md, PHYSICAL_REALIZATION.md, ARCHITECTURE_ANALYSIS.md,
experiments.log) -- no invented numbers:

- hardware.tex: board components, DDR3/FPGA/flash/ESP32, real pinout,
  SPI protocol, boot procedure.
- architecture.tex: packed INT8 MAC core, N=8 hybrid systolic
  architecture (shared-weight broadcast), hierarchical arbiter,
  result writeback, why N=8 is the DDR3-bandwidth-bound sweet spot.
- tests_timing.tex: verification methodology, real functional test
  results table, full real P&R signoff history (N=2 through N=16),
  the definitive N=8 signoff (WNS=0.000ns), and an honestly-caveated
  ESP32-S3 comparison (real historical ECP5 measurement vs. the
  superseded, never-verified Artix-7 projection).

main.tex ties the three together as report chapters.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-21 08:54:25 +02:00

latex

docs: LaTeX chapters for hardware, chip architecture, and tests/timing

2026-09-21 08:54:25 +02:00

ARCHITECTURE_ANALYSIS.md

feat: N=8 hybrid systolic promoted to the real, definitive deployment target (EXP-0096)

2026-09-21 08:29:04 +02:00

BOM.md

feat: real DDRManager re-measurement at 32-bit channel + BOM/pinout docs (EXP-0087)

2026-09-20 18:37:41 +02:00

FPGA-Neural-Flash-Subsystem-Verification.md

fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7)