micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
84710 lines
1.9 MiB
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84710 lines
1.9 MiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C10:CIB_EBR
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arc: N1_V02N0201 H02W0201
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arc: N1_V02N0601 H02E0601
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.tile CIB_R10C11:CIB_EBR
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arc: W1_H02W0201 S1_V02N0201
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.tile CIB_R10C12:CIB_EBR
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arc: N1_V02N0201 S1_V02N0701
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arc: N1_V02N0401 H02W0401
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.tile CIB_R10C13:CIB_EBR
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arc: W1_H02W0401 V06N0203
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.tile CIB_R10C14:CIB_EBR
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arc: S1_V02S0601 N1_V02S0601
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arc: S1_V02S0701 V01N0101
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.tile CIB_R10C23:CIB_EBR
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arc: V01S0100 S3_V06N0303
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.tile CIB_R10C24:CIB_EBR
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arc: E1_H02E0201 S3_V06N0103
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arc: E1_H02E0301 S1_V02N0301
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arc: E1_H02E0601 V06N0303
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arc: N1_V01N0001 S3_V06N0003
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arc: N1_V02N0201 S1_V02N0201
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arc: S1_V02S0301 S3_V06N0003
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arc: S1_V02S0501 N1_V01S0100
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.tile CIB_R10C25:CIB_EBR
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arc: N1_V02N0301 H02W0301
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arc: N1_V02N0601 H02E0601
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arc: S1_V02S0201 H02E0201
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arc: S1_V02S0301 H02W0301
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.tile CIB_R10C26:CIB_EBR
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arc: E1_H02E0301 W1_H02E0301
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arc: N1_V02N0101 S1_V02N0001
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arc: N1_V02N0201 W1_H02E0201
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arc: N1_V02N0601 E1_H02W0601
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arc: S1_V02S0401 E1_H02W0401
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arc: S1_V02S0501 E1_H02W0501
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arc: S1_V02S0601 E1_H02W0601
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arc: W1_H02W0301 V06S0003
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.tile CIB_R10C27:CIB_EBR
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arc: E1_H02E0501 V02S0501
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arc: N1_V02N0201 H06W0103
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arc: N1_V02N0401 S1_V02N0401
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arc: N1_V02N0501 V01N0101
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arc: N1_V02N0601 V01N0001
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arc: N1_V02N0701 V01N0101
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arc: S1_V02S0601 H02W0601
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arc: S1_V02S0701 S3_V06N0203
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arc: V01S0000 S3_V06N0103
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.tile CIB_R10C28:CIB_EBR
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arc: N1_V02N0101 S1_V02N0001
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arc: N1_V02N0301 W1_H02E0301
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arc: N1_V02N0501 S1_V02N0501
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arc: N1_V02N0601 S1_V02N0301
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arc: N1_V02N0701 S3_V06N0203
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arc: S1_V02S0501 H02E0501
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arc: S1_V02S0601 N1_V01S0000
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arc: W1_H02W0401 S3_V06N0203
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arc: W1_H02W0501 V06S0303
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arc: W1_H02W0601 V06S0303
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.tile CIB_R10C29:CIB_EBR
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arc: E1_H02E0201 S3_V06N0103
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arc: N1_V02N0101 S3_V06N0103
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arc: N1_V02N0201 S3_V06N0103
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arc: N1_V02N0401 S1_V02N0401
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arc: S1_V02S0201 S3_V06N0103
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arc: S1_V02S0601 N1_V01S0000
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arc: S1_V02S0701 N1_V01S0100
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arc: V01S0100 S3_V06N0303
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.tile CIB_R10C2:CIB_EBR
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arc: S1_V02S0701 S3_V06N0203
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.tile CIB_R10C30:CIB_EBR
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arc: E1_H02E0001 N1_V01S0000
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arc: E1_H02E0401 S1_V02N0401
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arc: N1_V01N0001 S3_V06N0003
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arc: N1_V02N0201 S3_V06N0103
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arc: N1_V02N0301 V01N0101
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arc: N1_V02N0401 S1_V02N0401
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arc: N1_V02N0501 S1_V02N0401
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arc: S1_V02S0001 V01N0001
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arc: V01S0000 S3_V06N0103
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arc: V01S0100 S3_V06N0303
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arc: W3_H06W0103 S3_V06N0103
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.tile CIB_R10C31:CIB_EBR
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arc: N1_V02N0401 H02E0401
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arc: S1_V02S0001 H02E0001
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arc: S1_V02S0201 W1_H02E0201
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arc: S1_V02S0601 H02W0601
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.tile CIB_R10C32:CIB_EBR
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arc: N1_V02N0101 S1_V02N0101
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arc: N1_V02N0401 S1_V02N0101
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arc: S1_V02S0001 N1_V01S0000
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arc: W1_H02W0601 V02S0601
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.tile CIB_R10C33:CIB_EBR
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arc: N1_V02N0201 E1_H02W0201
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arc: N1_V02N0401 S1_V02N0101
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arc: V01S0100 S3_V06N0303
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.tile CIB_R10C35:CIB_EBR
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arc: N1_V02N0201 N1_V01S0000
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arc: W1_H02W0201 S3_V06N0103
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R10C6:CIB_EBR
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arc: S1_V02S0201 H06W0103
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.tile CIB_R10C7:CIB_EBR
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arc: S1_V02S0201 E1_H02W0201
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.tile CIB_R10C8:CIB_EBR
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arc: S1_V02S0301 H02W0301
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.tile CIB_R10C9:CIB_EBR
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arc: E1_H02E0601 S1_V02N0601
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arc: N1_V02N0201 E1_H02W0201
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arc: N1_V02N0601 S1_V02N0601
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arc: W1_H02W0201 E1_H02W0201
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arc: W1_H02W0301 V06N0003
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arc: W3_H06W0103 E1_H02W0201
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.tile CIB_R11C1:CIB_LR
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arc: JA0 H02W0701
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arc: JB0 E1_H01W0100
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arc: S3_V06S0303 JF5
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.tile CIB_R13C89:CIB_LR
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arc: W3_H06W0303 JQ5
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.tile CIB_R14C1:CIB_LR
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arc: S1_V02S0701 H06W0203
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.tile CIB_R14C89:CIB_LR
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arc: S1_V02S0501 H06E0303
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.tile CIB_R15C1:CIB_LR
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arc: S1_V02S0701 E1_H02W0701
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.tile CIB_R16C1:CIB_LR
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arc: E1_H02E0201 S3_V06N0103
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arc: E1_H02E0601 V02N0601
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arc: JA0 N1_V02S0701
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enum: CIB.JB0MUX 0
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.tile CIB_R16C89:CIB_LR
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arc: JA0 N1_V02S0501
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enum: CIB.JB0MUX 0
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.tile CIB_R17C1:CIB_LR
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arc: E1_H02E0101 S1_V02N0101
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arc: E1_H02E0501 S3_V06N0303
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arc: E1_H02E0601 S3_V06N0303
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arc: E1_H02E0701 S3_V06N0203
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arc: JA3 N1_V02S0701
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arc: N1_V02N0601 N3_V06S0303
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arc: S1_V02S0101 S3_V06N0103
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arc: V01S0000 S3_V06N0103
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enum: CIB.JB3MUX 0
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.tile CIB_R18C1:CIB_LR
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arc: E1_H01E0101 E3_H06W0203
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arc: E1_H02E0101 V02S0101
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arc: E1_H02E0301 S1_V02N0301
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arc: E1_H02E0401 N1_V01S0000
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arc: E1_H02E0501 E3_H06W0303
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arc: E1_H02E0601 S3_V06N0303
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.tile CIB_R19C1:CIB_LR
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arc: E1_H02E0001 V02N0001
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arc: E1_H02E0201 S1_V02N0201
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arc: E1_H02E0301 S1_V02N0301
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arc: N1_V02N0101 S1_V02N0001
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arc: S3_V06S0203 E3_H06W0203
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.tile CIB_R1C11:CIB
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arc: S3_V06S0103 E3_H06W0103
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C14:CIB
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arc: S3_V06S0103 E1_H01W0100
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.tile CIB_R1C15:CIB
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arc: H01W0100 JQ0
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arc: JA0 V02N0501
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arc: JB0 V01N0001
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.tile CIB_R1C17:CIB
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arc: S3_V06S0003 E3_H06W0003
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C20:CIB
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arc: S3_V06S0003 H06W0003
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.tile CIB_R1C22:CIB
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arc: E1_H02E0701 S3_V06N0203
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.tile CIB_R1C23:CIB
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arc: JA0 H02E0701
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arc: S3_V06S0003 E3_H06W0003
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arc: W3_H06W0003 E3_H06W0003
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enum: CIB.JB0MUX 0
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.tile CIB_R1C24:CIB
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arc: JA0 H02W0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C25:CIB
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arc: W1_H02W0501 S3_V06N0303
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.tile CIB_R1C26:CIB
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arc: S3_V06S0003 H06W0003
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.tile CIB_R1C27:CIB
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arc: JA0 V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C28:CIB
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arc: S3_V06S0303 E1_H01W0100
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.tile CIB_R1C29:CIB
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arc: E3_H06E0003 JQ0
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arc: H01W0100 JQ0
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C2:CIB
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arc: S3_V06S0103 H06W0103
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.tile CIB_R1C32:CIB
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arc: S3_V06S0003 H06E0003
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.tile CIB_R1C33:CIB
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arc: E1_H02E0501 V02N0501
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arc: JA0 V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C34:CIB
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C35:CIB
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arc: E3_H06E0003 W3_H06E0003
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arc: S3_V06S0003 W3_H06E0003
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arc: S3_V06S0103 E3_H06W0103
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.tile CIB_R1C36:CIB
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0303 E1_H01W0100
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.tile CIB_R1C37:CIB
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arc: H01W0100 JQ0
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.tile CIB_R1C38:CIB
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arc: S3_V06S0003 H06E0003
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.tile CIB_R1C41:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: E3_H06E0103 W3_H06E0003
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arc: S3_V06S0003 W3_H06E0003
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C42:CIB
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arc: JA0 H02E0501
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arc: JB0 V02N0301
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C43:CIB
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arc: H00R0000 S1_V02N0401
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arc: JA0 H00R0000
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enum: CIB.JB0MUX 0
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.tile CIB_R1C44:CIB
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arc: E1_H02E0501 S1_V02N0501
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arc: JA0 E1_H02W0701
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arc: S3_V06S0103 H06E0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C45:CIB
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C46:CIB
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arc: W1_H02W0701 V02N0701
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.tile CIB_R1C47:CIB
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arc: E1_H02E0001 S3_V06N0003
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arc: E1_H02E0401 S3_V06N0203
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arc: E1_H02E0701 S1_V02N0701
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arc: JA0 S1_V02N0501
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arc: JB0 V02N0301
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C48:CIB
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arc: E1_H02E0501 V02N0501
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arc: H00R0000 H02E0401
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arc: JA0 H00R0000
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arc: JD7 H02E0001
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enum: CIB.JB0MUX 0
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.tile CIB_R1C49:CIB
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arc: JA0 W1_H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C50:CIB
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arc: JA0 W1_H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C5:CIB
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arc: S3_V06S0103 E3_H06W0103
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C8:CIB
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arc: S3_V06S0103 H06W0103
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.tile CIB_R20C1:CIB_LR
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arc: E1_H01E0101 E3_H06W0203
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arc: E1_H02E0001 S3_V06N0003
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arc: E1_H02E0201 E3_H06W0103
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arc: E1_H02E0401 V02N0401
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arc: N1_V02N0001 S3_V06N0003
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arc: N1_V02N0301 S3_V06N0003
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.tile CIB_R20C89:CIB_LR
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arc: JA3 W1_H02E0701
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arc: S1_V02S0301 H01E0101
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arc: S1_V02S0501 H06E0303
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arc: S1_V02S0701 W3_H06E0203
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enum: CIB.JB3MUX 0
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.tile CIB_R21C1:CIB_LR
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arc: E1_H01E0001 E3_H06W0003
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arc: E1_H01E0101 E3_H06W0203
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arc: E1_H02E0001 E3_H06W0003
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arc: E1_H02E0201 S1_V02N0201
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arc: E1_H02E0401 E3_H06W0203
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arc: N1_V02N0001 E3_H06W0003
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arc: N1_V02N0201 S1_V02N0201
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arc: N1_V02N0301 S1_V02N0201
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arc: N1_V02N0401 S1_V02N0101
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arc: S1_V02S0001 E3_H06W0003
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arc: S3_V06S0203 E3_H06W0203
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.tile CIB_R22C10:CIB_DSP
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arc: E1_H02E0001 V06S0003
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arc: E1_H02E0101 V06S0103
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arc: E1_H02E0201 V02S0201
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arc: E1_H02E0301 V02S0301
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arc: E3_H06E0003 JQ3
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arc: E3_H06E0103 JQ2
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arc: E3_H06E0203 N1_V01S0000
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arc: H00R0100 H02E0701
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arc: H01W0100 JF1
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arc: JB0 W1_H02E0101
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arc: JB1 W1_H02E0301
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arc: JB2 W1_H02E0101
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arc: JB3 W1_H02E0301
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arc: JB4 W1_H02E0101
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arc: JB5 W1_H02E0301
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arc: JB6 V02N0701
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arc: JB7 H02W0101
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arc: JD0 W1_H02E0001
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arc: JD1 W1_H02E0201
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arc: JD2 W1_H02E0001
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arc: JD3 W1_H02E0201
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arc: JD4 W1_H02E0001
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arc: JD5 V02N0401
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arc: JD6 N1_V02S0401
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arc: JD7 H00R0100
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arc: JLSR0 E1_H02W0301
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arc: JLSR1 E1_H02W0301
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arc: N1_V01N0101 JQ1
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arc: N1_V02N0001 JQ0
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arc: N1_V02N0101 E1_H02W0101
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|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 JF2
|
|
arc: W1_H02W0301 JF3
|
|
arc: W3_H06W0003 JF0
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C11:CIB_DSP
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02W0501
|
|
arc: JB0 H02E0101
|
|
arc: JB1 V00T0000
|
|
arc: JB2 H00R0100
|
|
arc: JB3 N1_V02S0101
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 N1_V02S0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 N1_V02S0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 V02N0601
|
|
arc: JD5 H02E0001
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 W1_H02E0001
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C12:CIB_DSP
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: JB0 V02S0101
|
|
arc: JB1 H02E0301
|
|
arc: JB2 V02S0101
|
|
arc: JB3 H02E0301
|
|
arc: JB4 V00B0100
|
|
arc: JB5 H02E0301
|
|
arc: JB6 V00B0000
|
|
arc: JB7 W1_H02E0301
|
|
arc: JCE3 E1_H02W0101
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V02S0201
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 V02S0201
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 V00B0000
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 V00T0000
|
|
arc: JLSR1 V00T0000
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C13:CIB_DSP
|
|
arc: E1_H01E0101 JQ7
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: N1_V01N0001 JQ0
|
|
arc: N1_V01N0101 JQ6
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 JQ3
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C14:CIB_DSP
|
|
arc: E1_H01E0101 JQ7
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V01N0001 JQ0
|
|
arc: N1_V01N0101 JQ6
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 JQ3
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N1_V02N0601 JQ4
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C15:CIB_DSP
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00R0000 H02W0401
|
|
arc: JB2 V02S0301
|
|
arc: JB3 V02S0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 N1_V01S0000
|
|
arc: JB6 S1_V02N0501
|
|
arc: JB7 W1_H02E0101
|
|
arc: JD2 S1_V02N0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 V02N0601
|
|
arc: JD6 H02W0001
|
|
arc: JD7 V02S0601
|
|
arc: JLSR0 V00T0000
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile CIB_R22C16:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: JB0 V00B0000
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00R0000
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 V02N0701
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 V02N0701
|
|
arc: JB7 W1_H02E0101
|
|
arc: JD0 H02E0001
|
|
arc: JD1 V00B0100
|
|
arc: JD2 H02E0201
|
|
arc: JD3 W1_H02E0001
|
|
arc: JD4 H02E0201
|
|
arc: JD5 W1_H02E0001
|
|
arc: JD6 H02E0201
|
|
arc: JD7 W1_H02E0001
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 V01N0001
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C17:CIB_DSP
|
|
arc: H00R0000 V02S0601
|
|
arc: JB0 H02E0101
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H02E0101
|
|
arc: JB3 W1_H02E0101
|
|
arc: JCE0 H00R0000
|
|
arc: JCE1 H00R0000
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 H02E0001
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 H02E0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
|
|
.tile CIB_R22C18:CIB_DSP
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S1_V02S0301 V01N0101
|
|
|
|
.tile CIB_R22C19:CIB_DSP
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
|
|
.tile CIB_R22C1:CIB_LR_S
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
|
|
.tile CIB_R22C20:CIB_DSP
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R22C21:CIB_DSP
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0103 V06S0103
|
|
arc: W3_H06W0203 V06S0203
|
|
arc: W3_H06W0303 V06S0303
|
|
|
|
.tile CIB_R22C22:CIB_DSP
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
|
|
.tile CIB_R22C23:CIB_DSP
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0501 H02W0501
|
|
|
|
.tile CIB_R22C24:CIB_DSP
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
|
|
.tile CIB_R22C25:CIB_DSP
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0701 H02W0701
|
|
|
|
.tile CIB_R22C26:CIB_DSP
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
|
|
.tile CIB_R22C27:CIB_DSP
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R22C28:CIB_DSP
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile CIB_R22C29:CIB_DSP
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile CIB_R22C2:CIB_DSP
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
|
|
.tile CIB_R22C30:CIB_DSP
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R22C31:CIB_DSP
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: W1_H02W0001 V06N0003
|
|
|
|
.tile CIB_R22C32:CIB_DSP
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 V01N0101
|
|
|
|
.tile CIB_R22C33:CIB_DSP
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
|
|
.tile CIB_R22C34:CIB_DSP
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
|
|
.tile CIB_R22C35:CIB_DSP
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 V01N0101
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
|
|
.tile CIB_R22C36:CIB_DSP
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S3_V06S0303 N1_V02S0601
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile CIB_R22C37:CIB_DSP
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile CIB_R22C38:CIB_DSP
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0701 V01N0101
|
|
|
|
.tile CIB_R22C39:CIB_DSP
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S1_V02S0301 H02E0301
|
|
|
|
.tile CIB_R22C3:CIB_DSP
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
|
|
.tile CIB_R22C40:CIB_DSP
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
|
|
.tile CIB_R22C41:CIB_DSP
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
|
|
.tile CIB_R22C44:CIB_DSP
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
|
|
.tile CIB_R22C47:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile CIB_R22C4:CIB_DSP
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 JQ2
|
|
arc: E1_H02E0301 JQ3
|
|
arc: E1_H02E0501 JQ5
|
|
arc: E1_H02E0601 JQ4
|
|
arc: E3_H06E0203 JQ7
|
|
arc: E3_H06E0303 JQ6
|
|
arc: N1_V01N0101 JQ0
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: S1_V02S0101 JQ1
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 H06W0203
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C53:CIB_DSP
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile CIB_R22C59:CIB_DSP
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R22C5:CIB_DSP
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 JQ1
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0203 JQ7
|
|
arc: E3_H06E0303 JQ6
|
|
arc: N1_V01N0101 JQ0
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0301 JQ3
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 JQ5
|
|
arc: S1_V02S0601 JQ4
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V01S0100 JQ2
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C65:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R22C6:CIB_DSP
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: H00R0000 V02S0601
|
|
arc: JB2 N1_V02S0101
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 V02N0501
|
|
arc: JB6 V00B0100
|
|
arc: JB7 N1_V02S0501
|
|
arc: JD2 N1_V01S0000
|
|
arc: JD3 H02E0201
|
|
arc: JD4 S1_V02N0601
|
|
arc: JD5 V02S0401
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 H02W0301
|
|
arc: JLSR1 H02W0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 S1_V02N0101
|
|
|
|
.tile CIB_R22C71:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R22C77:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R22C7:CIB_DSP
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: JB0 V00B0000
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 V00B0100
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 V00B0100
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 H02E0201
|
|
arc: JD1 S1_V02N0001
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V02S0201
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 H00R0100
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 H00R0100
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W3_H06W0103 N1_V01S0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C83:CIB_DSP
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R22C89:CIB_LR_S
|
|
arc: JA0 N1_V02S0701
|
|
arc: JA3 N1_V02S0501
|
|
arc: JB0 N1_V02S0301
|
|
arc: W3_H06W0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R22C8:CIB_DSP
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0203 JQ7
|
|
arc: E3_H06E0303 JQ5
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 H02W0701
|
|
arc: H01W0000 JF6
|
|
arc: H01W0100 JF4
|
|
arc: JB0 V02S0301
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 V02S0301
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 S1_V02N0501
|
|
arc: JB5 H02W0301
|
|
arc: JB6 H02E0101
|
|
arc: JB7 V02S0501
|
|
arc: JCE0 V02S0201
|
|
arc: JCE1 V02S0201
|
|
arc: JCE2 H00L0000
|
|
arc: JCE3 H00L0000
|
|
arc: JD0 V02N0001
|
|
arc: JD1 V02S0001
|
|
arc: JD2 V02N0001
|
|
arc: JD3 V02S0001
|
|
arc: JD4 E1_H02W0001
|
|
arc: JD5 H00R0100
|
|
arc: JD6 H02E0001
|
|
arc: JD7 S1_V02N0601
|
|
arc: N1_V01N0001 JQ4
|
|
arc: N1_V01N0101 JQ6
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 JF5
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 JF7
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile CIB_R22C9:CIB_DSP
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0003 JQ3
|
|
arc: E3_H06E0103 JQ2
|
|
arc: E3_H06E0203 JQ4
|
|
arc: E3_H06E0303 JQ5
|
|
arc: H00R0000 H02E0601
|
|
arc: H01W0000 JF6
|
|
arc: H01W0100 JF2
|
|
arc: JB0 E1_H02W0301
|
|
arc: JB1 V02N0101
|
|
arc: JB2 V02N0301
|
|
arc: JB3 H02E0301
|
|
arc: JB4 V02N0701
|
|
arc: JB5 V02S0501
|
|
arc: JB6 V02N0701
|
|
arc: JB7 H02E0301
|
|
arc: JD0 V00B0100
|
|
arc: JD1 V00T0100
|
|
arc: JD2 N1_V02S0201
|
|
arc: JD3 H00R0000
|
|
arc: JD4 H02E0001
|
|
arc: JD5 V02N0601
|
|
arc: JD6 H02E0001
|
|
arc: JD7 V02N0601
|
|
arc: N1_V01N0001 JQ1
|
|
arc: N1_V01N0101 JQ6
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 JQ7
|
|
arc: S1_V02S0101 JF3
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0501 JF7
|
|
arc: S1_V02S0701 JF5
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 JF4
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0003 JF0
|
|
arc: W3_H06W0103 JF1
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R23C1:CIB_LR
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile CIB_R24C1:CIB_LR
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile CIB_R25C1:CIB_LR
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
|
|
.tile CIB_R26C1:CIB_LR
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: JA0 H02W0501
|
|
arc: JA3 H02W0701
|
|
arc: JB3 E1_H01W0100
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R27C1:CIB_LR
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
|
|
.tile CIB_R28C1:CIB_LR
|
|
arc: JA3 V02S0501
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R29C1:CIB_LR
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: JA0 V02S0701
|
|
arc: JA3 H02W0701
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R29C89:CIB_LR
|
|
arc: H00R0100 H02E0701
|
|
arc: JA3 V02N0701
|
|
arc: JB3 H00R0100
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R30C1:CIB_LR
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
|
|
.tile CIB_R30C89:CIB_LR
|
|
arc: N1_V02N0701 H01E0101
|
|
|
|
.tile CIB_R31C1:CIB_LR
|
|
arc: JA0 H02W0701
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0501 H06W0303
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R31C89:CIB_LR
|
|
arc: JA0 N1_V02S0501
|
|
arc: JB0 N1_V02S0301
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R32C1:CIB_LR
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 V02S0501
|
|
arc: JA3 V00T0000
|
|
arc: JB3 H02W0301
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00T0000 H02W0001
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R32C89:CIB_LR
|
|
arc: JA0 V02N0701
|
|
arc: JA3 V02N0501
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R33C1:CIB_LR
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
|
|
.tile CIB_R33C89:CIB_LR
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
|
|
.tile CIB_R34C10:CIB_EBR
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0601 H06W0303
|
|
|
|
.tile CIB_R34C11:CIB_EBR
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
|
|
.tile CIB_R34C12:CIB_EBR
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H02E0601
|
|
|
|
.tile CIB_R34C13:CIB_EBR
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: W3_H06W0303 N3_V06S0303
|
|
|
|
.tile CIB_R34C14:CIB_EBR
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: W1_H02W0601 V06S0303
|
|
|
|
.tile CIB_R34C15:CIB_EBR
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
|
|
.tile CIB_R34C16:CIB_EBR
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile CIB_R34C17:CIB_EBR
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
|
|
.tile CIB_R34C18:CIB_EBR
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
|
|
.tile CIB_R34C19:CIB_EBR
|
|
arc: N1_V02N0601 V01N0001
|
|
|
|
.tile CIB_R34C1:CIB_LR_S
|
|
arc: E3_H06E0303 V06N0303
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: JA0 H00R0000
|
|
arc: JA3 E1_H02W0701
|
|
arc: JB0 N1_V02S0101
|
|
arc: N1_V01N0101 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R34C20:CIB_EBR
|
|
arc: E1_H02E0501 V06S0303
|
|
|
|
.tile CIB_R34C21:CIB_EBR
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
|
|
.tile CIB_R34C22:CIB_EBR
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: H01W0000 JQ0
|
|
arc: H01W0100 JQ1
|
|
arc: JA0 H02W0501
|
|
arc: JA1 H00L0000
|
|
arc: JA2 H00L0100
|
|
arc: JA3 S1_V02N0501
|
|
arc: JA6 H02E0701
|
|
arc: JA7 V00T0100
|
|
arc: JB1 V02S0301
|
|
arc: JB3 S1_V02N0101
|
|
arc: JC0 H02W0401
|
|
arc: JC1 S1_V02N0401
|
|
arc: JC2 H00R0100
|
|
arc: JC3 V02N0601
|
|
arc: JC6 N1_V02S0201
|
|
arc: JC7 V00T0000
|
|
arc: JCLK0 G_HPBX0000
|
|
arc: JD0 V00B0100
|
|
arc: JD2 H00R0000
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N3_V06N0003 JQ3
|
|
arc: N3_V06N0103 JQ2
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02S0701
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JCE1MUX 1
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R34C23:CIB_EBR
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02S0701
|
|
arc: JA0 H02E0701
|
|
arc: JA1 H00R0000
|
|
arc: JA4 V00B0000
|
|
arc: JA5 V00T0000
|
|
arc: JA6 H02W0701
|
|
arc: JA7 N1_V02S0101
|
|
arc: JC0 N1_V02S0601
|
|
arc: JC1 H00R0100
|
|
arc: JC4 V00B0100
|
|
arc: JC5 V00T0100
|
|
arc: JC6 V02S0001
|
|
arc: JC7 H02W0601
|
|
arc: JCLK0 G_HPBX0000
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 V06S0303
|
|
enum: CIB.JLSR1MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE1MUX 1
|
|
|
|
.tile CIB_R34C24:CIB_EBR
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: H01W0000 JQ2
|
|
arc: H01W0100 JQ3
|
|
arc: JA0 H02E0501
|
|
arc: JA1 H00L0000
|
|
arc: JA2 H00L0100
|
|
arc: JA3 W1_H02E0501
|
|
arc: JA6 H02W0501
|
|
arc: JA7 V00T0100
|
|
arc: JB3 H02E0301
|
|
arc: JB5 H00R0000
|
|
arc: JC0 H02E0601
|
|
arc: JC1 S1_V02N0401
|
|
arc: JC2 H00R0100
|
|
arc: JC3 V02S0601
|
|
arc: JC6 V00T0000
|
|
arc: JC7 W1_H02E0401
|
|
arc: JCLK0 G_HPBX0000
|
|
arc: JD2 H02E0201
|
|
arc: JD4 N1_V02S0401
|
|
arc: JLSR1 H02W0301
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N3_V06N0303 JQ5
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0203 JQ4
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JCE1MUX 1
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R34C25:CIB_EBR
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: JA0 H02E0701
|
|
arc: JA1 W1_H02E0701
|
|
arc: JA4 V00B0000
|
|
arc: JA5 N1_V02S0101
|
|
arc: JA6 H00L0000
|
|
arc: JA7 V00T0100
|
|
arc: JC0 V02S0601
|
|
arc: JC1 H02E0601
|
|
arc: JC4 N1_V02S0201
|
|
arc: JC5 H02W0601
|
|
arc: JC6 V00T0000
|
|
arc: JC7 S1_V02N0201
|
|
arc: JCLK0 G_HPBX0000
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0501 V02S0501
|
|
enum: CIB.JLSR1MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JCE3MUX 1
|
|
enum: CIB.JCE2MUX 1
|
|
enum: CIB.JCE1MUX 1
|
|
|
|
.tile CIB_R34C26:CIB_EBR
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: W1_H02W0601 V02S0601
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JLSR0MUX 0
|
|
enum: CIB.JCE1MUX 1
|
|
enum: CIB.JCE0MUX 1
|
|
enum: CIB.JCLK0MUX 0
|
|
|
|
.tile CIB_R34C27:CIB_EBR
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile CIB_R34C28:CIB_EBR
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 V01N0101
|
|
|
|
.tile CIB_R34C29:CIB_EBR
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
|
|
.tile CIB_R34C2:CIB_EBR
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
|
|
.tile CIB_R34C30:CIB_EBR
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
|
|
.tile CIB_R34C31:CIB_EBR
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
|
|
.tile CIB_R34C32:CIB_EBR
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0501 H02W0501
|
|
|
|
.tile CIB_R34C33:CIB_EBR
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
|
|
.tile CIB_R34C35:CIB_EBR
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
|
|
.tile CIB_R34C36:CIB_EBR
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
|
|
.tile CIB_R34C37:CIB_EBR
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0601 V01N0001
|
|
|
|
.tile CIB_R34C38:CIB_EBR
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
|
|
.tile CIB_R34C3:CIB_EBR
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
|
|
.tile CIB_R34C47:CIB_EBR
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
|
|
.tile CIB_R34C4:CIB_EBR
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0501 H02W0501
|
|
|
|
.tile CIB_R34C53:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R34C59:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C5:CIB_EBR
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
|
|
.tile CIB_R34C65:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C6:CIB_EBR
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0401 H02E0401
|
|
|
|
.tile CIB_R34C71:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C77:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C7:CIB_EBR
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
|
|
.tile CIB_R34C83:CIB_EBR
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R34C89:CIB_LR_S
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R34C8:CIB_EBR
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 H02E0601
|
|
|
|
.tile CIB_R34C9:CIB_EBR
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
|
|
.tile CIB_R35C1:CIB_LR
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0303 JQ5
|
|
arc: H00L0100 H02W0101
|
|
arc: JA0 H00L0100
|
|
arc: JA3 V00B0000
|
|
arc: JB3 E1_H01W0100
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 E1_H02W0601
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R35C89:CIB_LR
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0100 JQ5
|
|
arc: JA0 H01E0001
|
|
arc: JA3 W1_H02E0501
|
|
arc: JB0 H00R0100
|
|
arc: JB3 H00R0000
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R37C1:CIB_LR
|
|
arc: H00R0100 H02W0701
|
|
arc: JA0 N1_V02S0701
|
|
arc: JA3 N1_V02S0501
|
|
arc: JB0 N1_V02S0101
|
|
arc: JB3 H00R0100
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R37C89:CIB_LR
|
|
arc: JA0 N1_V02S0701
|
|
arc: JA3 N1_V02S0501
|
|
arc: JB0 N1_V02S0101
|
|
arc: W3_H06W0303 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R38C1:CIB_LR
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: JA0 E1_H01E0001
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R38C89:CIB_LR
|
|
arc: W3_H06W0303 JF5
|
|
|
|
.tile CIB_R5C1:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R5C89:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C18:CIB
|
|
arc: JA0 N1_V02S0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C3:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C42:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C43:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C45:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
arc: JA0 N1_V02S0701
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile MIB_R0C15:PIOT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C23:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C24:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C27:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C29:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C33:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C34:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C37:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C44:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C45:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C47:PIOT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C48:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C49:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C50:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C12:EBR_SPINE_UL1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C50:EBR_SPINE_UR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R11C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R12C0:PICL1
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R12C90:PICR1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R13C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C0:PICL1_DQS0
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C90:PICR1_DQS0
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C90:PICR2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C0:PICL0_DQS2
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R18C0:PICL1_DQS3
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C15:PICT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R1C23:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C24:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C27:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C29:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C33:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C34:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C37:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C44:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C45:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C47:PICT0
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R1C48:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C49:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C50:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C90:PICR0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C90:PICR1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R22C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R26C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C0:PICL1_DQS0
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C0:PICL2_DQS1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C0:PICL0_DQS2
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R30C0:PICL1_DQS3
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R31C0:PICL2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R32C90:PICR0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R33C90:PICR1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R34C90:MIB_CIB_LR_A
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R35C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R36C0:PICL1
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R36C90:PICR1
|
|
enum: PIOB.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R37C0:PICL2
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.BASE_TYPE BIDIR_LVCMOS33
|
|
|
|
.tile MIB_R37C90:PICR2
|
|
enum: PIOC.BASE_TYPE BIDIR_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C0:PICL1_DQS0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C90:PICR1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R58C12:EBR_SPINE_LL1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R58C30:EBR_SPINE_LL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C50:EBR_SPINE_LR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C1:BANKREF6
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile MIB_R71C6:EFB2_PICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C89:BANKREF3
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile R11C10:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A1 E1_H02W0501
|
|
arc: A3 H02E0701
|
|
arc: A4 S1_V02N0101
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: C1 F4
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 Q4
|
|
arc: CE0 H00L0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00T0100
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00T0100 F3
|
|
arc: V01S0000 F1
|
|
word: SLICEC.K0.INIT 0010001000001010
|
|
word: SLICEB.K1.INIT 1010101010101000
|
|
word: SLICEA.K1.INIT 0000110100000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C11:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: A0 F7
|
|
arc: A1 F5
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 E1_H01E0001
|
|
arc: A5 S1_V02N0301
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 S1_V02N0101
|
|
arc: B5 V00B0100
|
|
arc: B7 V01S0000
|
|
arc: C0 H02W0601
|
|
arc: C1 H02W0601
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 H00L0100
|
|
arc: C5 S1_V02N0001
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D1 V01S0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 W1_H02E0201
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0001 F0
|
|
arc: S3_V06S0103 F1
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 F3
|
|
word: SLICED.K1.INIT 0011000001010000
|
|
word: SLICEB.K0.INIT 1010101010101000
|
|
word: SLICEA.K0.INIT 0100010100000000
|
|
word: SLICEB.K1.INIT 0001110100000000
|
|
word: SLICEC.K1.INIT 1111111000000000
|
|
word: SLICEA.K1.INIT 0000000010001010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C12:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A2 F7
|
|
arc: A4 S1_V02N0101
|
|
arc: A7 Q7
|
|
arc: B2 H00L0000
|
|
arc: B4 S1_V02N0701
|
|
arc: B7 V00T0000
|
|
arc: C2 F4
|
|
arc: C4 Q4
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V01S0100
|
|
arc: D4 H02W0201
|
|
arc: D7 S1_V02N0601
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0201 F2
|
|
arc: V00T0000 Q0
|
|
word: SLICED.K1.INIT 0101001100000000
|
|
word: SLICEC.K0.INIT 1100110011001000
|
|
word: SLICEB.K0.INIT 0100000001010000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R11C13:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W3_H06W0203 V06N0203
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 H02E0301
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C14:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00B0000 V02N0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: W3_H06W0103 V06N0103
|
|
arc: A0 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V02N0701
|
|
arc: A4 V02N0301
|
|
arc: A6 F7
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 S1_V02N0301
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 H00R0000
|
|
arc: B6 F3
|
|
arc: B7 V00B0100
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 W1_H02E0401
|
|
arc: C4 V01N0101
|
|
arc: C6 V02N0001
|
|
arc: C7 F4
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D2 H02W0201
|
|
arc: D3 F0
|
|
arc: D4 H02E0201
|
|
arc: D6 V01N0001
|
|
arc: D7 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q2
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K0.INIT 0000101000100010
|
|
word: SLICEB.K0.INIT 1111111000000000
|
|
word: SLICEA.K0.INIT 0000000010111111
|
|
word: SLICEB.K1.INIT 0100010100000000
|
|
word: SLICED.K1.INIT 0000110100000000
|
|
word: SLICED.K0.INIT 1110000011101111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R11C15:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0701
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0203 V06N0203
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 F0
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R11C16:PLC2
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
|
|
.tile R11C18:PLC2
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R11C22:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
|
|
.tile R11C23:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: B0 V01N0001
|
|
arc: B1 V01N0001
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: M0 V00T0000
|
|
arc: M1 V01S0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 0000101000001100
|
|
word: SLICEA.K1.INIT 1111101011111100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C24:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 H02W0601
|
|
arc: C1 W1_H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0000 Q6
|
|
word: SLICEA.K0.INIT 0000110000001010
|
|
word: SLICEA.K1.INIT 1111110011111010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C25:PLC2
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 H00R0000
|
|
arc: A1 H00R0000
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 V02N0401
|
|
arc: C1 S1_V02N0601
|
|
arc: CE0 V02S0201
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 0000101000001100
|
|
word: SLICEA.K1.INIT 1111101011111100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C26:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 H02W0601
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A5 V02N0101
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B5 H02W0101
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C5 E1_H02W0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0201
|
|
arc: D5 S1_V02N0601
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICEC.K1.INIT 1100000010001000
|
|
word: SLICEA.K0.INIT 0000110000001010
|
|
word: SLICEA.K1.INIT 1111110011111010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C27:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 S1_V02N0701
|
|
arc: B0 H02W0301
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 H02E0401
|
|
arc: C3 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 H02W0201
|
|
arc: D3 H00R0000
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 H02E0501
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q6
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 0000110000001010
|
|
word: SLICEB.K1.INIT 1111111111001010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C28:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A2 H02E0501
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V02N0101
|
|
arc: A5 V00B0000
|
|
arc: A6 F5
|
|
arc: A7 N1_V02S0101
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 H00L0000
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 V02S0501
|
|
arc: B6 N1_V02S0701
|
|
arc: B7 V02N0701
|
|
arc: C0 H02E0601
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 N1_V02S0401
|
|
arc: C3 F4
|
|
arc: C4 H02W0601
|
|
arc: C5 H02W0601
|
|
arc: C6 S1_V02N0201
|
|
arc: C7 W1_H02E0601
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 V00B0100
|
|
arc: D2 V01S0100
|
|
arc: D3 F0
|
|
arc: D4 V00B0000
|
|
arc: D5 V02N0401
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 H00R0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 W1_H02E0601
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 1111111110110011
|
|
word: SLICEB.K1.INIT 1111100011111111
|
|
word: SLICED.K0.INIT 1110101011111111
|
|
word: SLICEA.K0.INIT 0000001100110011
|
|
word: SLICEC.K0.INIT 1100000010100000
|
|
word: SLICED.K1.INIT 1010110000000000
|
|
word: SLICEA.K1.INIT 0000001100110011
|
|
word: SLICEC.K1.INIT 1101000010000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C29:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: A0 F7
|
|
arc: A1 F7
|
|
arc: A2 E1_H01E0001
|
|
arc: A4 H02W0701
|
|
arc: A5 H02W0701
|
|
arc: A6 N1_V01S0100
|
|
arc: B3 H00R0000
|
|
arc: B4 V01S0000
|
|
arc: B5 V01S0000
|
|
arc: B7 V02N0501
|
|
arc: C0 V02N0601
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H02W0601
|
|
arc: C3 N1_V02S0601
|
|
arc: C4 V00T0000
|
|
arc: C5 V00T0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 V01S0100
|
|
arc: D4 V01N0001
|
|
arc: D5 V01N0001
|
|
arc: D6 V00B0000
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F0
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 F6
|
|
word: SLICEB.K1.INIT 0000000000111111
|
|
word: SLICED.K1.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 0000010101010101
|
|
word: SLICED.K0.INIT 1010101000000000
|
|
word: SLICEC.K0.INIT 0000110100001000
|
|
word: SLICEC.K1.INIT 1111110111111000
|
|
word: SLICEA.K0.INIT 0000010101010101
|
|
word: SLICEA.K1.INIT 0000010101010101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R11C2:PLC2
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: D6 S1_V02N0401
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F6
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R11C30:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A4 V00T0000
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 F3
|
|
arc: B1 Q1
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 H02W0301
|
|
arc: B7 H02W0301
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V02N0001
|
|
arc: C5 V00T0000
|
|
arc: C6 V01N0101
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V01S0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 F2
|
|
arc: D5 F2
|
|
arc: D6 H00L0100
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0100
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q5
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 Q5
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0501 Q7
|
|
word: SLICEC.K1.INIT 0000000000111111
|
|
word: SLICEC.K0.INIT 0000000001011111
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICED.K0.INIT 0010001100100000
|
|
word: SLICED.K1.INIT 1110111111101100
|
|
word: SLICEA.K0.INIT 0000001100110011
|
|
word: SLICEA.K1.INIT 0000000000111111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R11C31:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: A0 V02N0701
|
|
arc: A1 V02N0501
|
|
arc: A2 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 H02E0701
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 V02N0701
|
|
arc: B5 H00L0000
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 V01N0101
|
|
arc: C5 V01N0101
|
|
arc: CE0 H02W0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 H02E0201
|
|
arc: D2 V01S0100
|
|
arc: D3 V01S0100
|
|
arc: D4 N1_V02S0601
|
|
arc: D5 N1_V02S0601
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 F4
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00B0100
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 N1_V01N0101
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 Q7
|
|
word: SLICEC.K0.INIT 0101010000010000
|
|
word: SLICEC.K1.INIT 1111111011011100
|
|
word: SLICEA.K0.INIT 0011001000010000
|
|
word: SLICEA.K1.INIT 1110111011111100
|
|
word: SLICEB.K0.INIT 0011001000000010
|
|
word: SLICEB.K1.INIT 1111111011001110
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C32:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: B0 H02W0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B5 V02N0701
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00L0000
|
|
arc: C3 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02S0001
|
|
arc: D2 H02E0201
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 S1_V02N0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0001 F0
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0301 Q1
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEC.K1.INIT 1100110000000000
|
|
word: SLICEA.K1.INIT 0000010101010101
|
|
word: SLICEA.K0.INIT 0001010100010101
|
|
word: SLICEB.K0.INIT 0000000010111000
|
|
word: SLICEB.K1.INIT 1111101111111000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C33:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 V01N0001
|
|
arc: B1 V01N0001
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0501
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 F0
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H01W0100
|
|
arc: M4 V00B0100
|
|
arc: M5 V01S0000
|
|
arc: M6 H02W0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 F4
|
|
arc: W1_H02W0401 Q6
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0203 Q7
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEB.K0.INIT 0000000011001010
|
|
word: SLICEB.K1.INIT 1111111111001010
|
|
word: SLICEC.K0.INIT 0000000010101100
|
|
word: SLICEC.K1.INIT 1111111110101100
|
|
word: SLICEA.K0.INIT 0000000010101100
|
|
word: SLICEA.K1.INIT 1111111110101100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C34:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0501
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 S1_V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0001
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M5 V01S0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEA.K0.INIT 0000000010111000
|
|
word: SLICEA.K1.INIT 1111111110111000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C35:PLC2
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 V02N0501
|
|
arc: A1 V01N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 V02N0101
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 Q6
|
|
arc: V00T0100 Q3
|
|
word: SLICEA.K0.INIT 0000000011011000
|
|
word: SLICEA.K1.INIT 1111111110111000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C36:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W3_H06W0203 V01N0001
|
|
|
|
.tile R11C38:PLC2
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R11C41:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R11C47:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R11C4:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
|
|
.tile R11C5:PLC2
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: B2 H00R0000
|
|
arc: B3 Q3
|
|
arc: C2 N1_V01N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 E1_H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: F2 F5B_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: V01S0000 Q4
|
|
word: SLICEB.K0.INIT 1111000011001100
|
|
word: SLICEB.K1.INIT 1111111111001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R11C6:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: A2 S1_V02N0701
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B5 V02N0501
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 S1_V02N0401
|
|
arc: C5 H01E0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 H02W0201
|
|
arc: D2 V02N0001
|
|
arc: D5 F2
|
|
arc: E1_H01E0101 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02W0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 H02E0601
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICEB.K0.INIT 1000101000000000
|
|
word: SLICEC.K1.INIT 0000000000111111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R11C7:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A1 F7
|
|
arc: A4 N1_V01N0101
|
|
arc: A7 Q7
|
|
arc: B1 V02N0301
|
|
arc: B3 Q3
|
|
arc: B4 S1_V02N0701
|
|
arc: B7 S1_V02N0501
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 V02N0401
|
|
arc: C3 H00L0000
|
|
arc: C4 H02E0601
|
|
arc: C7 H02W0601
|
|
arc: CE0 H02E0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H01E0101
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 F2
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 F4
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: S3_V06S0103 F1
|
|
word: SLICED.K1.INIT 0000101100000000
|
|
word: SLICEA.K1.INIT 1100100011111011
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICEC.K0.INIT 1000110000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R11C8:PLC2
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 V00T0000
|
|
arc: A4 F7
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 Q7
|
|
arc: B0 E1_H01W0100
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 V02N0301
|
|
arc: B4 V02N0501
|
|
arc: B6 V01S0000
|
|
arc: B7 N1_V02S0501
|
|
arc: C0 E1_H02W0601
|
|
arc: C2 H00L0000
|
|
arc: C3 F4
|
|
arc: C4 Q4
|
|
arc: C6 Q6
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: D2 H02W0201
|
|
arc: D3 F0
|
|
arc: D4 S1_V02N0601
|
|
arc: D6 H02E0201
|
|
arc: D7 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 W1_H02E0301
|
|
arc: M0 H01E0001
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S3_V06S0003 F3
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0601 F6
|
|
word: SLICED.K0.INIT 0001000100000101
|
|
word: SLICEA.K0.INIT 1011101011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000110101
|
|
word: SLICEC.K0.INIT 0100000001000100
|
|
word: SLICEB.K0.INIT 0011000100000000
|
|
word: SLICEB.K1.INIT 1100100011111011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C9:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 S1_V02N0501
|
|
arc: B0 V00T0000
|
|
arc: B2 S1_V02N0101
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 S1_V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02N0201
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D2 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEB.K0.INIT 0101010100010101
|
|
word: SLICEA.K0.INIT 1000101010101010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R12C10:PLC2
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A2 V00T0000
|
|
arc: A4 F7
|
|
arc: A6 V02N0301
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 H02E0301
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V02N0701
|
|
arc: C0 V02N0401
|
|
arc: C2 V02N0601
|
|
arc: C4 E1_H01E0101
|
|
arc: C6 F4
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V02N0201
|
|
arc: D2 E1_H02W0001
|
|
arc: D4 F2
|
|
arc: D6 V01N0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S3_V06S0303 F6
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICED.K1.INIT 0010001100110011
|
|
word: SLICEB.K0.INIT 1000000011000000
|
|
word: SLICEC.K0.INIT 0000000001011111
|
|
word: SLICED.K0.INIT 1010111110001101
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R12C11:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C12:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A2 V02N0701
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: C0 H00R0100
|
|
arc: C1 H00L0100
|
|
arc: C2 N1_V01S0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: D2 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1011101011111111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R12C13:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R12C14:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A2 W1_H02E0701
|
|
arc: A7 Q7
|
|
arc: B2 H00R0100
|
|
arc: B7 V02N0501
|
|
arc: C2 W1_H02E0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0001
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 Q0
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0701 F7
|
|
word: SLICEB.K0.INIT 1111001011111111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000001000111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C15:PLC2
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 W1_H02E0701
|
|
arc: A2 V00T0000
|
|
arc: A7 Q7
|
|
arc: B0 V02N0301
|
|
arc: B2 H00R0100
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 W1_H02E0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 V02N0001
|
|
arc: D7 F0
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: M2 H02E0601
|
|
arc: M5 H00R0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEA.K0.INIT 1111111000000000
|
|
word: SLICEB.K0.INIT 0011000001010000
|
|
word: SLICED.K1.INIT 0000101100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C16:PLC2
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
|
|
.tile R12C17:PLC2
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
|
|
.tile R12C19:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R12C21:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: CE0 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: LSR0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V00T0100 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C22:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: C2 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F2 F5B_SLICE
|
|
arc: LSR0 E1_H02W0501
|
|
arc: M0 V00T0000
|
|
arc: M2 N1_V01N0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V00T0000 F2
|
|
word: SLICEB.K0.INIT 1111101011111100
|
|
word: SLICEB.K1.INIT 0000101000001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C23:PLC2
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0000
|
|
arc: B0 V01N0001
|
|
arc: B1 V01N0001
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0100
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K0.INIT 0000111000000100
|
|
word: SLICEA.K1.INIT 1111111011110100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C24:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A3 V02S0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 E1_H02W0501
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V00B0000
|
|
arc: B3 Q3
|
|
arc: B4 V02S0701
|
|
arc: B5 N1_V02S0501
|
|
arc: C0 H02W0601
|
|
arc: C1 S1_V02N0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 E1_H02W0601
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D3 H00R0000
|
|
arc: D4 V02S0601
|
|
arc: D5 V02S0401
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00T0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M3 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V02N0301 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 0000111000000010
|
|
word: SLICEA.K1.INIT 1111111011001110
|
|
word: SLICEC.K0.INIT 1100100000001000
|
|
word: SLICEB.K1.INIT 1000100010100000
|
|
word: SLICEC.K1.INIT 1100101000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C25:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A2 H02E0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 V01N0001
|
|
arc: B2 H02E0301
|
|
arc: B4 H02W0101
|
|
arc: B5 V00B0100
|
|
arc: C0 F4
|
|
arc: C2 H02W0601
|
|
arc: C4 H02W0601
|
|
arc: C5 H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 H02W0201
|
|
arc: D4 H00R0100
|
|
arc: D5 V02S0401
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0100 Q5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111111111110011
|
|
word: SLICEB.K0.INIT 1000101010000000
|
|
word: SLICEC.K0.INIT 1100101000000000
|
|
word: SLICEC.K1.INIT 1100101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C26:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 V02N0501
|
|
arc: A2 V01N0101
|
|
arc: A3 V02N0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 H02E0701
|
|
arc: A6 V02N0101
|
|
arc: A7 V02N0301
|
|
arc: B2 H02E0301
|
|
arc: B3 H00R0000
|
|
arc: B4 H02E0101
|
|
arc: B5 H02W0301
|
|
arc: B6 V00B0000
|
|
arc: B7 V00T0000
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: LSR1 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0101 F3
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C27:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A3 V02S0501
|
|
arc: A5 H02W0701
|
|
arc: A6 H02E0701
|
|
arc: B0 V00T0000
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 H00L0000
|
|
arc: B4 H00R0000
|
|
arc: B7 V02S0701
|
|
arc: CE1 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0001 F0
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 H02W0301
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C28:PLC2
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0203 V06N0203
|
|
arc: A0 V02S0501
|
|
arc: A1 V02N0701
|
|
arc: A6 E1_H02W0501
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 H02E0301
|
|
arc: B5 V02N0501
|
|
arc: B7 H02E0101
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S3_V06S0203 F4
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R12C29:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 S1_V02N0701
|
|
arc: A4 H02E0701
|
|
arc: A5 V00B0000
|
|
arc: C4 H02W0601
|
|
arc: C5 H02W0601
|
|
arc: C6 V02N0001
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V00B0000
|
|
arc: D5 H02W0201
|
|
arc: D6 S1_V02N0601
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0701 Q5
|
|
arc: S3_V06S0203 F4
|
|
arc: V00B0000 F6
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 0000010101010101
|
|
word: SLICEC.K0.INIT 0000000001011111
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R12C30:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A1 H02E0501
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 S1_V02N0501
|
|
arc: A5 F7
|
|
arc: A7 Q7
|
|
arc: B0 H02E0101
|
|
arc: B2 V02N0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 V02S0701
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C2 H00L0000
|
|
arc: C3 H02E0401
|
|
arc: C5 V02N0201
|
|
arc: C7 V00T0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 F0
|
|
arc: D3 H02W0001
|
|
arc: D4 H02E0001
|
|
arc: D5 H02W0201
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 Q2
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00T0100
|
|
arc: M6 E1_H02W0401
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V01S0100 Q6
|
|
word: SLICEC.K1.INIT 1111101110111011
|
|
word: SLICEB.K0.INIT 1110101011111111
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
word: SLICED.K1.INIT 1000110010000000
|
|
word: SLICEA.K0.INIT 0000001100001111
|
|
word: SLICEA.K1.INIT 0000010100001111
|
|
word: SLICEB.K1.INIT 1010001010000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C31:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F0
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0501 Q7
|
|
arc: V00T0100 Q3
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K0.INIT 0011000100100000
|
|
word: SLICEA.K1.INIT 1111110111101100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C32:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: B0 H02E0101
|
|
arc: C0 W1_H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M5 W1_H02E0001
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q2
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q5
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C33:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 E1_H01E0001
|
|
arc: B0 H01W0100
|
|
arc: B1 H01W0100
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: E1_H01E0001 Q1
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: V01S0100 Q6
|
|
word: SLICEA.K0.INIT 0000000011001010
|
|
word: SLICEA.K1.INIT 1111111111001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C34:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: A0 H02W0501
|
|
arc: A1 S1_V02N0701
|
|
arc: B0 H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: C0 H00R0100
|
|
arc: C1 H00L0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M5 V01S0000
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q7
|
|
arc: W3_H06W0203 Q7
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 0000000011011000
|
|
word: SLICEA.K1.INIT 1111111111100010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C35:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 S1_V02N0501
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 V02S0601
|
|
arc: C1 V02S0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q2
|
|
arc: V00B0100 Q5
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEA.K0.INIT 0000000011100100
|
|
word: SLICEA.K1.INIT 1111111111100100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C36:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02W0301
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V01S0100 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C37:PLC2
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
|
|
.tile R12C3:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
|
|
.tile R12C4:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02N0301
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R12C5:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: A0 V02N0701
|
|
arc: A2 H02E0501
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 N1_V01N0101
|
|
arc: A6 F5
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 V02N0101
|
|
arc: B4 H02W0101
|
|
arc: B5 F3
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 H02W0401
|
|
arc: C3 V02N0401
|
|
arc: C4 V01N0101
|
|
arc: C5 H01E0001
|
|
arc: C6 F4
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D2 V00B0100
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02S0601
|
|
arc: D5 F0
|
|
arc: D6 F2
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 Q3
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 W1_H02E0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q0
|
|
word: SLICED.K1.INIT 0000010100000011
|
|
word: SLICEB.K1.INIT 0000000010111111
|
|
word: SLICEA.K0.INIT 1101000000000000
|
|
word: SLICEB.K0.INIT 0000000010001100
|
|
word: SLICEC.K0.INIT 0000100000001100
|
|
word: SLICEC.K1.INIT 0000000000111111
|
|
word: SLICED.K0.INIT 1101110111010001
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R12C6:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: V00B0000 H02E0601
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 H00R0000
|
|
arc: A1 H00R0000
|
|
arc: A3 V02N0701
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C3 H02W0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D3 H02W0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0001 F0
|
|
arc: V00B0100 Q5
|
|
arc: W1_H02W0101 F3
|
|
word: SLICEB.K1.INIT 1010101010101000
|
|
word: SLICEA.K0.INIT 1100111110100000
|
|
word: SLICEA.K1.INIT 1100111110101111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C7:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A3 E1_H02W0701
|
|
arc: A5 V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B5 V02N0701
|
|
arc: C3 N1_V01N0001
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00L0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V02N0001
|
|
arc: D5 H01W0000
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H02W0001
|
|
arc: M3 H02W0201
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEB.K1.INIT 0101000101010101
|
|
word: SLICEC.K1.INIT 0011001100010011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C8:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: A0 E1_H02W0701
|
|
arc: A2 V00B0000
|
|
arc: A3 V00T0000
|
|
arc: A5 N1_V02S0301
|
|
arc: A6 V02N0101
|
|
arc: A7 H00R0000
|
|
arc: B4 H00L0000
|
|
arc: E1_H01E0101 F5
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R12C9:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0203 E1_H02W0401
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A7 Q7
|
|
arc: B7 S1_V02N0501
|
|
arc: C7 V02N0001
|
|
arc: CE1 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H02E0201 Q2
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
word: SLICED.K1.INIT 0010001100110011
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R13C10:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 V01N0101
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 F7
|
|
arc: A7 Q7
|
|
arc: B0 F3
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 Q3
|
|
arc: B4 V01S0000
|
|
arc: B5 H02E0301
|
|
arc: B6 H02E0101
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 H00L0000
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V02N0001
|
|
arc: C6 H02E0401
|
|
arc: C7 V02S0001
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 Q2
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 F2
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F6
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEB.K1.INIT 0000001100000101
|
|
word: SLICEC.K0.INIT 0000000011011111
|
|
word: SLICEA.K0.INIT 0010001000000010
|
|
word: SLICEB.K0.INIT 0000110000000100
|
|
word: SLICED.K1.INIT 1000000011000000
|
|
word: SLICEC.K1.INIT 1100111110001011
|
|
word: SLICED.K0.INIT 0011000011110000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R13C11:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 F7
|
|
arc: A7 Q7
|
|
arc: B0 E1_H02W0301
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 S1_V02N0401
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D7 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S3_V06S0003 F0
|
|
word: SLICED.K1.INIT 0010001100110011
|
|
word: SLICEA.K0.INIT 0010001000000010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R13C12:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: B1 Q1
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: V01S0100 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R13C13:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0203 V01N0001
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A3 V02N0501
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: C0 H00R0100
|
|
arc: C1 N1_V01N0001
|
|
arc: C3 V02N0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 S1_V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M3 H01W0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEB.K1.INIT 0000001100000101
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R13C14:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R13C15:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0103 V01N0101
|
|
arc: W3_H06W0303 V01N0101
|
|
|
|
.tile R13C17:PLC2
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R13C19:PLC2
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R13C20:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: A2 V00B0000
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 E1_H01W0000
|
|
arc: B2 F3
|
|
arc: B3 V01N0001
|
|
arc: B4 V00B0100
|
|
arc: B5 S1_V02N0501
|
|
arc: C2 V02N0601
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V02N0201
|
|
arc: D2 H00R0000
|
|
arc: D3 H02W0001
|
|
arc: D4 V02N0401
|
|
arc: D5 F2
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0303 F5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEC.K0.INIT 1001000000001001
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
word: SLICEC.K1.INIT 0011110000000000
|
|
word: SLICEB.K0.INIT 1000010000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R13C21:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
|
|
.tile R13C22:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: B0 H02W0301
|
|
arc: B1 H02W0301
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M5 V01S0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 0101010000000100
|
|
word: SLICEA.K1.INIT 1111111010101110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C23:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 H02E0501
|
|
arc: A1 H02E0501
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 H02E0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEA.K0.INIT 0000000010101100
|
|
word: SLICEA.K1.INIT 1111111110101100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C24:PLC2
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00R0000 H02W0401
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02E0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: A4 W1_H02E0701
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: B4 V02N0501
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 Q4
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 S1_V02N0601
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0401 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 F2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0000
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0601 Q4
|
|
arc: S1_V02S0001 Q0
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1111101011111111
|
|
word: SLICEB.K0.INIT 0010001000110000
|
|
word: SLICEB.K1.INIT 1110111011111100
|
|
word: SLICEC.K0.INIT 1110010000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C25:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A1 H00R0000
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: A5 E1_H01W0000
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 Q3
|
|
arc: B5 S1_V02N0701
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C5 E1_H02W0601
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00B0100
|
|
arc: D2 V01S0100
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 V00B0000
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M3 W1_H02E0201
|
|
arc: M5 H02W0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V02N0501 Q5
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEB.K0.INIT 0010001100100000
|
|
word: SLICEB.K1.INIT 1111111110101100
|
|
word: SLICEC.K1.INIT 0001010100111111
|
|
word: SLICEA.K1.INIT 0000011101110111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R13C26:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: A0 V02S0501
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V02N0501
|
|
arc: A4 V00T0100
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 H02E0701
|
|
arc: A7 H02E0501
|
|
arc: B2 V02S0301
|
|
arc: B3 H00R0000
|
|
arc: B4 V02N0701
|
|
arc: B5 H00L0000
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 V00T0000
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0701 F7
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0601 F4
|
|
arc: W1_H02W0701 F7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C27:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 S1_V02N0501
|
|
arc: A2 V02N0701
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V00B0000
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 V00T0100
|
|
arc: B0 H02W0301
|
|
arc: B1 V02S0301
|
|
arc: B2 H00L0000
|
|
arc: B3 V01N0001
|
|
arc: B4 H00R0000
|
|
arc: B5 V02S0701
|
|
arc: B6 V00B0100
|
|
arc: B7 N1_V02S0701
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: LSR0 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0701 Q5
|
|
arc: N3_V06N0003 F3
|
|
arc: S1_V02S0001 F2
|
|
arc: W1_H02W0201 F2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C28:PLC2
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 N1_V02S0501
|
|
arc: A1 H00R0000
|
|
arc: A6 E1_H02W0701
|
|
arc: B0 V02N0301
|
|
arc: B1 H02E0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 V02S0301
|
|
arc: B4 H02E0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B7 V00T0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0401 F4
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F5
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R13C29:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 V02N0701
|
|
arc: A4 F5
|
|
arc: A5 V02S0301
|
|
arc: A7 N1_V02S0101
|
|
arc: B4 H02E0101
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 S1_V02N0701
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 H02E0601
|
|
arc: C6 H02W0601
|
|
arc: C7 H02W0601
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H01W0000
|
|
arc: D5 V00B0000
|
|
arc: D6 V02S0601
|
|
arc: D7 H00R0100
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F6
|
|
arc: LSR0 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V01S0000 F0
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1110101011111111
|
|
word: SLICEC.K1.INIT 1000110010000000
|
|
word: SLICED.K0.INIT 0000001100110011
|
|
word: SLICED.K1.INIT 0000000001011111
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R13C2:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C30:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 H02W0201
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 V02N0501
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 F7
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 H00L0000
|
|
arc: B0 V02S0301
|
|
arc: B1 F3
|
|
arc: B2 V02S0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H02E0301
|
|
arc: B5 W1_H02E0301
|
|
arc: B7 V02N0501
|
|
arc: C0 H00L0100
|
|
arc: C2 W1_H02E0601
|
|
arc: C4 V00T0000
|
|
arc: C5 V00T0000
|
|
arc: C6 S1_V02N0201
|
|
arc: C7 V00B0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D2 V02N0001
|
|
arc: D3 H02E0001
|
|
arc: D4 N1_V02S0401
|
|
arc: D5 F0
|
|
arc: D6 E1_H02W0201
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F6
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 F2
|
|
arc: N3_V06N0003 Q3
|
|
arc: S1_V02S0301 Q3
|
|
arc: S3_V06S0303 Q5
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K0.INIT 1110101011111111
|
|
word: SLICEC.K1.INIT 1110101011111111
|
|
word: SLICED.K0.INIT 0101000000000000
|
|
word: SLICED.K1.INIT 1000110010000000
|
|
word: SLICEA.K1.INIT 0001000100110011
|
|
word: SLICEA.K0.INIT 0000001100001111
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 1000101010000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R13C31:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 F7
|
|
arc: A5 H02E0501
|
|
arc: B1 V00T0000
|
|
arc: B5 V02N0501
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C5 V00T0100
|
|
arc: C7 H02W0601
|
|
arc: CE2 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V00B0100
|
|
arc: D5 H00R0100
|
|
arc: D7 V02N0601
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 0000010101010101
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 1100100000001000
|
|
word: SLICEA.K1.INIT 0000000000111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R13C32:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0000 H02W0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0701
|
|
arc: A4 H02E0501
|
|
arc: A5 F7
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 V02S0101
|
|
arc: B1 V02S0101
|
|
arc: B4 V02S0701
|
|
arc: B5 H02E0301
|
|
arc: B6 V02N0701
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 F6
|
|
arc: C3 F6
|
|
arc: C4 H02E0401
|
|
arc: C5 N1_V02S0001
|
|
arc: C7 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 V02S0201
|
|
arc: D3 V00B0100
|
|
arc: D4 F2
|
|
arc: D5 H02E0201
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0101 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0000
|
|
arc: M6 E1_H02W0401
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0501 Q7
|
|
arc: S1_V02S0101 Q1
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEB.K0.INIT 0000010100001111
|
|
word: SLICEB.K1.INIT 0000010100001111
|
|
word: SLICEC.K0.INIT 1110101011111111
|
|
word: SLICEC.K1.INIT 1110111110101111
|
|
word: SLICEA.K0.INIT 0000000010111000
|
|
word: SLICEA.K1.INIT 1111111110111000
|
|
word: SLICED.K0.INIT 1100110000000000
|
|
word: SLICED.K1.INIT 1000100011000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R13C33:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 H02W0101
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A2 V02S0501
|
|
arc: A4 H02W0501
|
|
arc: A5 H02W0501
|
|
arc: A6 V02N0301
|
|
arc: A7 V02N0301
|
|
arc: B0 H02E0101
|
|
arc: B1 V02S0101
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0701
|
|
arc: C0 V02N0401
|
|
arc: C1 H00L0000
|
|
arc: C2 V02N0401
|
|
arc: C4 V02S0201
|
|
arc: C5 V02S0201
|
|
arc: C6 V00B0100
|
|
arc: C7 V00B0100
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 H02E0201
|
|
arc: D2 V02N0001
|
|
arc: D4 H02W0001
|
|
arc: D5 H02W0001
|
|
arc: D6 V00B0000
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 F1
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F7
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0601 F4
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K1.INIT 0000001100000000
|
|
word: SLICEB.K0.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEC.K0.INIT 0000000010101100
|
|
word: SLICEC.K1.INIT 1111111110101100
|
|
word: SLICED.K1.INIT 0000000010100000
|
|
word: SLICED.K0.INIT 0000101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C34:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02E0601
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00B0000 H02W0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 H02W0501
|
|
arc: A1 H00L0000
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 H01W0100
|
|
arc: B1 V02S0101
|
|
arc: B2 H02E0301
|
|
arc: B5 H02E0101
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 V01S0100
|
|
arc: D2 S1_V02N0201
|
|
arc: D5 H02E0001
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F5
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F5
|
|
arc: V00B0100 Q5
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0501 Q7
|
|
word: SLICEA.K0.INIT 0000000011011000
|
|
word: SLICEA.K1.INIT 1111111010111010
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEC.K1.INIT 1000100000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C35:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 V02N0501
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 V02N0501
|
|
arc: B0 H02W0301
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 V01N0001
|
|
arc: B3 Q3
|
|
arc: C0 H00R0100
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H00R0100
|
|
arc: C3 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: E1_H01E0001 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H01E0001
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H01W0100
|
|
arc: M4 H02W0401
|
|
arc: M5 H00L0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0001 F2
|
|
word: SLICEA.K0.INIT 0000000011001010
|
|
word: SLICEA.K1.INIT 1111111111100100
|
|
word: SLICEB.K0.INIT 0000000010101100
|
|
word: SLICEB.K1.INIT 1111111111011000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C36:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M4 H02W0401
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0201 Q0
|
|
arc: W1_H02W0301 Q3
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C37:PLC2
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 H01E0101
|
|
|
|
.tile R13C38:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
|
|
.tile R13C3:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
|
|
.tile R13C41:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R13C44:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C47:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: F1 F1_SLICE
|
|
arc: N3_V06N0103 F1
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R13C4:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0100 V02N0501
|
|
arc: B0 H01W0100
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 S1_V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V01S0100
|
|
arc: E1_H02E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0100 Q5
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEA.K1.INIT 1111111100001111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R13C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R13C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R13C5:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: A5 Q5
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B5 V01S0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01N0001
|
|
arc: C5 S1_V02N0201
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0001
|
|
arc: D5 E1_H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M5 H00L0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 F5
|
|
arc: V01S0000 Q7
|
|
word: SLICEC.K1.INIT 0101001100000000
|
|
word: SLICEA.K0.INIT 1111110010001000
|
|
word: SLICEA.K1.INIT 1110111011110011
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R13C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R13C6:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 F7
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 H01E0001
|
|
arc: A4 V02S0301
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 H02W0301
|
|
arc: B1 F3
|
|
arc: B2 H01W0100
|
|
arc: B4 H02W0301
|
|
arc: B7 V00B0100
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 H00L0000
|
|
arc: C4 Q4
|
|
arc: C7 F4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 F2
|
|
arc: D4 S1_V02N0601
|
|
arc: D7 S1_V02N0401
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 0101010100010101
|
|
word: SLICEB.K0.INIT 1000101000000000
|
|
word: SLICEC.K0.INIT 0000001100010001
|
|
word: SLICED.K1.INIT 0000100000001010
|
|
word: SLICEB.K1.INIT 0000000001011111
|
|
word: SLICEA.K1.INIT 1111101000110011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R13C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R13C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R13C7:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A0 H00L0000
|
|
arc: A3 V00B0000
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 F5
|
|
arc: B0 S1_V02N0101
|
|
arc: B3 Q3
|
|
arc: B5 V01S0000
|
|
arc: B6 F3
|
|
arc: B7 V00B0100
|
|
arc: C0 N1_V01N0001
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 Q6
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0000
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0401 F6
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q5
|
|
word: SLICEB.K1.INIT 0010001000001010
|
|
word: SLICED.K0.INIT 0010000000100010
|
|
word: SLICEA.K0.INIT 0001110100000000
|
|
word: SLICEC.K1.INIT 1111111000000000
|
|
word: SLICED.K1.INIT 0000000010001010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R13C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R13C8:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 V02S0701
|
|
arc: A1 H02E0701
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 H01W0100
|
|
arc: B7 H02E0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C7 H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 N1_V01S0000
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q5
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M5 H02W0001
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0101 Q1
|
|
arc: S3_V06S0103 Q1
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0501 F7
|
|
word: SLICED.K1.INIT 0000101100001111
|
|
word: SLICEA.K0.INIT 1010001010100000
|
|
word: SLICEA.K1.INIT 1111001000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C9:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 H02E0501
|
|
arc: A1 H02E0501
|
|
arc: A2 S1_V02N0501
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 V00T0000
|
|
arc: B0 V02S0101
|
|
arc: B1 H02E0301
|
|
arc: B2 H00L0000
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 H01E0101
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C2 N1_V01N0001
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 F4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: D2 S1_V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 S1_V02N0601
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 H02W0301
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00T0000 F2
|
|
word: SLICEC.K0.INIT 1111111000000000
|
|
word: SLICEB.K0.INIT 0000101000100010
|
|
word: SLICEC.K1.INIT 0100000001010000
|
|
word: SLICEA.K0.INIT 1100110001000000
|
|
word: SLICEA.K1.INIT 1100110001000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C10:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0303 H01E0101
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 V02S0701
|
|
arc: B0 V00B0000
|
|
arc: C0 W1_H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q2
|
|
word: SLICEA.K0.INIT 0000000011001110
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C11:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: C1 H00L0000
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 H02W0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R14C12:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0303 V06N0303
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A0 V02N0701
|
|
arc: B0 H01W0100
|
|
arc: B3 Q3
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V01S0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 V00B0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 F2
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEA.K0.INIT 1011111110101111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1111110000001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R14C13:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 V01N0101
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 W1_H02E0701
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: B3 H02E0301
|
|
arc: B4 H02E0301
|
|
arc: B5 V02N0701
|
|
arc: C2 N1_V01S0100
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 S1_V02N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 V01S0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V00T0100
|
|
arc: D4 E1_H02W0201
|
|
arc: D6 E1_H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0203 F4
|
|
arc: N3_V06N0303 F6
|
|
arc: S3_V06S0303 F6
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K0.INIT 1000000010100000
|
|
word: SLICEA.K0.INIT 1111111110101010
|
|
word: SLICEA.K1.INIT 1110111001000100
|
|
word: SLICEB.K1.INIT 1110111011001100
|
|
word: SLICEC.K1.INIT 1110101011101010
|
|
word: SLICED.K0.INIT 1111101011110000
|
|
word: SLICEC.K0.INIT 1111110011001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R14C14:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A5 V02S0301
|
|
arc: A6 V02S0301
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 H02W0301
|
|
arc: B2 H02E0101
|
|
arc: B4 H02E0101
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 V02N0601
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 H02W0401
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 H02W0401
|
|
arc: C7 N1_V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 H02W0001
|
|
arc: D4 H02W0001
|
|
arc: D5 H02W0001
|
|
arc: D6 H02W0001
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F7
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0401 F4
|
|
arc: N3_V06N0103 F1
|
|
arc: N3_V06N0203 F4
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICED.K1.INIT 1111111111000000
|
|
word: SLICED.K0.INIT 1111111110100000
|
|
word: SLICEC.K1.INIT 1111111110100000
|
|
word: SLICEC.K0.INIT 1111111111000000
|
|
word: SLICEB.K0.INIT 1111111111000000
|
|
word: SLICEA.K1.INIT 1111110011001100
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R14C15:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 H01E0101
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A1 V02N0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 S1_V02N0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 V02S0701
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 H00L0100
|
|
arc: C3 H00R0100
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V00T0100
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 V02S0001
|
|
arc: D4 H00R0100
|
|
arc: D5 H00R0100
|
|
arc: D6 H02W0001
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0401 F6
|
|
arc: N3_V06N0203 F7
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0101 F3
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K1.INIT 1111111111000000
|
|
word: SLICEC.K0.INIT 1111111111000000
|
|
word: SLICEB.K1.INIT 1111101011110000
|
|
word: SLICED.K0.INIT 1111111110100000
|
|
word: SLICED.K1.INIT 1111101011110000
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1011101110001000
|
|
word: SLICEB.K0.INIT 1111110000001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R14C16:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B3 E1_H01W0100
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 S1_V02N0601
|
|
arc: C3 H00L0000
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 H02E0001
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 F3
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0301 Q1
|
|
arc: S3_V06S0003 Q0
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K1.INIT 1111110011110000
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R14C17:PLC2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A7 H02W0701
|
|
arc: C1 V02N0601
|
|
arc: D1 H02W0201
|
|
arc: D7 V02N0601
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F1
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0301 F1
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K1.INIT 0101010100000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R14C18:PLC2
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
|
|
.tile R14C19:PLC2
|
|
arc: W1_H02W0101 V02N0101
|
|
|
|
.tile R14C20:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A2 V02N0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A7 V02N0301
|
|
arc: B0 V02S0301
|
|
arc: B4 V02N0701
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02S0501
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0601 F4
|
|
arc: V01S0000 F5
|
|
word: SLICED.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R14C21:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R14C22:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0501 V06N0303
|
|
|
|
.tile R14C23:PLC2
|
|
arc: E3_H06E0203 V06N0203
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02W0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 E1_H02W0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1111111111001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C24:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 E1_H02W0701
|
|
arc: B0 H02W0101
|
|
arc: B3 H00L0000
|
|
arc: B4 V01S0000
|
|
arc: C0 N1_V02S0601
|
|
arc: C3 V02N0601
|
|
arc: C4 V00T0000
|
|
arc: CE0 H00L0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 W1_H02E0201
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 1111111111110011
|
|
word: SLICEB.K1.INIT 1101000010000000
|
|
word: SLICEC.K0.INIT 1100000010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R14C25:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A0 F5
|
|
arc: A1 N1_V02S0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 H02E0701
|
|
arc: B1 V02N0101
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: C0 F4
|
|
arc: C1 H02W0601
|
|
arc: C4 V02N0201
|
|
arc: C5 V00T0000
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 H00R0000
|
|
arc: D4 V02S0601
|
|
arc: D5 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W1_H02W0101 F1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111111110101111
|
|
word: SLICEA.K1.INIT 0001010100111111
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 1101000010000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R14C26:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 F7
|
|
arc: A2 H00L0100
|
|
arc: A6 H02W0501
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 V00B0000
|
|
arc: B2 S1_V02N0101
|
|
arc: B6 V02S0701
|
|
arc: B7 V02N0501
|
|
arc: C2 V02S0601
|
|
arc: C6 V02N0201
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 V02N0201
|
|
arc: D6 V02S0601
|
|
arc: D7 N1_V02S0401
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICED.K1.INIT 1100100001000000
|
|
word: SLICEB.K0.INIT 0001010100111111
|
|
word: SLICEA.K0.INIT 1110111011111111
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R14C27:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 V02S0501
|
|
arc: A4 H02E0501
|
|
arc: A5 Q5
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 V00T0100
|
|
arc: B4 V00B0100
|
|
arc: C0 H02W0401
|
|
arc: C4 N1_V02S0201
|
|
arc: C5 H02E0601
|
|
arc: C6 H02W0401
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 V02N0401
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 H02W0601
|
|
arc: M1 V01S0100
|
|
arc: M3 H00L0000
|
|
arc: M5 V01S0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0501 F5
|
|
arc: S1_V02S0601 F4
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q6
|
|
word: SLICEC.K1.INIT 1010101011110000
|
|
word: SLICED.K0.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICED.K1.INIT 1010101011110000
|
|
word: SLICEC.K0.INIT 1100010010000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R14C28:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A0 V02S0701
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 H02E0701
|
|
arc: A4 V02N0101
|
|
arc: A5 V00T0000
|
|
arc: A6 V02S0101
|
|
arc: A7 V02S0301
|
|
arc: B2 H00R0000
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 H02E0301
|
|
arc: B6 V02N0701
|
|
arc: B7 S1_V02N0501
|
|
arc: CE1 V02N0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F6
|
|
arc: LSR0 V00T0100
|
|
arc: M3 H00L0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V01S0000 Q5
|
|
arc: W1_H02W0301 F3
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0103 F2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C29:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A1 S1_V02N0701
|
|
arc: A2 V00T0000
|
|
arc: A3 N1_V02S0501
|
|
arc: A6 E1_H02W0701
|
|
arc: B0 V00B0000
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 N1_V02S0701
|
|
arc: B7 E1_H02W0101
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0001 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F7
|
|
arc: N1_V01N0001 F5
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 F3
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R14C2:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
|
|
.tile R14C30:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: A0 V02N0501
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 V02N0101
|
|
arc: A6 H02E0701
|
|
arc: B1 S1_V02N0301
|
|
arc: B7 V00T0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0001 F0
|
|
arc: V01S0000 F4
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R14C31:PLC2
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 H02E0701
|
|
arc: A4 F7
|
|
arc: A7 H02W0701
|
|
arc: B4 N1_V01S0000
|
|
arc: B7 V02S0501
|
|
arc: C4 V02N0201
|
|
arc: C7 H02W0601
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 W1_H02E0201
|
|
arc: D7 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V01S0000 Q4
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1111101110111011
|
|
word: SLICED.K1.INIT 1011000010000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C32:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0203 V01N0001
|
|
arc: A0 N1_V02S0501
|
|
arc: A2 F5
|
|
arc: A5 W1_H02E0501
|
|
arc: A7 V02S0101
|
|
arc: B0 F3
|
|
arc: B1 F3
|
|
arc: B2 E1_H02W0101
|
|
arc: B5 V02N0701
|
|
arc: B7 H02E0301
|
|
arc: C1 H02W0601
|
|
arc: C2 H00L0000
|
|
arc: C3 N1_V01S0100
|
|
arc: C5 V02S0001
|
|
arc: C7 V02S0001
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 F0
|
|
arc: D3 V00T0100
|
|
arc: D5 H00R0100
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0101 Q2
|
|
word: SLICEC.K1.INIT 1100101000000000
|
|
word: SLICEA.K1.INIT 0000001100110011
|
|
word: SLICEB.K0.INIT 1110101011111111
|
|
word: SLICEA.K0.INIT 0001000100110011
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 1010110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R14C33:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 F7
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 E1_H02W0501
|
|
arc: B3 V02S0101
|
|
arc: B4 H02W0301
|
|
arc: B7 N1_V02S0701
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V02S0001
|
|
arc: C7 H02E0601
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H02E0001
|
|
arc: D2 V00B0100
|
|
arc: D4 F2
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0000
|
|
arc: M0 H02E0601
|
|
arc: M2 H02E0601
|
|
arc: M3 E1_H02W0201
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0303 Q6
|
|
arc: V01S0100 F0
|
|
arc: W3_H06W0003 Q3
|
|
word: SLICEB.K1.INIT 0001010100010101
|
|
word: SLICEB.K0.INIT 0000010101010101
|
|
word: SLICEC.K0.INIT 1110101011111111
|
|
word: SLICEA.K1.INIT 0000010101010101
|
|
word: SLICEA.K0.INIT 0000010101010101
|
|
word: SLICEC.K1.INIT 1010101000000000
|
|
word: SLICED.K0.INIT 1010101000000000
|
|
word: SLICED.K1.INIT 1000101010000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C34:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A5 V02N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 Q1
|
|
arc: B5 S1_V02N0501
|
|
arc: C0 H00L0100
|
|
arc: C1 H02E0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V02N0001
|
|
arc: D5 H02E0001
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F5
|
|
arc: V01S0100 Q2
|
|
word: SLICEA.K0.INIT 0011000100100000
|
|
word: SLICEA.K1.INIT 1111111111011000
|
|
word: SLICEC.K1.INIT 0000000001000100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C35:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 V02S0501
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 E1_H01E0001
|
|
arc: B1 H02E0301
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 N1_V02S0101
|
|
arc: C0 W1_H02E0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 H00R0000
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0401 Q4
|
|
arc: V01S0000 F2
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
word: SLICEB.K0.INIT 0000000011100010
|
|
word: SLICEB.K1.INIT 1111111111100010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C36:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 H02E0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0103 Q1
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C37:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: CE1 V02N0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: LSR0 V00B0100
|
|
arc: M2 H02E0601
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00T0000 Q2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C38:PLC2
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
|
|
.tile R14C3:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: S1_V02S0101 H06W0103
|
|
|
|
.tile R14C42:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R14C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R14C48:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R14C49:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R14C4:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02S0701
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q4
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R14C5:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C61:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R14C67:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R14C6:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 H02W0701
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A2 V00T0000
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 F7
|
|
arc: A7 F5
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 V02N0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V01S0000
|
|
arc: B7 F3
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 V02N0401
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0201
|
|
arc: C6 V00B0100
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 H02W0001
|
|
arc: D5 H02W0001
|
|
arc: D6 V01N0001
|
|
arc: D7 F0
|
|
arc: E1_H01E0001 F4
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F2
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEC.K0.INIT 0000000000110101
|
|
word: SLICEC.K1.INIT 0010001100110011
|
|
word: SLICEB.K1.INIT 0101000000010000
|
|
word: SLICED.K1.INIT 0001000100110011
|
|
word: SLICEB.K0.INIT 0000000010001100
|
|
word: SLICED.K0.INIT 1111010111000101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R14C73:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R14C79:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R14C7:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0203 E1_H02W0401
|
|
arc: A7 Q7
|
|
arc: B7 V00T0000
|
|
arc: C7 V02N0201
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F7
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00T0000 Q0
|
|
word: SLICED.K1.INIT 0000000000110101
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R14C85:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
|
|
.tile R14C86:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R14C8:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 V02S0701
|
|
arc: A3 H02E0501
|
|
arc: A4 H02W0701
|
|
arc: B0 V00T0000
|
|
arc: B3 Q3
|
|
arc: B4 H02E0301
|
|
arc: C0 V02S0601
|
|
arc: C3 V02N0401
|
|
arc: C4 Q4
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D3 V02N0201
|
|
arc: D4 H02E0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M3 H00R0000
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0301 F3
|
|
arc: W1_H02W0601 F4
|
|
word: SLICEC.K0.INIT 1010001010101010
|
|
word: SLICEB.K1.INIT 1101000011110000
|
|
word: SLICEA.K0.INIT 1100110000001000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C9:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A1 V02N0501
|
|
arc: A2 V01N0101
|
|
arc: B1 Q1
|
|
arc: B2 V02N0101
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 H00L0000
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 F2
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 Q6
|
|
word: SLICEB.K0.INIT 1010101010101000
|
|
word: SLICEA.K1.INIT 0000101000100010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R15C10:PLC2
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 H02E0701
|
|
arc: A7 Q7
|
|
arc: B0 E1_H02W0101
|
|
arc: B2 E1_H02W0301
|
|
arc: B7 V01S0000
|
|
arc: C0 E1_H02W0601
|
|
arc: C2 E1_H02W0601
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 Q2
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEA.K0.INIT 0000000100110001
|
|
word: SLICEB.K0.INIT 0101010100010101
|
|
word: SLICED.K1.INIT 0010001100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R15C11:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A2 W1_H02E0701
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 S1_V02N0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 N1_V01S0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1000101000000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R15C12:PLC2
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H02E0501
|
|
arc: A3 H02E0701
|
|
arc: A6 F7
|
|
arc: A7 Q7
|
|
arc: B0 H00R0100
|
|
arc: B3 Q3
|
|
arc: B6 F3
|
|
arc: B7 V01S0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 V00T0000
|
|
arc: C6 H02E0601
|
|
arc: C7 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D3 V02S0001
|
|
arc: D4 H02W0001
|
|
arc: D6 F0
|
|
arc: D7 H02E0201
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 F4
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H01E0001
|
|
arc: M3 H00L0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V02N0401 F4
|
|
arc: N3_V06N0203 F4
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F6
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0401 F4
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 0000000011110000
|
|
word: SLICEA.K0.INIT 1011101011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0100010100000000
|
|
word: SLICED.K1.INIT 1011000000000000
|
|
word: SLICED.K0.INIT 1110000011101111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R15C13:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A2 E1_H01E0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 V01S0100
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0201 Q2
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0001 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEB.K0.INIT 0101010110101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C14:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: A0 H02W0501
|
|
arc: A1 V02N0701
|
|
arc: A2 H02W0501
|
|
arc: B0 S1_V02N0101
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 V02N0501
|
|
arc: C0 V02N0401
|
|
arc: C1 H02W0601
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 H02W0601
|
|
arc: C4 H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00T0100
|
|
arc: D2 H00R0000
|
|
arc: D3 V00B0100
|
|
arc: D4 S1_V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0601 Q4
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 1101100011011000
|
|
word: SLICEA.K1.INIT 1111101000001010
|
|
word: SLICEC.K0.INIT 1111110000001100
|
|
word: SLICEB.K0.INIT 1111010110100000
|
|
word: SLICEB.K1.INIT 1100111111000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R15C15:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A3 V00B0000
|
|
arc: A6 H02E0701
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 N1_V02S0301
|
|
arc: B2 H02E0101
|
|
arc: B4 H02E0301
|
|
arc: B5 H00R0000
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICED.K1.INIT 1001100110011010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R15C16:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: A0 W1_H02E0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A6 H02E0701
|
|
arc: A7 H00R0000
|
|
arc: B1 V00T0000
|
|
arc: B2 H02E0301
|
|
arc: B3 H00L0000
|
|
arc: B5 S1_V02N0701
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICED.K1.INIT 1001100110011010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R15C17:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 H00L0000
|
|
arc: A3 V00B0000
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 S1_V02N0301
|
|
arc: B2 H02E0301
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 V00T0000
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1001100110011010
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011010
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R15C18:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 W1_H02E0501
|
|
arc: B1 S1_V02N0301
|
|
arc: F2 F2_SLICE
|
|
arc: S3_V06S0103 F2
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R15C19:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C20:PLC2
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R15C21:PLC2
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0303 H06E0303
|
|
|
|
.tile R15C22:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R15C23:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: B0 V00B0000
|
|
arc: C0 V02N0601
|
|
arc: CE0 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 H02E0301
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C24:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: A0 V02S0701
|
|
arc: A1 H00R0000
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 H02W0301
|
|
arc: B1 H02W0301
|
|
arc: C0 H02E0401
|
|
arc: C1 N1_V01N0001
|
|
arc: C7 V00B0100
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 V01S0100
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 F7
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 H00L0100
|
|
arc: M5 V01S0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q5
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K1.INIT 1111000010101010
|
|
word: SLICEA.K0.INIT 0010001000110000
|
|
word: SLICEA.K1.INIT 1111110111101100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C25:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0303 V06N0303
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: B2 H02E0101
|
|
arc: C2 V02N0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 Q2
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00T0100 Q1
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C26:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: B0 V00T0000
|
|
arc: C0 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C27:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A0 H00L0000
|
|
arc: A3 V01N0101
|
|
arc: A6 E1_H01W0000
|
|
arc: B0 V00T0000
|
|
arc: B3 W1_H02E0101
|
|
arc: C0 E1_H02W0401
|
|
arc: C6 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: D3 V02N0201
|
|
arc: D6 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0601 F6
|
|
word: SLICEA.K0.INIT 1110111111001111
|
|
word: SLICED.K0.INIT 1010101011110000
|
|
word: SLICEB.K1.INIT 1010101011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C28:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: B6 V00B0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C6 S1_V02N0001
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0001
|
|
arc: D6 V02N0401
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F6
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
word: SLICED.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C29:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A5 H02W0701
|
|
arc: B0 V00T0000
|
|
arc: C0 V02N0401
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D5 S1_V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0701 F5
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEC.K1.INIT 1010101000000000
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C2:PLC2
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile R15C30:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 F5
|
|
arc: A1 H02W0501
|
|
arc: A2 F7
|
|
arc: A3 F7
|
|
arc: A5 H02E0501
|
|
arc: B0 H02W0101
|
|
arc: B3 N1_V02S0301
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 V02S0501
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 H02W0601
|
|
arc: C2 W1_H02E0401
|
|
arc: C5 V02S0001
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D1 V02N0201
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 H00R0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F1
|
|
arc: W1_H02W0101 F1
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEB.K1.INIT 0001000101010101
|
|
word: SLICEB.K0.INIT 0000010101010101
|
|
word: SLICEA.K0.INIT 1110101011111111
|
|
word: SLICEA.K1.INIT 1010000000000000
|
|
word: SLICED.K1.INIT 1100000011000000
|
|
word: SLICEC.K1.INIT 1010000010001000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C31:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: B0 V02N0301
|
|
arc: B3 V01N0001
|
|
arc: C0 H02E0401
|
|
arc: C3 H02W0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 V00B0100
|
|
arc: D3 V01S0100
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W1_H02W0001 F2
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C32:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 V02S0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A5 W1_H02E0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: C1 V02S0601
|
|
arc: C2 H02W0401
|
|
arc: C3 H02W0401
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D5 S1_V02N0601
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 F2
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q3
|
|
word: SLICEA.K1.INIT 0000010101010101
|
|
word: SLICEA.K0.INIT 0001000101010101
|
|
word: SLICEB.K0.INIT 0000000010101100
|
|
word: SLICEB.K1.INIT 1111111110101100
|
|
word: SLICEC.K1.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R15C33:PLC2
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A0 V02S0501
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 V02S0701
|
|
arc: B0 H02W0301
|
|
arc: B1 H02W0301
|
|
arc: B2 V02S0101
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 H02E0601
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 F2
|
|
arc: D2 Q2
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S3_V06S0103 Q1
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEA.K0.INIT 1110101011111111
|
|
word: SLICEA.K1.INIT 1111111110001111
|
|
word: SLICEB.K0.INIT 1010100000001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C34:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00B0100 H02E0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: A0 V02S0701
|
|
arc: A1 V02S0701
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H02E0601
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
arc: V00T0100 Q1
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICEA.K0.INIT 0000101100001000
|
|
word: SLICEA.K1.INIT 1111101111111000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C35:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: B1 E1_H02W0301
|
|
arc: C1 S1_V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 E1_H02W0201
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C36:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 H02E0101
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 V02N0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 W1_H02E0001
|
|
arc: D2 S1_V02N0201
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 H02E0301
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K0.INIT 0000000010101100
|
|
word: SLICEA.K1.INIT 1111111110101100
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C37:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: B0 N1_V02S0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0011001100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C38:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0001 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C3:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0100 H02E0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: CE0 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0701 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C41:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R15C47:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R15C4:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R15C5:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: A0 F5
|
|
arc: A2 H02W0501
|
|
arc: A3 V00T0000
|
|
arc: A5 Q5
|
|
arc: A6 V00T0100
|
|
arc: A7 H00R0000
|
|
arc: B0 H01W0100
|
|
arc: B2 H02W0301
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 H02W0101
|
|
arc: C0 H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 H00L0000
|
|
arc: C5 H02W0601
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D2 Q2
|
|
arc: D3 H01E0101
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 V01N0001
|
|
arc: D7 E1_H02W0201
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00T0000 F2
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 F7
|
|
word: SLICED.K1.INIT 1011000011110000
|
|
word: SLICEC.K1.INIT 0000010000000111
|
|
word: SLICEB.K0.INIT 0000111100000111
|
|
word: SLICEA.K0.INIT 0100010100000000
|
|
word: SLICEB.K1.INIT 0000010100001111
|
|
word: SLICED.K0.INIT 1111010111000101
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R15C6:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B5 V00B0100
|
|
arc: B7 V01S0000
|
|
arc: C5 E1_H02W0601
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 H02E0001
|
|
arc: D7 H02W0201
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 Q2
|
|
word: SLICED.K1.INIT 0000010100000011
|
|
word: SLICEC.K1.INIT 0010000000110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R15C7:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02W0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A3 H02E0701
|
|
arc: A4 E1_H02W0701
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: B4 H02E0101
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H02W0401
|
|
arc: C3 F4
|
|
arc: C4 Q4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D3 H02W0001
|
|
arc: D4 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEC.K0.INIT 0101000101010101
|
|
word: SLICEB.K1.INIT 0000000011010000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R15C8:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A0 H00L0000
|
|
arc: A6 H02W0701
|
|
arc: B0 H02E0101
|
|
arc: B6 H02E0101
|
|
arc: C0 W1_H02E0601
|
|
arc: C6 Q6
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D6 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0000
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEA.K0.INIT 0000000100001101
|
|
word: SLICED.K0.INIT 0101000101010101
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R15C9:PLC2
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A2 S1_V02N0701
|
|
arc: A4 F5
|
|
arc: A5 N1_V01S0100
|
|
arc: A7 S1_V02N0101
|
|
arc: B1 V00B0000
|
|
arc: B2 V01N0001
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 E1_H02W0301
|
|
arc: B7 V00B0100
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0100
|
|
arc: C2 S1_V02N0601
|
|
arc: C4 Q4
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 F4
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 F0
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 E1_H02W0001
|
|
arc: D7 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 H02E0601
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: S3_V06S0203 F7
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1011101011111111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111000011100000
|
|
word: SLICEC.K0.INIT 0010000000100010
|
|
word: SLICED.K1.INIT 1010100011111101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R16C10:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R16C11:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R16C12:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: C2 H00R0100
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0001
|
|
arc: D3 V02S0201
|
|
arc: F2 F5B_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0201 F2
|
|
word: SLICEB.K0.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R16C13:PLC2
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A2 V01N0101
|
|
arc: A4 S1_V02N0101
|
|
arc: B0 H02W0101
|
|
arc: B3 V01N0001
|
|
arc: B5 V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0701
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R16C14:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A0 V01N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R16C15:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: A3 V01N0101
|
|
arc: B0 V00B0000
|
|
arc: B1 V02N0301
|
|
arc: B2 V01N0001
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R16C16:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 H02W0101
|
|
arc: A0 V01N0101
|
|
arc: A2 V00B0000
|
|
arc: A4 V00T0000
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 H00R0000
|
|
arc: B1 V02N0301
|
|
arc: B3 V01N0001
|
|
arc: B7 V02N0501
|
|
arc: CE0 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R16C17:PLC2
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A3 V00B0000
|
|
arc: A4 V00B0000
|
|
arc: B2 H02E0301
|
|
arc: C2 H02W0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 W1_H02E0601
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V00B0100
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0301 Q3
|
|
arc: S3_V06S0003 F0
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 1111101001010000
|
|
word: SLICEC.K0.INIT 1111101001010000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R16C18:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0100 V02N0501
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 S1_V02N0701
|
|
arc: B0 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: C2 H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 1110111000100010
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R16C19:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
|
|
.tile R16C20:PLC2
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
|
|
.tile R16C21:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 F7
|
|
arc: A2 V00T0000
|
|
arc: A7 Q7
|
|
arc: B1 Q1
|
|
arc: B2 V02S0101
|
|
arc: B7 W1_H02E0101
|
|
arc: C1 V02S0601
|
|
arc: C2 V02S0401
|
|
arc: C7 V00B0100
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 F2
|
|
arc: D2 V02S0001
|
|
arc: D7 W1_H02E0001
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 W1_H02E0601
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F1
|
|
word: SLICED.K1.INIT 0000000001000111
|
|
word: SLICEB.K0.INIT 0000101100001111
|
|
word: SLICEA.K1.INIT 0100010100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R16C22:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V02S0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C23:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: A2 V02S0501
|
|
arc: B1 E1_H02W0101
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H01W0000
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 V02N0201
|
|
arc: D2 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M0 H02E0601
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1010111110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C24:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0000 V02N0601
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: A0 E1_H02W0701
|
|
arc: B0 V02N0301
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1110111000100010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C25:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A3 S1_V02N0501
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: B3 S1_V02N0301
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 E1_H01W0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0001
|
|
arc: D2 V00T0100
|
|
arc: D3 V02N0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q1
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F2
|
|
arc: LSR1 H02W0301
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0100 Q3
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1010101011001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R16C26:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A3 H01E0001
|
|
arc: A4 V00B0000
|
|
arc: A6 V02N0301
|
|
arc: B0 E1_H02W0101
|
|
arc: B5 H02E0301
|
|
arc: B7 H01E0101
|
|
arc: E1_H01E0001 F3
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R16C27:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A0 V01N0101
|
|
arc: A1 V02N0701
|
|
arc: A6 V02N0301
|
|
arc: B2 V01N0001
|
|
arc: B3 N1_V02S0301
|
|
arc: B4 H00L0000
|
|
arc: B5 H02W0301
|
|
arc: B7 V00B0000
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 F7
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H00R0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0601 F4
|
|
arc: S3_V06S0003 F3
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C28:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: A4 H02W0501
|
|
arc: B0 V02S0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B5 H02W0101
|
|
arc: B6 V00T0000
|
|
arc: B7 H02W0301
|
|
arc: E1_H01E0001 F5
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 F4
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R16C29:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 H02E0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 S1_V02N0101
|
|
arc: C4 H02W0401
|
|
arc: C6 Q6
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02E0001
|
|
arc: D5 V02S0401
|
|
arc: D6 V02S0401
|
|
arc: D7 H00R0100
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F7
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 N1_V01N0101
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0601 F6
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1111010110100000
|
|
word: SLICED.K1.INIT 1111101001010000
|
|
word: SLICEC.K0.INIT 1111010110100000
|
|
word: SLICEC.K1.INIT 1111111100000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C2:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0601
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0100 V02S0701
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0203 Q4
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R16C30:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 H02W0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: A2 H02E0501
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 S1_V02N0101
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 V02N0301
|
|
arc: B1 W1_H02E0301
|
|
arc: B3 V01N0001
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0000
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0100
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 N1_V02S0601
|
|
arc: C4 V00B0100
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 V00B0100
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00B0100
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 E1_H02W0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F4
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M5 V01S0000
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0401 F6
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEC.K0.INIT 1010111110100000
|
|
word: SLICED.K1.INIT 1010110010101100
|
|
word: SLICEC.K1.INIT 1110111001000100
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C31:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 E1_H01E0001
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 H00L0000
|
|
arc: B2 V02N0301
|
|
arc: B3 V01N0001
|
|
arc: B7 H02E0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C2 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C4 H02W0601
|
|
arc: C5 V02N0201
|
|
arc: C6 V01N0101
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 H02E0001
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 V00B0100
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 V02N0601
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M4 V00T0000
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F0
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 0000000001010000
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 1100111111000000
|
|
word: SLICED.K0.INIT 1111000010101010
|
|
word: SLICED.K1.INIT 1100110011110000
|
|
word: SLICEC.K1.INIT 1010101011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C32:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A0 E1_H02W0501
|
|
arc: A5 Q5
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 V02N0301
|
|
arc: C0 W1_H02E0401
|
|
arc: C1 H00L0100
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 V02N0401
|
|
arc: C5 V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 S1_V02N0001
|
|
arc: D5 H02W0001
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M5 V01S0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0701 F5
|
|
arc: W1_H02W0701 Q7
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
word: SLICEB.K0.INIT 1111000011001100
|
|
word: SLICEC.K1.INIT 1010101011110000
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C33:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: W3_H06W0303 V01N0101
|
|
arc: A1 W1_H02E0701
|
|
arc: A3 H02E0501
|
|
arc: B2 H01W0100
|
|
arc: C1 H02E0401
|
|
arc: C2 V02N0601
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 V00B0100
|
|
arc: D2 V00T0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0001 F0
|
|
arc: V01S0000 Q5
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 1010101010101010
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111000010101010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C34:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 V02N0701
|
|
arc: A3 V01N0101
|
|
arc: A5 V02N0301
|
|
arc: A6 V02N0301
|
|
arc: A7 V02N0301
|
|
arc: B1 W1_H02E0101
|
|
arc: B3 V02N0101
|
|
arc: B5 V02N0501
|
|
arc: B6 V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C0 H02E0601
|
|
arc: C5 V02N0001
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0001
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D2 V01S0100
|
|
arc: D3 V02N0201
|
|
arc: D5 H02E0201
|
|
arc: D6 H02E0201
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: LSR0 V00B0100
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F7
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0601 F6
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K0.INIT 0010000000000000
|
|
word: SLICEC.K1.INIT 0100000000000000
|
|
word: SLICEA.K0.INIT 1111000011110000
|
|
word: SLICEA.K1.INIT 1100110010101010
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1100110010101010
|
|
word: SLICED.K1.INIT 0001000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R16C35:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A1 H02W0501
|
|
arc: A2 E1_H01E0001
|
|
arc: B0 V02N0101
|
|
arc: C0 H02E0401
|
|
arc: C1 H00L0100
|
|
arc: C2 V02S0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00T0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0001 Q2
|
|
arc: V01S0000 Q7
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1111000010101010
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C36:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W3_H06W0203 V06N0203
|
|
arc: A0 H02E0501
|
|
arc: B1 W1_H02E0101
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 H00L0100
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q1
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C37:PLC2
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 V01N0001
|
|
arc: B2 S1_V02N0301
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C2 W1_H02E0601
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 S1_V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 F2
|
|
arc: LSR0 V00T0000
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0201 F2
|
|
arc: S1_V02S0001 F0
|
|
arc: S3_V06S0103 Q2
|
|
word: SLICEB.K0.INIT 0011000000000000
|
|
word: SLICEA.K0.INIT 1000000010100000
|
|
word: SLICEA.K1.INIT 0110000010100000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R16C38:PLC2
|
|
arc: W1_H02W0201 V06S0103
|
|
|
|
.tile R16C3:PLC2
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: B0 H01W0100
|
|
arc: C0 H00L0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: E1_H01E0001 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S3_V06S0303 Q5
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C4:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: B0 V02N0101
|
|
arc: B1 E1_H02W0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V02N0001
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0000 Q1
|
|
word: SLICEA.K0.INIT 1110111111101110
|
|
word: SLICEA.K1.INIT 0000000011001110
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R16C5:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: A0 H00L0000
|
|
arc: A2 V02S0701
|
|
arc: A4 V02S0101
|
|
arc: B0 V02S0101
|
|
arc: B2 H01W0100
|
|
arc: B4 H00R0000
|
|
arc: C0 H00R0100
|
|
arc: C2 F4
|
|
arc: C4 V02S0001
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 F0
|
|
arc: D4 V02S0401
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: H00R0100 Q7
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F2
|
|
word: SLICEA.K0.INIT 0000000000011101
|
|
word: SLICEC.K0.INIT 1101111100000000
|
|
word: SLICEB.K0.INIT 0000000011010000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R16C6:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: C0 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D3 W1_H02E0001
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M1 W1_H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0103 Q1
|
|
arc: V00T0000 F0
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0101 F3
|
|
word: SLICEA.K0.INIT 1111111100001111
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R16C7:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0100
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R16C8:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A0 H01E0001
|
|
arc: A3 V02S0501
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: B0 V02N0301
|
|
arc: B3 Q3
|
|
arc: B5 H02E0301
|
|
arc: B6 F3
|
|
arc: C0 N1_V01S0100
|
|
arc: C3 N1_V01S0100
|
|
arc: C5 V02S0001
|
|
arc: C6 Q6
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D3 H02E0201
|
|
arc: D5 H01W0000
|
|
arc: D6 V02N0401
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 F6
|
|
word: SLICEB.K1.INIT 1111000011100000
|
|
word: SLICEC.K1.INIT 0100000001001100
|
|
word: SLICED.K0.INIT 0100000001000100
|
|
word: SLICEA.K0.INIT 1111010011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R16C9:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A3 V02S0501
|
|
arc: B3 Q3
|
|
arc: C3 H00L0000
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V02S0001
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0000
|
|
arc: M3 H02W0201
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V01S0000 F3
|
|
word: SLICEB.K1.INIT 0010001000001010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R17C10:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: A2 H02E0501
|
|
arc: A3 V00T0000
|
|
arc: A4 N1_V02S0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 H01W0100
|
|
arc: B4 V00B0100
|
|
arc: C2 H00L0000
|
|
arc: C3 F4
|
|
arc: C4 Q4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 N1_V02S0201
|
|
arc: D3 F2
|
|
arc: D4 H01W0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEC.K0.INIT 0000000100100011
|
|
word: SLICEB.K0.INIT 0101000101010101
|
|
word: SLICEB.K1.INIT 0000110100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R17C11:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: D1 N1_V02S0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M3 H00L0000
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R17C12:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: C6 N1_V02S0001
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E3_H06E0303 F6
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F6
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V02N0401 F6
|
|
arc: N3_V06N0303 F6
|
|
arc: S1_V02S0601 F6
|
|
arc: S3_V06S0303 F6
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0401 F6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICED.K0.INIT 0000000011110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R17C13:PLC2
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0303 V06S0303
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 V01N0101
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H02E0701
|
|
arc: A7 Q7
|
|
arc: B0 H02W0301
|
|
arc: B2 V01N0001
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0701
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 H02E0401
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F5
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 F4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 F4
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C14:PLC2
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0303 V06S0303
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V01N0101
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0100
|
|
arc: A5 V00T0100
|
|
arc: A6 V00T0100
|
|
arc: A7 V00T0100
|
|
arc: B0 V01N0001
|
|
arc: B1 V02N0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F6
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0501 F7
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C15:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0303 V06S0303
|
|
arc: A0 V01N0101
|
|
arc: A1 H00L0100
|
|
arc: A2 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 V02N0101
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0201 F0
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R17C16:PLC2
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: A0 V01N0101
|
|
arc: A1 H00L0000
|
|
arc: A2 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V00T0100
|
|
arc: A6 V00T0100
|
|
arc: A7 V00T0100
|
|
arc: B0 H01W0100
|
|
arc: B1 V02N0101
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0301
|
|
arc: B4 H02E0301
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q3
|
|
arc: LSR1 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0101 Q3
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C17:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: A0 H00L0000
|
|
arc: A1 V01N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 W1_H02E0301
|
|
arc: B4 H02W0101
|
|
arc: B5 H02W0101
|
|
arc: B6 V02N0701
|
|
arc: C4 V02N0201
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 N1_V02S0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 W1_H02E0201
|
|
arc: D5 V02N0601
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0301 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
word: SLICED.K0.INIT 1111110000001100
|
|
word: SLICEC.K0.INIT 1111110000110000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R17C18:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: A2 V02N0501
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 N1_V02S0101
|
|
arc: B7 W1_H02E0301
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 V02N0601
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 W1_H02E0201
|
|
arc: D2 V00B0100
|
|
arc: D7 S1_V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K1.INIT 1110101101111101
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
word: SLICEB.K0.INIT 1111101000001010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R17C19:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
|
|
.tile R17C20:PLC2
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 H02E0501
|
|
arc: A3 S1_V02N0501
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: B0 V00B0000
|
|
arc: B3 Q3
|
|
arc: B5 F3
|
|
arc: B6 W1_H02E0301
|
|
arc: C0 W1_H02E0601
|
|
arc: C3 H00L0100
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 H02W0401
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D3 N1_V02S0001
|
|
arc: D5 V02N0401
|
|
arc: D6 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 1011101011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1010101010101000
|
|
word: SLICEC.K1.INIT 0000000010001100
|
|
word: SLICED.K0.INIT 1100100011111011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R17C21:PLC2
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: B0 H02W0101
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: B6 H02W0101
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C6 V02N0201
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D6 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F1
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEB.K1.INIT 0000000000000011
|
|
word: SLICEA.K1.INIT 0000000000001100
|
|
word: SLICEB.K0.INIT 0000001100000000
|
|
word: SLICED.K0.INIT 1100000000000000
|
|
word: SLICEA.K0.INIT 0000110000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R17C22:PLC2
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A5 S1_V02N0301
|
|
arc: C5 V00B0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 E1_H02W0201
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0303 F5
|
|
arc: V00B0100 Q5
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEC.K1.INIT 1111000010101010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C23:PLC2
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: B4 H02W0101
|
|
arc: C4 S1_V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V00B0000
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 F4
|
|
arc: LSR0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N3_V06N0203 F4
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q1
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 1111110000110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C24:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 H02E0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A2 S1_V02N0501
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 V02N0101
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0201
|
|
arc: D2 Q2
|
|
arc: E1_H01E0001 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 F2
|
|
arc: LSR0 V00B0000
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V00T0100 Q1
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEB.K0.INIT 1110111000100010
|
|
word: SLICEA.K0.INIT 1111000011110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C25:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: A0 V02N0701
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 S1_V02N0101
|
|
arc: B0 E1_H02W0101
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 H02E0601
|
|
arc: C4 Q4
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V00B0100
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 H02E0201
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 H02W0601
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F4
|
|
arc: V00T0000 F0
|
|
arc: W1_H02W0001 F2
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
word: SLICEA.K0.INIT 1100110010101010
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1111000011110000
|
|
word: SLICEB.K1.INIT 1010101011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C26:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 V02S0501
|
|
arc: A5 Q5
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B6 E1_H02W0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 V02S0601
|
|
arc: C3 N1_V01S0100
|
|
arc: C5 V02N0201
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V00B0100
|
|
arc: D5 H02W0201
|
|
arc: D6 H02E0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEC.K1.INIT 1010101011110000
|
|
word: SLICED.K0.INIT 1111000011001100
|
|
word: SLICED.K1.INIT 1111000011110000
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
word: SLICEB.K1.INIT 1111110000110000
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C27:PLC2
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A5 V02S0101
|
|
arc: A7 Q7
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 H00L0000
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V02N0701
|
|
arc: C0 V02S0601
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V00T0100
|
|
arc: C5 V00T0100
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V02S0001
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 V02N0401
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 H00R0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0101 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0000 Q5
|
|
arc: W1_H02W0701 F7
|
|
word: SLICED.K1.INIT 1010101011001100
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICEC.K0.INIT 1111110000001100
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICEB.K1.INIT 1111110000110000
|
|
word: SLICEC.K1.INIT 1111101000001010
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C28:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A2 H02W0701
|
|
arc: A4 V00T0000
|
|
arc: A7 N1_V01N0101
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 H01W0100
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0401
|
|
arc: C4 Q4
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 V02N0001
|
|
arc: D2 V01S0100
|
|
arc: D3 V00B0100
|
|
arc: D4 E1_H02W0001
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0401 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 H00R0100
|
|
arc: M4 H02W0401
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q6
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEB.K0.INIT 1111101001010000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICED.K1.INIT 1010111110100000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C29:PLC2
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 H01E0001
|
|
arc: B0 H02E0101
|
|
arc: B2 V02N0301
|
|
arc: B4 H01E0101
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0000
|
|
arc: B7 H02E0301
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 F6
|
|
arc: E3_H06E0103 Q1
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0100 F7
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C2:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V00B0000 Q4
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R17C30:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02S0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A1 H02W0701
|
|
arc: A2 V00T0000
|
|
arc: A3 E1_H02W0501
|
|
arc: A4 H02W0501
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B5 V02N0501
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F2
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: LSR1 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 F1
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F4
|
|
arc: W1_H02W0301 F3
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C31:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A1 S1_V02N0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 V02N0101
|
|
arc: A5 E1_H02W0501
|
|
arc: B0 E1_H02W0101
|
|
arc: B2 E1_H02W0301
|
|
arc: B6 V02N0501
|
|
arc: B7 V00B0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F0
|
|
arc: V01S0000 F3
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R17C32:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0203 V06S0203
|
|
arc: B0 V00T0000
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 H02E0301
|
|
arc: B6 H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C4 V02N0201
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 V00T0100
|
|
arc: C7 H02E0401
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H00L0100
|
|
arc: D5 V02N0401
|
|
arc: D6 V01N0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M3 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0203 F4
|
|
arc: W1_H02W0401 F4
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1111110000110000
|
|
word: SLICED.K0.INIT 1111001111000000
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 1111001111000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C33:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A2 E1_H01E0001
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0101
|
|
arc: A7 Q7
|
|
arc: B0 V01N0001
|
|
arc: B5 V01S0000
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 W1_H02E0601
|
|
arc: C2 W1_H02E0601
|
|
arc: C4 V00T0100
|
|
arc: C5 H02W0401
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02E0201
|
|
arc: D2 V00B0100
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D6 V02N0401
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M5 H02W0001
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F5
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q5
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K1.INIT 1101100011011000
|
|
word: SLICEC.K0.INIT 1111010110100000
|
|
word: SLICEB.K0.INIT 1010111110100000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 1010111110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C34:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A0 V02N0501
|
|
arc: A4 E1_H02W0701
|
|
arc: A6 V00T0100
|
|
arc: A7 Q7
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 V02N0301
|
|
arc: B7 V02N0701
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 V02N0401
|
|
arc: C4 V00B0100
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V01S0100
|
|
arc: D4 H02E0001
|
|
arc: D6 V02N0601
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F6
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M2 V00B0000
|
|
arc: M3 H02W0201
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q1
|
|
arc: V00T0100 Q3
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0001 F2
|
|
word: SLICED.K0.INIT 1010111110100000
|
|
word: SLICEB.K0.INIT 1111110000001100
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
word: SLICEA.K0.INIT 1110111000100010
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICED.K1.INIT 1010101011001100
|
|
word: SLICEC.K0.INIT 1010101011110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C35:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0701
|
|
arc: A7 Q7
|
|
arc: C1 H00L0000
|
|
arc: C2 H00R0100
|
|
arc: C3 V02N0401
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 V02N0201
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0101 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEB.K0.INIT 1111010110100000
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 1010101011110000
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1010101011110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R17C36:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: B1 V02N0101
|
|
arc: C1 H02E0401
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H02E0201
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0201 F0
|
|
arc: S3_V06S0003 Q3
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET SET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R17C37:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: A0 H02E0701
|
|
arc: A2 V02N0501
|
|
arc: B2 H01W0100
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 H02E0601
|
|
arc: C2 S1_V02N0401
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00T0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q3
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 0110000011000000
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
word: SLICEA.K1.INIT 1111000011110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R17C38:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
|
|
.tile R17C39:PLC2
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
|
|
.tile R17C3:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: A0 H00L0000
|
|
arc: A3 F5
|
|
arc: A5 Q5
|
|
arc: B0 V02N0301
|
|
arc: B5 V02S0701
|
|
arc: C0 N1_V01N0001
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D3 F0
|
|
arc: D5 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 1000110000000000
|
|
word: SLICEC.K1.INIT 0000000010111111
|
|
word: SLICEB.K1.INIT 0000000001011111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R17C41:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R17C47:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R17C4:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00B0100 H02W0501
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0000 F0
|
|
arc: M0 V00B0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R17C5:PLC2
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 S1_V02N0701
|
|
arc: C6 H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F0
|
|
arc: LSR1 V00B0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: S3_V06S0003 F0
|
|
arc: V00B0000 F6
|
|
word: SLICED.K0.INIT 1111111100001111
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R17C6:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 E1_H01E0001
|
|
arc: A5 Q5
|
|
arc: B0 H02W0301
|
|
arc: B2 H00L0000
|
|
arc: B5 H02E0301
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 N1_V02S0401
|
|
arc: C5 E1_H01E0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 N1_V02S0001
|
|
arc: D5 F0
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02W0601
|
|
arc: M2 H02W0601
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
word: SLICEA.K0.INIT 1010101010101000
|
|
word: SLICEB.K0.INIT 0101001100000000
|
|
word: SLICEC.K1.INIT 0000101100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R17C7:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A0 H02E0501
|
|
arc: A4 N1_V02S0101
|
|
arc: B0 H01W0100
|
|
arc: B4 V01S0000
|
|
arc: C0 E1_H02W0401
|
|
arc: C4 N1_V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D4 V00B0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0401 F4
|
|
arc: S3_V06S0003 F0
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q7
|
|
word: SLICEA.K0.INIT 1111001011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000100001011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R17C8:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A2 E1_H01E0001
|
|
arc: B1 Q1
|
|
arc: B2 S1_V02N0101
|
|
arc: C0 H00R0100
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 E1_H02W0401
|
|
arc: CE0 H00L0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D2 F0
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: S1_V02S0201 F2
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1000110000000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R17C9:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 N1_V02S0501
|
|
arc: A3 V00T0000
|
|
arc: A4 S1_V02N0301
|
|
arc: B0 N1_V02S0301
|
|
arc: B3 Q3
|
|
arc: B4 H02W0301
|
|
arc: C0 S1_V02N0601
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 E1_H01E0101
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V02S0601
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M3 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: S3_V06S0203 F4
|
|
arc: V00T0000 F0
|
|
word: SLICEA.K0.INIT 1111000011100000
|
|
word: SLICEB.K1.INIT 0000000010001010
|
|
word: SLICEC.K0.INIT 1010100011111101
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R18C10:PLC2
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V06S0003
|
|
|
|
.tile R18C11:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 V02N0501
|
|
arc: A2 V02N0501
|
|
arc: B0 H01W0100
|
|
arc: B2 H00L0000
|
|
arc: C0 H02W0601
|
|
arc: C2 H02W0401
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00T0000 F2
|
|
word: SLICEB.K0.INIT 1000101000000000
|
|
word: SLICEA.K0.INIT 1011101011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R18C12:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0203 V06S0203
|
|
arc: A3 V00T0000
|
|
arc: A5 F7
|
|
arc: A7 Q7
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: B5 S1_V02N0701
|
|
arc: B7 V02N0501
|
|
arc: C1 N1_V01N0001
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 H01E0001
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H02E0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D3 H02W0001
|
|
arc: D5 S1_V02N0601
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0301 F3
|
|
arc: S3_V06S0303 F5
|
|
word: SLICEB.K1.INIT 0010011100000000
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICED.K1.INIT 0010000000110000
|
|
word: SLICEC.K1.INIT 1100111110001011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R18C13:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 V01N0101
|
|
arc: A4 H02W0501
|
|
arc: A5 V00B0000
|
|
arc: A6 H00L0000
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V02S0301
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 V02N0501
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0701
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E3_H06E0203 F4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F5
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F7
|
|
arc: N3_V06N0203 Q7
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0501 Q7
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R18C14:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0100 H02W0701
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 H00L0100
|
|
arc: A3 H02E0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02S0101
|
|
arc: A6 H02E0501
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V00B0000
|
|
arc: B1 V02N0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 V02N0101
|
|
arc: B4 V02S0701
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02N0701
|
|
arc: B7 V02N0501
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R18C15:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A0 H02E0701
|
|
arc: A1 H00L0100
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V00B0000
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V02S0301
|
|
arc: A6 H00R0000
|
|
arc: A7 N1_V02S0101
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 V02S0701
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 S1_V02N0701
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0601 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: N3_V06N0203 Q7
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q7
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R18C16:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0701
|
|
arc: A3 V00T0000
|
|
arc: A4 V02N0301
|
|
arc: A5 V02N0301
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 V02S0101
|
|
arc: B0 H02W0301
|
|
arc: B1 N1_V02S0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 H00L0000
|
|
arc: B6 V02N0701
|
|
arc: B7 V02N0501
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0701 F5
|
|
arc: V01S0100 F4
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R18C17:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: H00L0000 H02W0201
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 H00L0000
|
|
arc: A1 E1_H02W0701
|
|
arc: A4 H02W0701
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: C4 V02S0001
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 W1_H02E0001
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F1
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 1111010110100000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R18C18:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 S1_V02N0501
|
|
arc: A2 S1_V02N0501
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 H02E0401
|
|
arc: C2 V02S0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 H01E0101
|
|
arc: D2 H02E0201
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEA.K0.INIT 1111101001010000
|
|
word: SLICEA.K1.INIT 1111010110100000
|
|
word: SLICEB.K0.INIT 1111010110100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R18C19:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A2 V00T0000
|
|
arc: B2 H00R0000
|
|
arc: C2 V02S0401
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0001
|
|
arc: E1_H01E0001 F2
|
|
arc: F2 F2_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00T0000 Q2
|
|
word: SLICEB.K0.INIT 0011010100000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R18C20:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A4 S1_V02N0101
|
|
arc: A6 V02S0101
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B3 V02S0301
|
|
arc: B5 H02W0301
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 H02W0401
|
|
arc: C3 H02W0401
|
|
arc: C4 V02N0201
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 S1_V02N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02S0401
|
|
arc: D5 H02W0001
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F5
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEC.K1.INIT 1111111111000000
|
|
word: SLICEC.K0.INIT 1111101011110000
|
|
word: SLICEB.K0.INIT 1111110011110000
|
|
word: SLICEB.K1.INIT 1111110011110000
|
|
word: SLICED.K0.INIT 1111111110100000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R18C21:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: A5 V02S0101
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02S0301
|
|
arc: B4 H02W0101
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V00B0000
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 F4
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 E1_H02W0601
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0001
|
|
arc: D2 H02W0001
|
|
arc: D3 V02N0001
|
|
arc: D4 H02E0201
|
|
arc: D5 V01N0001
|
|
arc: D6 V01N0001
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0301 F3
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F5
|
|
arc: V00B0000 F4
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K0.INIT 0000000011000000
|
|
word: SLICED.K1.INIT 1111111111000000
|
|
word: SLICEB.K1.INIT 1111111111000000
|
|
word: SLICEA.K1.INIT 1111110011001100
|
|
word: SLICEB.K0.INIT 1111110011001100
|
|
word: SLICED.K0.INIT 1111111111000000
|
|
word: SLICEA.K0.INIT 1111110011001100
|
|
word: SLICEC.K1.INIT 1111111110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R18C22:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C23:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02E0301
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0601 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C24:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: B0 N1_V02S0101
|
|
arc: B2 N1_V02S0101
|
|
arc: C0 H02W0601
|
|
arc: C2 E1_H01W0000
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D2 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S3_V06S0103 Q2
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C25:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 V02N0701
|
|
arc: A5 S1_V02N0101
|
|
arc: B1 S1_V02N0301
|
|
arc: B3 E1_H02W0101
|
|
arc: C0 H02E0401
|
|
arc: C3 H02E0601
|
|
arc: C5 V00B0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D2 V01S0100
|
|
arc: D3 V02N0201
|
|
arc: D5 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0000 F2
|
|
arc: LSR0 H02W0301
|
|
arc: M0 H02W0601
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0303 F5
|
|
arc: V00B0100 Q7
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K1.INIT 1111000010101010
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEA.K1.INIT 1100110011001100
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C26:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: B1 E1_H02W0301
|
|
arc: C1 H02W0601
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R18C27:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A1 H02W0501
|
|
arc: A3 S1_V02N0501
|
|
arc: A6 V02S0101
|
|
arc: B5 H02W0101
|
|
arc: C1 E1_H02W0401
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 V02N0201
|
|
arc: C6 V02S0001
|
|
arc: C7 V02N0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0201
|
|
arc: D2 V00T0100
|
|
arc: D3 W1_H02E0201
|
|
arc: D5 H00R0100
|
|
arc: D6 E1_H02W0001
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 F0
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H02E0201
|
|
arc: M5 V01S0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N3_V06N0103 F2
|
|
arc: N3_V06N0303 F5
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F6
|
|
word: SLICEC.K1.INIT 1111110000110000
|
|
word: SLICED.K0.INIT 1111101000001010
|
|
word: SLICED.K1.INIT 1111000011110000
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111101001010000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1010101011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C28:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 V02S0701
|
|
arc: A2 V02N0701
|
|
arc: A6 V02S0301
|
|
arc: B0 H02W0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B3 V02N0101
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 H00L0100
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V02N0201
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D6 E1_H02W0001
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 F3
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 1011101110001000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICED.K0.INIT 1010111110100000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C29:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 V02N0701
|
|
arc: A1 V01N0101
|
|
arc: A2 H02W0501
|
|
arc: A3 V02S0501
|
|
arc: A4 E1_H02W0501
|
|
arc: A6 V02N0301
|
|
arc: A7 V02S0101
|
|
arc: B1 V02N0101
|
|
arc: B5 H02W0101
|
|
arc: C0 V02S0601
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 V00B0100
|
|
arc: C5 V02N0001
|
|
arc: C6 V02S0001
|
|
arc: C7 V00B0100
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 H02W0201
|
|
arc: D6 H00R0100
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H02E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q6
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0501 Q7
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEC.K1.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1010101011001100
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEC.K0.INIT 1111101000001010
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
word: SLICEB.K1.INIT 1010101011110000
|
|
word: SLICED.K0.INIT 1111010110100000
|
|
word: SLICED.K1.INIT 1010111110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C2:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00T0000 V02N0401
|
|
arc: A0 E1_H01E0001
|
|
arc: A3 V02S0501
|
|
arc: A4 V00B0000
|
|
arc: B0 H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 H02E0101
|
|
arc: C0 H02E0401
|
|
arc: C3 F4
|
|
arc: C4 S1_V02N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D3 F0
|
|
arc: D4 H02W0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: M0 V00T0000
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q4
|
|
word: SLICEA.K0.INIT 0011000001010000
|
|
word: SLICEC.K0.INIT 1111000011100000
|
|
word: SLICEB.K1.INIT 0000000011010000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R18C30:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 V02S0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A2 V02N0501
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 V02S0101
|
|
arc: A5 V02S0301
|
|
arc: B0 V00T0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V02S0501
|
|
arc: B6 H02E0101
|
|
arc: B7 V00B0000
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F5
|
|
arc: E1_H01E0101 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F3
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M2 E1_H02W0601
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F4
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0501 F7
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C31:PLC2
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A0 S1_V02N0701
|
|
arc: A3 V00T0000
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 H02W0701
|
|
arc: B1 V00B0000
|
|
arc: B2 V02N0101
|
|
arc: B4 H00R0000
|
|
arc: B7 S1_V02N0501
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F4
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0001 F2
|
|
arc: W1_H02W0701 F7
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C32:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A1 S1_V02N0701
|
|
arc: A6 H00L0000
|
|
arc: B0 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 H02W0101
|
|
arc: B4 V02N0501
|
|
arc: B5 H02W0301
|
|
arc: B7 V00B0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F5
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F3
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 F6
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0201 F0
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C33:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A7 Q7
|
|
arc: B0 E1_H02W0101
|
|
arc: B4 V00B0100
|
|
arc: B6 V01S0000
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 H02E0401
|
|
arc: C7 H02E0401
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V02N0601
|
|
arc: D6 H02W0001
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F7
|
|
arc: LSR0 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 F6
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0201 Q2
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100111111000000
|
|
word: SLICEC.K1.INIT 1111000011110000
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 1010111110100000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C34:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 H02W0001
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: A1 H01E0001
|
|
arc: A2 H02E0701
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0301
|
|
arc: B5 V01S0000
|
|
arc: C0 H02E0401
|
|
arc: C5 E1_H02W0601
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V02S0001
|
|
arc: D2 W1_H02E0201
|
|
arc: D4 H02E0001
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0401 Q6
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K0.INIT 1110111000100010
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1110111000100010
|
|
word: SLICEC.K0.INIT 1111111100000000
|
|
word: SLICEC.K1.INIT 1111000011001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C35:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0701
|
|
arc: A4 N1_V01N0101
|
|
arc: B1 H02E0301
|
|
arc: B3 H02W0101
|
|
arc: C1 H02W0401
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 H02E0401
|
|
arc: C4 H02E0401
|
|
arc: CE1 H00L0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 V02N0201
|
|
arc: D2 V02S0201
|
|
arc: D4 E1_H01W0100
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0401 Q6
|
|
arc: W1_H02W0301 F3
|
|
arc: W1_H02W0601 Q6
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K0.INIT 1111101001010000
|
|
word: SLICEB.K1.INIT 1100101011001010
|
|
word: SLICEC.K0.INIT 1111101000001010
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C36:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A1 V01N0101
|
|
arc: A5 Q5
|
|
arc: B0 V00T0000
|
|
arc: B3 E1_H02W0101
|
|
arc: B7 V01S0000
|
|
arc: C0 H02E0401
|
|
arc: C3 H02W0401
|
|
arc: C5 V02N0001
|
|
arc: C7 V01N0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D3 V00B0100
|
|
arc: D5 V02N0401
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 H02W0601
|
|
arc: M2 N1_V01N0001
|
|
arc: M3 H00L0000
|
|
arc: M5 H02W0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S3_V06S0003 F3
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0101 Q3
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F5
|
|
word: SLICED.K1.INIT 1111110000110000
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1010101010101010
|
|
word: SLICEC.K1.INIT 1010101011110000
|
|
word: SLICEB.K1.INIT 0011000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C37:PLC2
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A2 V00T0000
|
|
arc: B0 H02E0301
|
|
arc: B2 V02S0101
|
|
arc: C0 V02N0601
|
|
arc: C2 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: D0 V00B0100
|
|
arc: D1 H02E0001
|
|
arc: D2 V02S0001
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 V00T0100
|
|
arc: S3_V06S0103 F2
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1111000001110000
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R18C38:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H01E0001
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 H01E0101
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 0010001010001000
|
|
word: SLICEA.K1.INIT 0011001100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C39:PLC2
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: C0 H00L0000
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C3:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 H02E0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 V02N0501
|
|
arc: A3 F5
|
|
arc: A5 Q5
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 F3
|
|
arc: B3 Q3
|
|
arc: B5 H00R0000
|
|
arc: C0 H02W0601
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 N1_V01N0001
|
|
arc: C5 S1_V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 H01E0101
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 H02W0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: M0 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M5 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F0
|
|
arc: S3_V06S0103 F1
|
|
word: SLICEC.K1.INIT 0000000001010011
|
|
word: SLICEA.K0.INIT 0000000010111111
|
|
word: SLICEB.K1.INIT 0100000001010000
|
|
word: SLICEA.K1.INIT 1010111110001101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R18C4:PLC2
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: CE0 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q6
|
|
arc: V01S0100 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C5:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: S1_V02S0001 Q2
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 F0
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R18C6:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: H00L0100 H02W0101
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: LSR1 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0100 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C7:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 E1_H02W0501
|
|
arc: A2 E1_H01E0001
|
|
arc: A4 F7
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 Q7
|
|
arc: B0 V02S0101
|
|
arc: B2 V02S0301
|
|
arc: B4 V02S0501
|
|
arc: B6 V00T0000
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 V02S0601
|
|
arc: C2 E1_H01W0000
|
|
arc: C4 Q4
|
|
arc: C6 H02E0401
|
|
arc: C7 V02S0201
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 V02S0201
|
|
arc: D4 F2
|
|
arc: D6 V02S0401
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F6
|
|
arc: V00T0000 F0
|
|
word: SLICEA.K0.INIT 0101010100010101
|
|
word: SLICED.K1.INIT 1100110011001000
|
|
word: SLICEB.K0.INIT 0100010000001100
|
|
word: SLICEC.K0.INIT 0000000010100010
|
|
word: SLICED.K0.INIT 0000000010001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R18C8:PLC2
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q6
|
|
arc: LSR0 W1_H02E0301
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R18C9:PLC2
|
|
arc: E3_H06E0203 V06N0203
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W3_H06W0003 V06N0003
|
|
arc: B1 Q1
|
|
arc: C0 V02S0601
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V02S0001
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R19C10:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W3_H06W0003 V06N0003
|
|
arc: B0 V02N0301
|
|
arc: C0 S1_V02N0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R19C11:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00B0100 H02W0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: A7 Q7
|
|
arc: B1 Q1
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 V02N0501
|
|
arc: B7 V00T0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0100
|
|
arc: C5 V02S0201
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 N1_V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 N1_V02S0601
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 H02W0401
|
|
arc: M5 H02E0001
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0201 F0
|
|
arc: V00T0000 Q2
|
|
word: SLICEC.K1.INIT 1111111000000000
|
|
word: SLICED.K1.INIT 0011010100000000
|
|
word: SLICED.K0.INIT 0000100000001010
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R19C12:PLC2
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A0 H02E0501
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: C0 F6
|
|
arc: C6 V02S0201
|
|
arc: C7 V02S0201
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D6 H01W0000
|
|
arc: D7 H00L0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H01E0001
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0201 F0
|
|
word: SLICED.K0.INIT 1111111111110000
|
|
word: SLICED.K1.INIT 1111101000001010
|
|
word: SLICEA.K0.INIT 1010111111101111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R19C13:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A0 H02E0701
|
|
arc: A2 V02S0501
|
|
arc: A3 H02E0701
|
|
arc: A4 N1_V02S0101
|
|
arc: C0 N1_V02S0401
|
|
arc: C2 H00R0100
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V00B0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 V00B0100
|
|
arc: D3 V00T0100
|
|
arc: D4 H00L0100
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q3
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
word: SLICEB.K1.INIT 1111101001010000
|
|
word: SLICEA.K0.INIT 1111010110100000
|
|
word: SLICEC.K0.INIT 1010111110100000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R19C14:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 W1_H02E0501
|
|
arc: A2 V01N0101
|
|
arc: A4 H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B2 H02E0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 V02S0401
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 H02W0401
|
|
arc: C4 V02S0201
|
|
arc: C5 V00T0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 V02S0201
|
|
arc: D3 H02W0201
|
|
arc: D4 H02E0001
|
|
arc: D5 H00R0100
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 Q3
|
|
arc: V00B0000 F4
|
|
arc: V01S0100 Q5
|
|
word: SLICEB.K0.INIT 0000001100010001
|
|
word: SLICEC.K0.INIT 0000000011011111
|
|
word: SLICEA.K0.INIT 0000000011000100
|
|
word: SLICEC.K1.INIT 1111110000110000
|
|
word: SLICEB.K1.INIT 1111110000110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R19C15:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: A2 F5
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 V01N0001
|
|
arc: B1 Q1
|
|
arc: B5 S1_V02N0701
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 H00L0000
|
|
arc: C2 N1_V01N0001
|
|
arc: C5 V02S0201
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: D2 V02N0201
|
|
arc: D5 W1_H02E0201
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F7
|
|
arc: V01S0000 F2
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICEC.K1.INIT 0010001100110011
|
|
word: SLICED.K1.INIT 1000000011000000
|
|
word: SLICEB.K0.INIT 0000010100001111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R19C16:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M3 H00L0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R19C17:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: B1 Q1
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H00L0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F0
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M3 H00L0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V01S0000 Q6
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R19C18:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 F5
|
|
arc: B0 H02W0101
|
|
arc: B1 F3
|
|
arc: B2 F3
|
|
arc: B3 H02E0301
|
|
arc: B5 H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C0 H00L0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00L0000
|
|
arc: C3 N1_V02S0401
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 H02E0001
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 V02N0601
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F6
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0501 Q7
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 0000110000001100
|
|
word: SLICEB.K1.INIT 0011001100110000
|
|
word: SLICEA.K0.INIT 0101000001010100
|
|
word: SLICEB.K0.INIT 0100010001010100
|
|
word: SLICEA.K1.INIT 0100010001010100
|
|
word: SLICEC.K1.INIT 0000000011001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R19C19:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 N1_V02S0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
word: SLICEA.K0.INIT 0100010001010100
|
|
word: SLICEA.K1.INIT 0100010001010100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R19C20:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: A3 V02N0501
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B3 Q3
|
|
arc: B5 F3
|
|
arc: B7 V00T0000
|
|
arc: C3 H02E0401
|
|
arc: C5 V00B0100
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 N1_V02S0001
|
|
arc: D5 N1_V02S0601
|
|
arc: D7 H02E0001
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M3 H02E0201
|
|
arc: M5 W1_H02E0001
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F5
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K1.INIT 1010101010101000
|
|
word: SLICED.K1.INIT 0101001100000000
|
|
word: SLICEC.K1.INIT 0000100000001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R19C21:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A5 F7
|
|
arc: A6 F7
|
|
arc: B1 F3
|
|
arc: B3 H02W0101
|
|
arc: B4 F3
|
|
arc: B7 H02W0101
|
|
arc: C1 N1_V01N0001
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0001
|
|
arc: C6 V02N0201
|
|
arc: C7 E1_H02W0401
|
|
arc: D1 V02N0001
|
|
arc: D3 H02E0201
|
|
arc: D4 V02S0601
|
|
arc: D5 V02S0601
|
|
arc: D6 V02S0601
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F4
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0601 F4
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K1.INIT 1111111110100000
|
|
word: SLICEB.K1.INIT 0011000000000000
|
|
word: SLICEC.K0.INIT 1111111111000000
|
|
word: SLICEA.K1.INIT 1111110011110000
|
|
word: SLICED.K1.INIT 0000000000110000
|
|
word: SLICED.K0.INIT 1111111110100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R19C22:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A4 E1_H02W0501
|
|
arc: C4 Q4
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 E1_H02W0001
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 F4
|
|
arc: LSR1 H02W0301
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N3_V06N0203 F4
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C23:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: B0 V02N0101
|
|
arc: B6 E1_H02W0101
|
|
arc: C0 N1_V02S0601
|
|
arc: C6 H02W0401
|
|
arc: CE0 H02E0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D6 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0303 F6
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICED.K0.INIT 1111110000001100
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C24:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 H02E0501
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B3 Q3
|
|
arc: B4 H02E0101
|
|
arc: B6 V00B0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0501 Q7
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICED.K1.INIT 0101010101011010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C25:PLC2
|
|
arc: H00L0000 H02W0201
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: A0 V02S0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 V00T0000
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 V00B0000
|
|
arc: A6 H02W0501
|
|
arc: A7 H00L0000
|
|
arc: B3 E1_H02W0301
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F0
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0501 F5
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F6
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICED.K1.INIT 0101010101011010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C26:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V00B0000
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V02N0101 Q3
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0301 F1
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C27:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: B1 H02W0101
|
|
arc: C1 S1_V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V02S0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0701 Q5
|
|
arc: N3_V06N0303 Q6
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R19C28:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 V02N0301
|
|
arc: A7 Q7
|
|
arc: B0 E1_H02W0301
|
|
arc: B3 S1_V02N0301
|
|
arc: C0 H02W0601
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 V01N0101
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D3 H02E0001
|
|
arc: D4 H01W0000
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 W1_H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0203 F7
|
|
arc: V01S0000 Q0
|
|
word: SLICED.K1.INIT 1010101011110000
|
|
word: SLICEC.K0.INIT 1111101001010000
|
|
word: SLICEC.K1.INIT 1111000011110000
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEB.K1.INIT 1010101011001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C29:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0103 V01N0101
|
|
arc: A0 H00R0000
|
|
arc: A3 H02W0501
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 V02S0101
|
|
arc: B2 H02W0101
|
|
arc: B4 S1_V02N0701
|
|
arc: B7 V00T0000
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 H02E0501
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0301 F3
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C2:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: A2 E1_H01E0001
|
|
arc: A4 F7
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 F5
|
|
arc: A7 Q7
|
|
arc: B2 H02E0301
|
|
arc: B4 H00R0000
|
|
arc: B5 H02E0301
|
|
arc: B7 V00T0000
|
|
arc: C2 V02N0401
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V02N0201
|
|
arc: C6 F4
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02E0001
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 H02E0001
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 F2
|
|
arc: E3_H06E0303 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K0.INIT 1011111100000000
|
|
word: SLICED.K1.INIT 0000000000110101
|
|
word: SLICEC.K1.INIT 0000000010111111
|
|
word: SLICEC.K0.INIT 0100000001010000
|
|
word: SLICED.K0.INIT 0000010100001111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R19C30:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A2 H02W0501
|
|
arc: A5 H02E0501
|
|
arc: B0 V00T0000
|
|
arc: B1 V00B0000
|
|
arc: B3 H00R0000
|
|
arc: B4 H02W0101
|
|
arc: B6 V02S0701
|
|
arc: B7 S1_V02N0701
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F7
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C31:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 H00L0000
|
|
arc: A2 E1_H02W0501
|
|
arc: A4 H02W0501
|
|
arc: A6 H02W0701
|
|
arc: B1 V02N0301
|
|
arc: B3 V02S0101
|
|
arc: B5 E1_H02W0301
|
|
arc: B7 V00B0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0601 F4
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F1
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C32:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: B0 E1_H02W0301
|
|
arc: B4 H01E0101
|
|
arc: B5 V01S0000
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 H02E0601
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V02N0601
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0501 Q5
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 Q7
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1111000011001100
|
|
word: SLICEC.K0.INIT 1111001111000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C33:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A0 H00L0100
|
|
arc: A1 E1_H01E0001
|
|
arc: B1 H00R0100
|
|
arc: B4 W1_H02E0301
|
|
arc: C0 W1_H02E0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C4 E1_H01E0101
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D4 V00B0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 H02E0301
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0301 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0301 Q1
|
|
word: SLICEC.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1100101011001010
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C34:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00R0000
|
|
arc: A4 V00B0000
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C4 H02W0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 W1_H02E0001
|
|
arc: D4 H02E0001
|
|
arc: E1_H01E0001 Q6
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0401 F4
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICEA.K1.INIT 1111101000001010
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C35:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: A0 E1_H01E0001
|
|
arc: C0 E1_H02W0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0701 Q5
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C36:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A1 W1_H02E0701
|
|
arc: B0 H02E0101
|
|
arc: C1 W1_H02E0401
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0601 Q4
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1100110011001100
|
|
word: SLICEA.K1.INIT 1111000010101010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R19C37:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00T0000 H02W0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: B0 V02S0301
|
|
arc: C0 H02E0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C38:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: A0 S1_V02N0501
|
|
arc: B0 V00T0000
|
|
arc: C0 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0101000001010100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C39:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00T0000 H02E0201
|
|
arc: A0 H01E0001
|
|
arc: C0 V02N0401
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 1010000010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C3:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 F0
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0000
|
|
arc: M3 H02W0201
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q5
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R19C41:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R19C44:PLC2
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R19C4:PLC2
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: C0 H02E0401
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 V02S0401
|
|
arc: C3 N1_V01S0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V02N0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R19C5:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H00L0000
|
|
arc: A2 V02N0501
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 V02N0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 H01E0101
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 E1_H02W0501
|
|
arc: M0 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0201 F0
|
|
arc: V00T0000 F2
|
|
word: SLICEB.K0.INIT 1000110000000000
|
|
word: SLICEA.K0.INIT 1101111111001111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C6:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 V02S0701
|
|
arc: B2 E1_H01W0100
|
|
arc: C0 E1_H01W0000
|
|
arc: C2 N1_V01S0100
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D2 H02W0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1010000001010000
|
|
word: SLICEB.K0.INIT 1100000000001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R19C7:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C8:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 N1_V02S0501
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 H00L0100
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 S1_V02N0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
word: SLICEA.K0.INIT 1100111011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R19C9:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 F5
|
|
arc: A5 Q5
|
|
arc: B3 Q3
|
|
arc: B4 F3
|
|
arc: B5 V02N0701
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 H01E0001
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 H02E0201
|
|
arc: D5 V02S0401
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V01S0000 F4
|
|
word: SLICEB.K1.INIT 0000110100000000
|
|
word: SLICEC.K1.INIT 1000000011000000
|
|
word: SLICEC.K0.INIT 1110000011101111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C10:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02W0601
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0003 Q3
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C11:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0501 Q5
|
|
arc: S1_V02S0301 Q1
|
|
arc: V01S0100 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C12:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A6 N1_V01N0101
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B6 H02E0301
|
|
arc: C0 H00R0100
|
|
arc: C6 V01N0101
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: D6 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02W0601
|
|
arc: M1 W1_H02E0001
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0601 F6
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICED.K0.INIT 1000110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C13:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A5 H02E0701
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C5 E1_H02W0601
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0001
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F5
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0401 Q4
|
|
arc: N3_V06N0303 F5
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEC.K1.INIT 0101000001010000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R20C14:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0103 N3_V06S0103
|
|
arc: W3_H06W0203 N3_V06S0203
|
|
arc: W3_H06W0303 N3_V06S0303
|
|
arc: A0 V02N0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0501
|
|
arc: A3 W1_H02E0501
|
|
arc: A6 H02W0501
|
|
arc: B0 H00R0100
|
|
arc: B1 F3
|
|
arc: B2 V01N0001
|
|
arc: B3 Q3
|
|
arc: B6 V00B0000
|
|
arc: C0 H02E0401
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H00L0000
|
|
arc: C6 N1_V02S0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V02N0201
|
|
arc: D2 N1_V02S0201
|
|
arc: D3 F2
|
|
arc: D6 H02E0001
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: V00B0000 Q6
|
|
word: SLICEB.K0.INIT 0100010101010101
|
|
word: SLICEA.K0.INIT 0000000100001011
|
|
word: SLICEB.K1.INIT 0000110100000000
|
|
word: SLICEA.K1.INIT 1010111110001101
|
|
word: SLICED.K0.INIT 1010101010101000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C15:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A1 V02S0501
|
|
arc: A3 F7
|
|
arc: A7 Q7
|
|
arc: B1 F3
|
|
arc: B3 Q3
|
|
arc: B7 W1_H02E0301
|
|
arc: C1 H00L0100
|
|
arc: C3 H02E0601
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D3 H01E0101
|
|
arc: D7 H01W0000
|
|
arc: E1_H02E0401 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: S1_V02S0301 F1
|
|
word: SLICED.K1.INIT 0000010011000100
|
|
word: SLICEB.K1.INIT 0100010100000000
|
|
word: SLICEA.K1.INIT 1110000011101111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R20C16:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A0 H02E0501
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 F5
|
|
arc: A7 H02E0501
|
|
arc: B0 E1_H01W0100
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 H02E0101
|
|
arc: B5 H02E0101
|
|
arc: B6 H02E0301
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 H02E0601
|
|
arc: C2 S1_V02N0401
|
|
arc: C4 Q4
|
|
arc: C5 H02E0601
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 H02E0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 V00T0100
|
|
arc: D3 S1_V02N0001
|
|
arc: D4 V02N0601
|
|
arc: D5 V02S0601
|
|
arc: D6 F0
|
|
arc: D7 F2
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0401 F6
|
|
arc: V00B0000 F4
|
|
arc: V00T0100 Q1
|
|
word: SLICEC.K0.INIT 1100010000000000
|
|
word: SLICEA.K0.INIT 1011101011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
word: SLICEC.K1.INIT 0010001100000000
|
|
word: SLICED.K1.INIT 1010001000000000
|
|
word: SLICED.K0.INIT 1100100011111011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C17:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 W1_H02E0501
|
|
arc: A2 H00L0100
|
|
arc: A5 W1_H02E0501
|
|
arc: A7 F5
|
|
arc: B0 V00B0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B5 H02E0301
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 H02W0601
|
|
arc: C2 H02E0401
|
|
arc: C5 E1_H01E0101
|
|
arc: C7 H02W0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D2 Q2
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 F2
|
|
arc: E1_H01E0101 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 F7
|
|
word: SLICEA.K0.INIT 1011101011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0100000001110000
|
|
word: SLICEC.K1.INIT 1010101010101000
|
|
word: SLICED.K1.INIT 0000000010001010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R20C18:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0701
|
|
arc: A7 Q7
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V00B0000
|
|
arc: B7 V00T0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 N1_V01S0100
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D7 H02W0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0501 F7
|
|
arc: S3_V06S0103 Q1
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K1.INIT 0000001100000101
|
|
word: SLICEA.K0.INIT 0101000001010100
|
|
word: SLICEA.K1.INIT 0101000001010100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R20C19:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A4 V02N0101
|
|
arc: A6 F7
|
|
arc: A7 V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B6 V01S0000
|
|
arc: B7 V02N0701
|
|
arc: C0 V02N0401
|
|
arc: C4 Q4
|
|
arc: C6 F4
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D4 V01N0001
|
|
arc: D6 H00R0100
|
|
arc: D7 E1_H02W0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0601 F6
|
|
word: SLICED.K1.INIT 1111111000000000
|
|
word: SLICEC.K0.INIT 0001101100000000
|
|
word: SLICED.K0.INIT 0000100000001010
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R20C20:PLC2
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H02W0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R20C21:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: C0 H02W0401
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q1
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00T0100 Q3
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R20C22:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V01S0000 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C23:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: B0 H02W0101
|
|
arc: C0 E1_H02W0401
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S3_V06S0003 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C24:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A1 E1_H02W0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V02S0101
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 V02S0301
|
|
arc: B1 H02W0101
|
|
arc: B5 V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 H00L0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C4 N1_V02S0201
|
|
arc: C5 E1_H02W0401
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00R0100
|
|
arc: CE2 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 V01S0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 N1_V02S0601
|
|
arc: D7 V02N0401
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q4
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0001 Q0
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F7
|
|
word: SLICEA.K0.INIT 1100111100000011
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICED.K1.INIT 1000001001000001
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 1111010110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C25:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: A3 V02S0501
|
|
arc: A6 V02S0301
|
|
arc: B1 V00T0000
|
|
arc: B3 V02N0101
|
|
arc: B5 H02W0301
|
|
arc: B6 N1_V01S0000
|
|
arc: C1 V02N0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 V02N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 H01W0000
|
|
arc: D5 V02N0401
|
|
arc: D6 S1_V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 F0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M2 H02W0601
|
|
arc: M4 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q1
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0501 Q7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0401 F4
|
|
word: SLICEB.K1.INIT 1001000000001001
|
|
word: SLICED.K0.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111110000001100
|
|
word: SLICEC.K0.INIT 1111111100000000
|
|
word: SLICEC.K1.INIT 1111000011001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R20C26:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 H00L0000
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0701
|
|
arc: A3 V02N0501
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V02N0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V00B0000
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 V02N0701
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V02N0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 V02S0201
|
|
arc: D4 V00B0000
|
|
arc: D5 V02S0401
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
word: SLICEA.K0.INIT 0000010011111110
|
|
word: SLICEA.K1.INIT 1111111000000010
|
|
word: SLICEB.K0.INIT 1010101110101000
|
|
word: SLICEB.K1.INIT 1010101110101000
|
|
word: SLICEC.K0.INIT 1111000011100010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C27:PLC2
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: B0 S1_V02N0101
|
|
arc: C0 H00L0000
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C28:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: B1 V01N0001
|
|
arc: C1 V02N0401
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V00B0100
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0101 Q2
|
|
arc: V01S0100 Q1
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R20C29:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A5 H02W0701
|
|
arc: B0 H01W0100
|
|
arc: B1 V02S0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 N1_V01N0001
|
|
arc: C5 V01N0101
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0201
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q3
|
|
arc: LSR1 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0501 Q5
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEC.K1.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C2:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: A0 H00L0000
|
|
arc: A2 F5
|
|
arc: A5 Q5
|
|
arc: B0 H02W0101
|
|
arc: B2 H01W0100
|
|
arc: B5 V01S0000
|
|
arc: C0 H02E0401
|
|
arc: C2 H02W0401
|
|
arc: C5 S1_V02N0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D2 F0
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0001 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 E1_H02W0601
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q6
|
|
word: SLICEC.K1.INIT 0011010100000000
|
|
word: SLICEA.K0.INIT 1111111000000000
|
|
word: SLICEB.K0.INIT 0100010100000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C30:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H02E0501
|
|
arc: A1 V01N0101
|
|
arc: A2 V00T0000
|
|
arc: A4 E1_H01W0000
|
|
arc: B1 Q1
|
|
arc: B3 V01N0001
|
|
arc: B4 V02S0501
|
|
arc: C0 H02E0601
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 H00L0100
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H00R0000
|
|
arc: D4 S1_V02N0401
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: LSR0 W1_H02E0501
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 F3
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0303 Q6
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEA.K1.INIT 0011001110101010
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
word: SLICEC.K0.INIT 1100110010101010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C31:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A0 V02N0701
|
|
arc: A4 V02S0301
|
|
arc: A5 E1_H02W0501
|
|
arc: B1 V01N0001
|
|
arc: B3 S1_V02N0301
|
|
arc: C0 H02E0601
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0001
|
|
arc: C5 V00B0100
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 H02W0201
|
|
arc: D3 V02S0001
|
|
arc: D4 V02S0401
|
|
arc: D5 H00R0100
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M2 V00B0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q5
|
|
arc: N1_V02N0301 Q1
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEC.K0.INIT 1111101001010000
|
|
word: SLICEC.K1.INIT 1111101000001010
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1100111111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C32:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N1_V02S0601
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A2 H02W0701
|
|
arc: A3 V00B0000
|
|
arc: B0 H02E0301
|
|
arc: B4 V01S0000
|
|
arc: C0 W1_H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 V02S0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 V02S0001
|
|
arc: D3 H02W0001
|
|
arc: D4 W1_H02E0001
|
|
arc: E1_H01E0001 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0601 Q6
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
word: SLICEC.K0.INIT 1111110000001100
|
|
word: SLICEB.K1.INIT 1010101011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C33:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 V02S0501
|
|
arc: A1 H00L0100
|
|
arc: A2 W1_H02E0501
|
|
arc: A6 H02W0701
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 E1_H01W0100
|
|
arc: B7 H02W0301
|
|
arc: C0 H00R0100
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 S1_V02N0401
|
|
arc: C6 N1_V02S0001
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V02S0201
|
|
arc: D3 V02N0201
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F6
|
|
arc: N3_V06N0203 F7
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0201 F2
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICED.K1.INIT 1100111111000000
|
|
word: SLICEB.K0.INIT 1101100011011000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 1111000111100000
|
|
word: SLICEA.K1.INIT 1100110111001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C34:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 H02W0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 H02W0701
|
|
arc: A7 Q7
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 Q3
|
|
arc: B6 V00B0000
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 N1_V01S0100
|
|
arc: C6 V02N0201
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D6 H01W0000
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M5 V01S0000
|
|
arc: M6 N1_V01N0101
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 F2
|
|
arc: N3_V06N0203 F7
|
|
arc: N3_V06N0303 F6
|
|
arc: V00B0000 Q6
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICED.K0.INIT 1100111111000000
|
|
word: SLICED.K1.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1111000011110000
|
|
word: SLICEB.K0.INIT 1101100011011000
|
|
word: SLICEB.K1.INIT 1100110011001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C35:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 E1_H02W0501
|
|
arc: A4 E1_H01W0000
|
|
arc: A7 H02W0501
|
|
arc: B0 V00T0000
|
|
arc: B6 V00T0000
|
|
arc: C4 V02N0001
|
|
arc: C6 V01N0101
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 V01S0100
|
|
arc: D4 S1_V02N0601
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0101 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q5
|
|
arc: N3_V06N0203 F4
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0501 F7
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEC.K0.INIT 1010101011110000
|
|
word: SLICEA.K0.INIT 1101110110001000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICED.K1.INIT 1010101011110000
|
|
word: SLICED.K0.INIT 1100110011110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C36:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0000 H02E0601
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: B0 H01W0100
|
|
arc: C0 E1_H01W0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 S1_V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q5
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C37:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A5 V00B0000
|
|
arc: B0 H02W0101
|
|
arc: B1 V02S0101
|
|
arc: B5 N1_V01S0000
|
|
arc: C0 H02E0401
|
|
arc: C1 S1_V02N0401
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 V02S0001
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 F1
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 F1
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0103 F1
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111111000001110
|
|
word: SLICEA.K1.INIT 1111000011000000
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C38:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: B0 E1_H01W0100
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H00L0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 N1_V01S0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q1
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C39:PLC2
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: A2 V00T0000
|
|
arc: A3 H01E0001
|
|
arc: A5 V00B0000
|
|
arc: A7 V02N0101
|
|
arc: B0 S1_V02N0101
|
|
arc: B4 H02E0301
|
|
arc: B6 N1_V01S0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F3
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 H02E0501
|
|
arc: M0 E1_H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0401 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F7
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C3:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A2 V00T0000
|
|
arc: A4 F7
|
|
arc: A7 Q7
|
|
arc: B2 S1_V02N0101
|
|
arc: B4 V01S0000
|
|
arc: B7 V00B0100
|
|
arc: C2 V02N0401
|
|
arc: C4 V02N0001
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 E1_H02W0001
|
|
arc: D4 F2
|
|
arc: D7 H00L0100
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: M1 H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M4 V00B0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 0000000100001101
|
|
word: SLICEB.K0.INIT 0000000010111111
|
|
word: SLICEC.K0.INIT 0100010100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C40:PLC2
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: A0 V01N0101
|
|
arc: B1 V01N0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: S1_V02S0001 F0
|
|
arc: V01S0000 F1
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R20C41:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: C0 H02E0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R20C42:PLC2
|
|
arc: W1_H02W0101 V01N0101
|
|
|
|
.tile R20C43:PLC2
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
|
|
.tile R20C44:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0303 H06E0303
|
|
|
|
.tile R20C45:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C47:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C4:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A1 H00R0000
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 Q3
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1100110010101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R20C50:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C51:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R20C53:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C56:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R20C57:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C59:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C5:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A3 V00T0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 F3
|
|
arc: B3 Q3
|
|
arc: C0 V02N0401
|
|
arc: C1 V02S0601
|
|
arc: C3 V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 F0
|
|
arc: D3 V02S0001
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
word: SLICEA.K0.INIT 1000110000000000
|
|
word: SLICEB.K1.INIT 0100010100000000
|
|
word: SLICEA.K1.INIT 1010111110001101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R20C62:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C63:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C65:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R20C68:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R20C69:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R20C6:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 V02S0501
|
|
arc: A2 V00T0000
|
|
arc: B0 V02N0301
|
|
arc: C0 V02N0601
|
|
arc: C2 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K0.INIT 1111010111110101
|
|
word: SLICEA.K0.INIT 0011011100000101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C71:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R20C74:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R20C75:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R20C77:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R20C7:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 V01N0001
|
|
arc: A0 H00R0000
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 S1_V02N0501
|
|
arc: A6 E1_H02W0501
|
|
arc: B1 Q1
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 V02S0101
|
|
arc: B6 S1_V02N0701
|
|
arc: C0 H00L0100
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C6 Q6
|
|
arc: C7 H01E0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00L0000
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 H02W0201
|
|
arc: D3 S1_V02N0001
|
|
arc: D6 F0
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 F3
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F2
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICED.K0.INIT 1100010000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R20C80:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C81:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R20C83:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R20C86:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C87:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R20C88:PLC2
|
|
arc: D6 V01N0001
|
|
arc: E1_H01E0101 F6
|
|
arc: F6 F6_SLICE
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R20C8:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0100 H02E0301
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A5 V02S0101
|
|
arc: B0 V02S0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 V02N0601
|
|
arc: C5 V02S0001
|
|
arc: C6 V02S0001
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D5 V02N0601
|
|
arc: D6 V02N0601
|
|
arc: E1_H01E0001 F6
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: M0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICED.K0.INIT 0000110000000000
|
|
word: SLICEC.K1.INIT 0000000000001010
|
|
word: SLICEA.K0.INIT 0000000000110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R20C9:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A7 H00L0000
|
|
arc: B0 V02N0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B4 H00L0000
|
|
arc: B5 H00L0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C4 H02E0601
|
|
arc: C5 H02E0601
|
|
arc: C7 H02E0601
|
|
arc: CE0 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 N1_V02S0001
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0001
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F2
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F1
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 F5
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F5
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEB.K0.INIT 0011000000000000
|
|
word: SLICEC.K1.INIT 1100000000000000
|
|
word: SLICEC.K0.INIT 0000110000000000
|
|
word: SLICED.K1.INIT 0000000000000101
|
|
word: SLICEA.K0.INIT 1100001100000000
|
|
word: SLICEA.K1.INIT 0000001100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R21C10:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: A0 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 V02S0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 V02N0201
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 1010000001010000
|
|
word: SLICEA.K0.INIT 1010000001010000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R21C11:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A2 V00B0000
|
|
arc: A3 F5
|
|
arc: A5 Q5
|
|
arc: A6 S1_V02N0301
|
|
arc: B0 V02S0301
|
|
arc: B1 Q1
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 Q3
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 F3
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 H02W0401
|
|
arc: C5 W1_H02E0401
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02E0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 F2
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 H02W0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 0000001100010001
|
|
word: SLICEC.K1.INIT 0000101100001111
|
|
word: SLICEB.K1.INIT 0000000010001010
|
|
word: SLICED.K0.INIT 1110000011101111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C12:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 F7
|
|
arc: A3 F5
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 Q5
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B2 V02S0301
|
|
arc: B3 Q3
|
|
arc: B4 H02W0301
|
|
arc: B5 H02W0301
|
|
arc: B6 F3
|
|
arc: B7 V00T0000
|
|
arc: C0 H02E0401
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 F4
|
|
arc: C4 H02E0401
|
|
arc: C5 V00T0000
|
|
arc: C6 N1_V02S0201
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 V02N0001
|
|
arc: D4 H02W0201
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 F2
|
|
arc: D7 H02W0001
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEA.K0.INIT 1111001011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000100110001
|
|
word: SLICEC.K0.INIT 0000101100001111
|
|
word: SLICED.K1.INIT 1111000011100000
|
|
word: SLICEB.K0.INIT 0010001000000010
|
|
word: SLICEB.K1.INIT 0100000001010000
|
|
word: SLICED.K0.INIT 1010111110001101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C13:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A2 H02W0701
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 V00B0000
|
|
arc: A5 V02N0301
|
|
arc: A6 H00R0000
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 V00T0000
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0101
|
|
arc: B4 H02W0101
|
|
arc: B5 V02N0701
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 V02N0501
|
|
arc: CE0 V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F7
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R21C14:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 H02E0501
|
|
arc: A1 V02N0701
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 H02W0501
|
|
arc: A5 V02N0301
|
|
arc: A6 H00R0000
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 H02W0101
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B5 H02E0101
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 V02N0501
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: M3 W1_H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: V01S0000 F2
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R21C15:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 H02E0701
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0701
|
|
arc: B0 H02W0101
|
|
arc: B1 H02W0301
|
|
arc: B2 V02N0301
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0201 F0
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R21C16:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A2 H02W0701
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: C0 V02N0401
|
|
arc: C1 H00L0100
|
|
arc: C2 V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V02N0001
|
|
arc: D2 V02S0001
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0001 F0
|
|
arc: V01S0100 Q4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 0100010101010101
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C17:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A2 W1_H02E0701
|
|
arc: A5 H02W0701
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B4 H01E0101
|
|
arc: B5 N1_V01S0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0100
|
|
arc: C2 H02W0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 F4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D4 F2
|
|
arc: D5 W1_H02E0001
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F0
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0100
|
|
arc: M5 H02W0001
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0501 F5
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1000101000000000
|
|
word: SLICEC.K0.INIT 0000000000111111
|
|
word: SLICEC.K1.INIT 1110111000001111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C18:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A3 H02E0501
|
|
arc: A5 N1_V01N0101
|
|
arc: B0 H02W0101
|
|
arc: B1 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 F3
|
|
arc: C0 H02E0601
|
|
arc: C3 H00L0100
|
|
arc: C4 H02W0601
|
|
arc: C5 V00B0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V00T0100
|
|
arc: D3 H02W0001
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 H00R0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F4
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0203 F4
|
|
arc: V00B0100 Q5
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEB.K1.INIT 0101000101010101
|
|
word: SLICEC.K1.INIT 0000000011000100
|
|
word: SLICEC.K0.INIT 1111111100110000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R21C19:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02S0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 H00L0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0001
|
|
arc: E1_H01E0101 Q6
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0601 Q6
|
|
arc: S3_V06S0303 Q6
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R21C20:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0303 V06S0303
|
|
arc: A2 H02W0501
|
|
arc: A4 H02W0701
|
|
arc: A6 F7
|
|
arc: A7 Q7
|
|
arc: B3 Q3
|
|
arc: B4 N1_V01S0000
|
|
arc: B6 H02W0301
|
|
arc: B7 E1_H02W0301
|
|
arc: C2 H00L0100
|
|
arc: C4 Q4
|
|
arc: C6 F4
|
|
arc: C7 W1_H02E0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 N1_V02S0601
|
|
arc: D6 H02W0001
|
|
arc: D7 F2
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 F6
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
word: SLICEB.K0.INIT 1010101011110000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
word: SLICED.K1.INIT 1000110000000000
|
|
word: SLICEC.K0.INIT 0100000001000100
|
|
word: SLICED.K0.INIT 1100100011111011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C21:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0003 V06S0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 V06S0303
|
|
arc: A0 H00L0100
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B7 H02W0301
|
|
arc: C0 S1_V02N0601
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D7 S1_V02N0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M5 V01S0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0100 F7
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICED.K1.INIT 1000000011000000
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R21C22:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 H02W0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W3_H06W0003 V06S0003
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 S1_V02N0101
|
|
arc: A7 F5
|
|
arc: B0 E1_H01W0100
|
|
arc: B2 H00L0000
|
|
arc: B3 H00R0000
|
|
arc: B4 F3
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 H02E0301
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 H02E0601
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: D4 F0
|
|
arc: D5 F2
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 F7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: V00B0000 F4
|
|
word: SLICEA.K0.INIT 0101000000110000
|
|
word: SLICEB.K1.INIT 1010101010101000
|
|
word: SLICEB.K0.INIT 0100010101010101
|
|
word: SLICEC.K1.INIT 0100010100000000
|
|
word: SLICEC.K0.INIT 0000000010001100
|
|
word: SLICED.K1.INIT 1100111110001011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C23:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C24:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: A1 N1_V02S0701
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 F5
|
|
arc: A7 N1_V01N0101
|
|
arc: B1 V02S0301
|
|
arc: B5 H02W0101
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 E1_H02W0301
|
|
arc: C1 N1_V02S0401
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 N1_V02S0201
|
|
arc: D1 V02N0001
|
|
arc: D5 N1_V02S0601
|
|
arc: D6 F0
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02W0601
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000001001000001
|
|
word: SLICEC.K1.INIT 1001000000001001
|
|
word: SLICED.K1.INIT 0100100000010010
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C25:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 W1_H02E0501
|
|
arc: A2 H02E0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V02N0301
|
|
arc: A6 H02W0701
|
|
arc: A7 H02E0501
|
|
arc: B2 V02S0101
|
|
arc: B3 H02E0101
|
|
arc: B4 V02S0501
|
|
arc: B5 V00B0100
|
|
arc: B6 H02E0301
|
|
arc: B7 V00T0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 F3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0501 Q5
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 F5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C26:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A0 V02S0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V00T0000
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 H00R0000
|
|
arc: A7 H02E0701
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 H00L0000
|
|
arc: B3 H00R0100
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 H02W0101
|
|
arc: B6 H02W0301
|
|
arc: B7 V01S0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F3
|
|
arc: V01S0100 F7
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C27:PLC2
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 H00L0000
|
|
arc: A3 N1_V02S0701
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 H02W0501
|
|
arc: B0 V02S0101
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 H02W0301
|
|
arc: B4 V02S0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: M3 H00L0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0203 Q7
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0203 F4
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0501 Q7
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C28:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A0 H02E0701
|
|
arc: A4 V02N0301
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 E1_H02W0701
|
|
arc: B4 V02N0701
|
|
arc: B5 H02W0301
|
|
arc: B6 V02S0701
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0201
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 V02N0401
|
|
arc: D6 S1_V02N0601
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q5
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 H02E0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010101100
|
|
word: SLICEC.K0.INIT 1100110011001010
|
|
word: SLICEC.K1.INIT 1100110111001000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C29:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: A6 V02S0301
|
|
arc: A7 V02S0101
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02N0501
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C2:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 H02W0301
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V02N0201
|
|
arc: E1_H02E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R21C30:PLC2
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 E1_H02W0701
|
|
arc: A4 W1_H02E0701
|
|
arc: A6 H02W0701
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0301
|
|
arc: B3 H02W0301
|
|
arc: B5 H02E0101
|
|
arc: B7 S1_V02N0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 F4
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 F7
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C31:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A1 H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 V00B0000
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 H02W0101
|
|
arc: B2 V02N0101
|
|
arc: B4 V02N0501
|
|
arc: B6 H02W0301
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F2
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C32:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 E1_H02W0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: A6 V02S0101
|
|
arc: A7 H02E0701
|
|
arc: B4 H01E0101
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 W1_H02E0201
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 H02E0001
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0103 Q1
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0501 Q7
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 1100110111001000
|
|
word: SLICEC.K0.INIT 1111111000000100
|
|
word: SLICEC.K1.INIT 1111111000000100
|
|
word: SLICED.K1.INIT 1100110011001010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C33:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 H00L0000
|
|
arc: A2 H01E0001
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 N1_V02S0301
|
|
arc: A5 V02N0101
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 V02S0101
|
|
arc: B3 V02N0301
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 N1_V02S0501
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 N1_V02S0601
|
|
arc: C4 V00B0100
|
|
arc: C5 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 V00B0100
|
|
arc: D4 W1_H02E0201
|
|
arc: D5 E1_H02W0001
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F0
|
|
arc: N3_V06N0303 Q6
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111100010001000
|
|
word: SLICEB.K0.INIT 1010101110101000
|
|
word: SLICEB.K1.INIT 1100110011011000
|
|
word: SLICEC.K0.INIT 1111111000000010
|
|
word: SLICEC.K1.INIT 1111111000010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C34:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 V00T0000
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 H00R0100
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 H00L0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D2 S1_V02N0001
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: W1_H02W0301 Q1
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEB.K0.INIT 1100110011001010
|
|
word: SLICEA.K1.INIT 1111000011100010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C35:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0003 V06N0003
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 S1_V02N0501
|
|
arc: B4 E1_H02W0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D4 H02E0001
|
|
arc: E1_H01E0101 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0401 Q4
|
|
arc: N3_V06N0203 Q4
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C36:PLC2
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: C0 H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q7
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C37:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: B0 H02E0301
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C38:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: A1 N1_V02S0501
|
|
arc: A5 E1_H01W0000
|
|
arc: B1 E1_H02W0301
|
|
arc: B5 N1_V01S0000
|
|
arc: C1 H00L0100
|
|
arc: C5 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 E1_H02W0001
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0101 F0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00B0100 F5
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C39:PLC2
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: A0 V02S0701
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: S1_V02S0301 Q1
|
|
arc: W1_H02W0101 Q1
|
|
word: SLICEA.K0.INIT 1010000010100000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C3:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: A0 H00L0000
|
|
arc: A2 F5
|
|
arc: A4 V02S0101
|
|
arc: A5 S1_V02N0301
|
|
arc: B1 Q1
|
|
arc: B2 E1_H02W0101
|
|
arc: B4 V01S0000
|
|
arc: C0 H00R0100
|
|
arc: C2 N1_V01S0100
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 F4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V02S0201
|
|
arc: D4 H02E0001
|
|
arc: D5 F0
|
|
arc: E1_H01E0001 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 Q7
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q4
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEC.K0.INIT 1000101000000000
|
|
word: SLICEC.K1.INIT 0000010100001111
|
|
word: SLICEB.K0.INIT 1101110111010001
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C40:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02S0001
|
|
arc: D2 N1_V01S0000
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q1
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0301 Q1
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C41:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
|
|
.tile R21C42:PLC2
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
|
|
.tile R21C43:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
|
|
.tile R21C44:PLC2
|
|
arc: H00R0100 H02W0701
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: C0 V02S0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R21C45:PLC2
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
|
|
.tile R21C47:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R21C4:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: A3 V00B0000
|
|
arc: A4 N1_V01N0101
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: B4 F3
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 E1_H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D3 V02S0001
|
|
arc: D4 E1_H01W0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M3 H02E0201
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q4
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0601 F4
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 1111111000000000
|
|
word: SLICEC.K0.INIT 0000000010001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C5:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 E1_H02W0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V02N0501
|
|
arc: A6 N1_V02S0301
|
|
arc: B0 S1_V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 H02W0301
|
|
arc: B6 H02W0301
|
|
arc: C0 E1_H02W0601
|
|
arc: C2 H00L0100
|
|
arc: C3 V02S0601
|
|
arc: C6 V02N0001
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 V00B0100
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 F2
|
|
arc: M1 H00R0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 H00L0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0601 F6
|
|
arc: S3_V06S0303 F6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0301 F3
|
|
arc: W1_H02W0401 F6
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1100100011111011
|
|
word: SLICEB.K0.INIT 0001110100000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C6:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0501
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 F5
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 V02S0301
|
|
arc: A6 F7
|
|
arc: A7 Q7
|
|
arc: B2 S1_V02N0301
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 H02E0101
|
|
arc: B6 F3
|
|
arc: B7 V00T0000
|
|
arc: C0 H00L0100
|
|
arc: C2 H02W0401
|
|
arc: C3 V02N0401
|
|
arc: C4 Q4
|
|
arc: C5 V02N0001
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 F4
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 V02S0001
|
|
arc: D3 F0
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 V02N0601
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M4 H02E0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0601 F6
|
|
arc: V00T0000 F2
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEA.K1.INIT 1111111110101010
|
|
word: SLICEC.K1.INIT 1000000010100000
|
|
word: SLICEC.K0.INIT 0000000101000101
|
|
word: SLICEB.K0.INIT 0000000010111111
|
|
word: SLICED.K1.INIT 0000100000001100
|
|
word: SLICEB.K1.INIT 0000010101010101
|
|
word: SLICED.K0.INIT 1111001110100011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R21C7:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 H02W0701
|
|
arc: A5 Q5
|
|
arc: A6 H02W0701
|
|
arc: A7 V02S0101
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: B2 V02N0301
|
|
arc: B3 V02S0101
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0701
|
|
arc: B6 V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C1 H00L0100
|
|
arc: C2 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C4 V02N0001
|
|
arc: C5 H02E0401
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 V02S0201
|
|
arc: D3 V02N0001
|
|
arc: D4 H00R0100
|
|
arc: D5 F0
|
|
arc: D6 H00R0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M3 H02E0201
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V02N0001 F2
|
|
arc: S1_V02S0401 F4
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F6
|
|
arc: V00B0000 Q6
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEB.K0.INIT 0000100000000000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0010000000000000
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 0010000000000000
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEC.K1.INIT 0010001100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C88:PLC2
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
|
|
.tile R21C8:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H00L0100
|
|
arc: A1 S1_V02N0501
|
|
arc: A6 S1_V02N0301
|
|
arc: B1 Q1
|
|
arc: B6 V02S0501
|
|
arc: C0 H02W0601
|
|
arc: C1 H02W0601
|
|
arc: C6 H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V02N0001
|
|
arc: D6 S1_V02N0401
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00L0100 Q1
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F6
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 0000111000000100
|
|
word: SLICED.K0.INIT 1010100011111101
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C9:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H00L0100
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 V00T0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V00T0000
|
|
arc: B2 N1_V02S0301
|
|
arc: B4 H00L0000
|
|
arc: C0 H00L0000
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C4 Q4
|
|
arc: CE0 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V02S0001
|
|
arc: D2 V00B0100
|
|
arc: D4 H02W0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 Q4
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F2
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K1.INIT 1100100011111011
|
|
word: SLICEB.K0.INIT 1010100011111101
|
|
word: SLICEA.K0.INIT 0111111110000000
|
|
word: SLICEC.K0.INIT 0011110011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R23C10:PLC2
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: H00L0000 H02W0001
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: A3 V02S0701
|
|
arc: B0 V02S0101
|
|
arc: C0 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0100 Q3
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K1.INIT 1010000000001010
|
|
word: SLICEA.K0.INIT 1100000000001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R23C11:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 H00L0000
|
|
arc: A3 H02W0701
|
|
arc: A4 N1_V02S0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B3 Q3
|
|
arc: B4 V01S0000
|
|
arc: C0 W1_H02E0601
|
|
arc: C3 F4
|
|
arc: C4 Q4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D3 F0
|
|
arc: D4 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0301 F3
|
|
arc: V01S0000 Q6
|
|
word: SLICEA.K0.INIT 1011000011110000
|
|
word: SLICEC.K0.INIT 0000000000011011
|
|
word: SLICEB.K1.INIT 0000110100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C12:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A2 H02E0701
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00R0100
|
|
arc: C2 H00L0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D2 V01S0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 E1_H02W0601
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0001 F2
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1000000010100000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R23C13:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A1 H00L0100
|
|
arc: B1 N1_V02S0301
|
|
arc: C1 N1_V02S0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V02S0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H02E0301 F1
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q2
|
|
arc: N3_V06N0103 Q2
|
|
word: SLICEA.K1.INIT 1111000011100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C14:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A1 H00R0000
|
|
arc: A5 V00T0000
|
|
arc: A6 N1_V02S0101
|
|
arc: B1 Q1
|
|
arc: B5 V02N0501
|
|
arc: B6 E1_H02W0101
|
|
arc: C0 H00L0100
|
|
arc: C5 H02E0401
|
|
arc: C6 V02N0001
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 V02N0601
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 F0
|
|
arc: M0 V00T0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M3 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F6
|
|
word: SLICED.K0.INIT 1010100011111101
|
|
word: SLICEC.K1.INIT 1010100011111101
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1010101011001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R23C15:PLC2
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: A2 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: B2 W1_H02E0301
|
|
arc: B4 H00R0000
|
|
arc: C2 F4
|
|
arc: C4 N1_V02S0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V01S0100
|
|
arc: D4 W1_H02E0001
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 F2
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q2
|
|
word: SLICEC.K0.INIT 0011010100000000
|
|
word: SLICEB.K0.INIT 0000100000001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R23C16:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
|
|
.tile R23C17:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A5 Q5
|
|
arc: B5 H02E0101
|
|
arc: C5 V00T0100
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 H02E0001
|
|
arc: E1_H02E0701 F5
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
word: SLICEC.K1.INIT 0000101100001111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C18:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A0 H00L0000
|
|
arc: B0 V02N0301
|
|
arc: C0 V02N0601
|
|
arc: C4 H02E0601
|
|
arc: D0 H00R0000
|
|
arc: D4 H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 F4
|
|
arc: M0 V00B0100
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010000100000100
|
|
word: SLICEC.K0.INIT 1111000000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R23C19:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A2 F7
|
|
arc: A4 N1_V02S0101
|
|
arc: A7 Q7
|
|
arc: B2 H01W0100
|
|
arc: B4 V01S0000
|
|
arc: B7 V00B0100
|
|
arc: C2 H02E0601
|
|
arc: C4 N1_V02S0201
|
|
arc: C7 N1_V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H00R0000
|
|
arc: D4 V00B0000
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K1.INIT 0100000001110000
|
|
word: SLICEC.K0.INIT 1111000011100000
|
|
word: SLICEB.K0.INIT 0100010100000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R23C20:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: W3_H06W0303 V06N0303
|
|
arc: A1 F7
|
|
arc: A2 V00T0000
|
|
arc: A4 H02W0501
|
|
arc: A7 Q7
|
|
arc: B1 H02W0101
|
|
arc: B2 H02E0301
|
|
arc: B4 H02E0101
|
|
arc: B7 N1_V02S0701
|
|
arc: C1 V02N0401
|
|
arc: C2 N1_V01N0001
|
|
arc: C4 Q4
|
|
arc: C7 F4
|
|
arc: CE0 H00R0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H01E0101
|
|
arc: D2 N1_V02S0201
|
|
arc: D4 H02E0001
|
|
arc: D7 F2
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 H02W0601
|
|
arc: M2 H02W0601
|
|
arc: M4 H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V00T0000 Q2
|
|
word: SLICEB.K0.INIT 0000001100010001
|
|
word: SLICEC.K0.INIT 0101000101010101
|
|
word: SLICED.K1.INIT 0000000010110000
|
|
word: SLICEA.K1.INIT 1100111110001011
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C21:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A3 H00L0100
|
|
arc: B0 V02S0301
|
|
arc: B3 N1_V02S0301
|
|
arc: C0 V02S0401
|
|
arc: C3 N1_V01N0001
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D3 N1_V02S0201
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02W0301
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V01S0000 Q7
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K1.INIT 0001000100000011
|
|
word: SLICEA.K0.INIT 0000111111001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C22:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: B1 Q1
|
|
arc: C0 H00R0100
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: V01S0000 Q2
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R23C23:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: A7 Q7
|
|
arc: B7 H02E0301
|
|
arc: C7 V00B0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D7 H00R0100
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 F7
|
|
word: SLICED.K1.INIT 0001000100000011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C24:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: B0 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: C0 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: D0 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 F0
|
|
arc: N3_V06N0003 F3
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
word: SLICEB.K1.INIT 0000110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R23C25:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: A1 H00L0000
|
|
arc: A3 V02S0701
|
|
arc: A5 Q5
|
|
arc: B1 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: C1 N1_V02S0401
|
|
arc: C3 N1_V02S0601
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 V02N0201
|
|
arc: D5 V00B0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0000
|
|
arc: M2 H02W0601
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0201 F0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0501 Q5
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1110101011000000
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110101011000000
|
|
word: SLICEC.K1.INIT 0101010100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C26:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A0 H02E0501
|
|
arc: A2 H02W0701
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 V00T0000
|
|
arc: A5 H02W0501
|
|
arc: A7 V02S0301
|
|
arc: B2 V02S0101
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 H00R0000
|
|
arc: B6 V00B0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F5
|
|
arc: N1_V01N0101 F4
|
|
arc: S1_V02S0501 F7
|
|
arc: V01S0000 F3
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C27:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A0 H02W0701
|
|
arc: A2 H02E0701
|
|
arc: A3 H02W0501
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 V00T0000
|
|
arc: B1 E1_H02W0101
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 V00B0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0101 F3
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F2
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C28:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 H02W0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A4 V00T0000
|
|
arc: A6 N1_V02S0101
|
|
arc: A7 H02E0701
|
|
arc: B2 H02E0301
|
|
arc: B3 E1_H02W0101
|
|
arc: B5 E1_H02W0301
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: V01S0000 F3
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C29:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A5 V02N0301
|
|
arc: B0 N1_V02S0101
|
|
arc: B5 V02S0501
|
|
arc: C5 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 H02W0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00R0000 F4
|
|
arc: LSR0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
word: SLICEC.K1.INIT 1110110010100000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C2:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 E1_H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C30:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A3 H01E0001
|
|
arc: A5 V02N0301
|
|
arc: A6 N1_V02S0301
|
|
arc: A7 V02N0101
|
|
arc: B3 V01N0001
|
|
arc: B5 H00L0000
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: C3 H02W0401
|
|
arc: C5 N1_V02S0201
|
|
arc: C6 V02N0201
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 N1_V02S0001
|
|
arc: D5 V02N0401
|
|
arc: D6 H00L0100
|
|
arc: D7 N1_V02S0601
|
|
arc: E3_H06E0103 Q1
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q6
|
|
arc: LSR1 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0501 Q7
|
|
arc: N3_V06N0303 Q5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F2
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1110110010100000
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
word: SLICEC.K1.INIT 1111100010001000
|
|
word: SLICED.K0.INIT 1010101110101000
|
|
word: SLICED.K1.INIT 1111000111100000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C31:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A1 V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A6 W1_H02E0701
|
|
arc: B1 N1_V02S0301
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B6 E1_H02W0301
|
|
arc: C1 S1_V02N0401
|
|
arc: C3 N1_V02S0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C6 V02N0001
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 V01N0001
|
|
arc: D6 V01N0001
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F2
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F6
|
|
arc: V00B0000 F4
|
|
arc: V00T0000 F0
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111100010001000
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110110010100000
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICEC.K0.INIT 0000011101110111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C32:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 N1_V02S0701
|
|
arc: A3 V00T0000
|
|
arc: A4 V02N0301
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 W1_H02E0101
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 V02N0501
|
|
arc: B7 N1_V02S0501
|
|
arc: C0 H02E0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V01N0101
|
|
arc: C7 H02E0401
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D3 H02E0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0101 F6
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0201 F2
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICED.K0.INIT 1111111111111111
|
|
word: SLICED.K1.INIT 1110110010100000
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111100010001000
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
word: SLICEA.K0.INIT 1111000011100010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C33:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A1 H02E0501
|
|
arc: A4 V02N0301
|
|
arc: A6 V02N0301
|
|
arc: B1 N1_V02S0101
|
|
arc: B4 E1_H02W0301
|
|
arc: B6 V00B0100
|
|
arc: C1 E1_H01W0000
|
|
arc: C4 V02N0001
|
|
arc: C6 V01N0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 W1_H02E0001
|
|
arc: D4 V01N0001
|
|
arc: D6 S1_V02N0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F0
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0601 F4
|
|
arc: N3_V06N0203 Q7
|
|
arc: V00B0000 F6
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111100010001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C34:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W3_H06W0103 V06N0103
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: B0 S1_V02N0101
|
|
arc: CE0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C35:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0003 V06N0003
|
|
arc: W3_H06W0103 V06N0103
|
|
arc: C0 S1_V02N0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q0
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q6
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C36:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: B0 V02N0101
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C37:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0100 H02W0101
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02W0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: A0 H00L0100
|
|
arc: A2 V02N0501
|
|
arc: B0 V00T0000
|
|
arc: B2 V02N0101
|
|
arc: C0 H00R0100
|
|
arc: C2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 V02N0001
|
|
arc: D3 V00T0100
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q0
|
|
arc: M2 V00B0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K0.INIT 0000111000001010
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
word: SLICEA.K0.INIT 0101000001010100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C38:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A2 V00B0000
|
|
arc: A7 N1_V02S0101
|
|
arc: B2 V02S0301
|
|
arc: B7 S1_V02N0501
|
|
arc: C2 H00L0100
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 Q2
|
|
arc: D7 V02N0401
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H01W0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0701 F7
|
|
arc: V00T0000 Q0
|
|
word: SLICED.K1.INIT 1000010000100001
|
|
word: SLICEB.K0.INIT 1101101111100111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C39:PLC2
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: W1_H02W0301 V02S0301
|
|
|
|
.tile R23C3:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00T0000 H02W0001
|
|
arc: A3 H00L0100
|
|
arc: B3 V02S0101
|
|
arc: C3 V02N0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H02E0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 E1_H02W0201
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M1 H02W0001
|
|
arc: M3 H00L0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 F3
|
|
arc: S1_V02S0301 Q1
|
|
arc: V01S0100 Q6
|
|
word: SLICEB.K1.INIT 0000101100001111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C40:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R23C41:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R23C43:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
|
|
.tile R23C44:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
|
|
.tile R23C47:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R23C4:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 E1_H02W0701
|
|
arc: A2 V02N0701
|
|
arc: A3 F7
|
|
arc: A5 Q5
|
|
arc: A7 F5
|
|
arc: B0 H01W0100
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0101
|
|
arc: B5 H02W0301
|
|
arc: B7 V01S0000
|
|
arc: C0 V02N0401
|
|
arc: C2 H02E0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 V02N0001
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: D2 Q2
|
|
arc: D3 F0
|
|
arc: D5 H02E0001
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q7
|
|
word: SLICEA.K0.INIT 1111001011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0001000000010011
|
|
word: SLICEC.K1.INIT 0000101100001111
|
|
word: SLICED.K1.INIT 0000000010001010
|
|
word: SLICEB.K1.INIT 1100100011111011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C5:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 F7
|
|
arc: A1 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 V02N0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 V02N0501
|
|
arc: B7 V00B0000
|
|
arc: C0 H02W0401
|
|
arc: C1 H00L0000
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 V02S0401
|
|
arc: C4 S1_V02N0001
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D1 W1_H02E0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 V02N0201
|
|
arc: D4 H02W0001
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0601 F4
|
|
arc: N3_V06N0103 F1
|
|
arc: N3_V06N0203 F4
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0601 F4
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0601 F4
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K1.INIT 0010000000000000
|
|
word: SLICEC.K0.INIT 0000100000000000
|
|
word: SLICEB.K1.INIT 1101110111010001
|
|
word: SLICEB.K0.INIT 1100110011001000
|
|
word: SLICED.K1.INIT 0101001100000000
|
|
word: SLICEA.K0.INIT 0100010100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R23C6:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 V01N0101
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 V02S0301
|
|
arc: A6 H00R0000
|
|
arc: A7 V02S0101
|
|
arc: B0 V00T0000
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 H00L0000
|
|
arc: B5 V02S0701
|
|
arc: B6 V00B0000
|
|
arc: B7 V02S0501
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0100 F6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C7:PLC2
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 V02S0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 V02S0301
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 V02S0101
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 W1_H02E0301
|
|
arc: B6 V00B0000
|
|
arc: B7 E1_H02W0301
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M3 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0100 F0
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C8:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H00R0000
|
|
arc: A1 V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A6 V02N0101
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0301
|
|
arc: B6 H02E0301
|
|
arc: C6 V02N0001
|
|
arc: D6 V02N0401
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F6
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 F2
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0100 F0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 1100111110001011
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R23C9:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0103 V06S0103
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: B0 H02W0301
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1100000000001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R24C10:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W3_H06W0103 N1_V01S0100
|
|
arc: B0 V00B0000
|
|
arc: C0 S1_V02N0601
|
|
arc: CE0 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C11:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A2 V02N0701
|
|
arc: A5 H02W0501
|
|
arc: B2 H00R0100
|
|
arc: B5 S1_V02N0501
|
|
arc: C2 W1_H02E0601
|
|
arc: C5 W1_H02E0601
|
|
arc: D2 W1_H02E0001
|
|
arc: D5 W1_H02E0001
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0103 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0303 F5
|
|
word: SLICEB.K0.INIT 0000100000000000
|
|
word: SLICEC.K1.INIT 0000010000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C12:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 F5
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 H00R0100
|
|
arc: B2 V02S0301
|
|
arc: B5 V01S0000
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 V02S0601
|
|
arc: C2 V02N0601
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 H02W0001
|
|
arc: D5 H02W0201
|
|
arc: D7 H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 F2
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 F0
|
|
arc: V01S0000 Q2
|
|
word: SLICEC.K1.INIT 0000000000110101
|
|
word: SLICED.K1.INIT 0010001100110011
|
|
word: SLICEA.K0.INIT 0100010000000100
|
|
word: SLICEB.K0.INIT 1100100011111011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C13:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A2 H00L0100
|
|
arc: A6 N1_V01N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 Q1
|
|
arc: B2 V02N0301
|
|
arc: B6 S1_V02N0701
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 N1_V01S0100
|
|
arc: C6 S1_V02N0001
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 H02E0201
|
|
arc: D2 F0
|
|
arc: D6 V02S0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q6
|
|
arc: V00B0000 F6
|
|
arc: W1_H02W0001 F2
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICED.K0.INIT 1011000000000000
|
|
word: SLICEB.K0.INIT 1101110011111111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R24C14:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0701 Q7
|
|
arc: M4 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C15:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 H02E0701
|
|
arc: A2 F5
|
|
arc: A3 V00B0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B2 V01N0001
|
|
arc: B3 Q3
|
|
arc: B5 V02N0501
|
|
arc: B7 F3
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 S1_V02N0401
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D2 H01E0101
|
|
arc: D3 W1_H02E0201
|
|
arc: D5 W1_H02E0201
|
|
arc: D7 V02S0601
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M5 H00L0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 F0
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEC.K1.INIT 0000000001010011
|
|
word: SLICEA.K0.INIT 0000000001010011
|
|
word: SLICEB.K1.INIT 0100010101010101
|
|
word: SLICED.K1.INIT 0000100000001100
|
|
word: SLICEB.K0.INIT 0100010000000100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C16:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C17:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 H01E0001
|
|
arc: A7 Q7
|
|
arc: B0 E1_H02W0301
|
|
arc: B3 Q3
|
|
arc: B7 H02E0301
|
|
arc: C0 V02S0401
|
|
arc: C2 H00R0100
|
|
arc: C3 N1_V01N0001
|
|
arc: C7 W1_H02E0401
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 W1_H02E0201
|
|
arc: D7 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H02E0201
|
|
arc: M5 H00L0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: V00B0100 F7
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICED.K1.INIT 1000110000000000
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R24C18:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N3_V06N0003 Q3
|
|
arc: S3_V06S0003 Q3
|
|
arc: V01S0000 Q2
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C19:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00T0000 V02N0601
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A3 H00L0100
|
|
arc: A4 F7
|
|
arc: A7 V02S0101
|
|
arc: B3 Q3
|
|
arc: B4 F3
|
|
arc: B7 V00B0100
|
|
arc: C3 N1_V02S0401
|
|
arc: C4 Q4
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V02S0001
|
|
arc: D4 V02S0601
|
|
arc: D7 V02S0401
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H00L0000
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0100 Q7
|
|
arc: W3_H06W0203 F4
|
|
word: SLICED.K1.INIT 1111000011100000
|
|
word: SLICEB.K1.INIT 0101001100000000
|
|
word: SLICEC.K0.INIT 0010000000100010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C20:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: B0 H01W0100
|
|
arc: B1 V00B0000
|
|
arc: C0 H00R0100
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R24C21:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 F7
|
|
arc: A2 F5
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 F3
|
|
arc: B3 H01W0100
|
|
arc: B4 V02N0501
|
|
arc: B5 V02S0701
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 F4
|
|
arc: C3 H00L0100
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 E1_H01E0101
|
|
arc: C7 W1_H02E0401
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 H01E0101
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 V01N0001
|
|
arc: D7 W1_H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F2
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICED.K1.INIT 0101001100000000
|
|
word: SLICEB.K1.INIT 1100110011001000
|
|
word: SLICEA.K0.INIT 0100010000000100
|
|
word: SLICEC.K0.INIT 0000110100001111
|
|
word: SLICEC.K1.INIT 1011000000000000
|
|
word: SLICEB.K0.INIT 0000010101010101
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R24C22:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 F5
|
|
arc: A3 H02E0701
|
|
arc: A4 H02E0701
|
|
arc: A5 V02N0101
|
|
arc: A6 H00L0000
|
|
arc: A7 Q7
|
|
arc: B0 H02E0301
|
|
arc: B1 Q1
|
|
arc: B2 F3
|
|
arc: B3 Q3
|
|
arc: B4 V01S0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 H02W0301
|
|
arc: B7 V02S0701
|
|
arc: C0 V02S0401
|
|
arc: C1 H00R0100
|
|
arc: C2 F4
|
|
arc: C3 V02S0601
|
|
arc: C4 V02N0001
|
|
arc: C5 V02S0201
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 H02E0601
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02E0001
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 N1_V02S0201
|
|
arc: D4 H02E0001
|
|
arc: D5 V02S0601
|
|
arc: D6 F2
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 F6
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEB.K1.INIT 0100010101010101
|
|
word: SLICEC.K0.INIT 1000000010100000
|
|
word: SLICEA.K0.INIT 0000000010110000
|
|
word: SLICEB.K0.INIT 0000001100001111
|
|
word: SLICED.K0.INIT 1010100011111101
|
|
word: SLICEC.K1.INIT 0000000001010011
|
|
word: SLICED.K1.INIT 0000101100001111
|
|
word: SLICEA.K1.INIT 0100000001010000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C23:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 W1_H02E0501
|
|
arc: A3 V02S0501
|
|
arc: A4 V00B0000
|
|
arc: B0 V00T0000
|
|
arc: B3 Q3
|
|
arc: B4 V00B0100
|
|
arc: C0 H02E0601
|
|
arc: C3 F4
|
|
arc: C4 H02E0401
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D3 F0
|
|
arc: D4 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: M0 H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEC.K0.INIT 0011010100000000
|
|
word: SLICEA.K0.INIT 1010101010101000
|
|
word: SLICEB.K1.INIT 0000110100000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C24:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N3_V06N0003 Q0
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C25:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 H02W0501
|
|
arc: A1 V02S0701
|
|
arc: A3 H02W0701
|
|
arc: A6 H02W0701
|
|
arc: B1 V02S0101
|
|
arc: B3 H02W0301
|
|
arc: B6 V02N0701
|
|
arc: C1 S1_V02N0601
|
|
arc: C3 H02E0401
|
|
arc: C6 H02W0401
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H01E0101
|
|
arc: D3 V02S0001
|
|
arc: D6 H02E0001
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: M4 E1_H01E0101
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0601 F6
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00T0000 F2
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110101011000000
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111100010001000
|
|
word: SLICED.K0.INIT 0000011101110111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C26:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A1 H02E0701
|
|
arc: A3 V02N0501
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 H02E0701
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 E1_H02W0701
|
|
arc: B1 H02E0101
|
|
arc: B3 V02S0301
|
|
arc: B4 H02W0101
|
|
arc: B5 V02S0501
|
|
arc: B6 H02W0101
|
|
arc: B7 V02N0701
|
|
arc: C1 V02S0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 H02E0401
|
|
arc: C6 H01E0001
|
|
arc: C7 H02E0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D3 H00R0000
|
|
arc: D4 V02N0601
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 V01N0001
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: LSR0 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M2 H02W0601
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F2
|
|
arc: V00B0000 F6
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110101011000000
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1110110010100000
|
|
word: SLICED.K1.INIT 0000011101110111
|
|
word: SLICEC.K0.INIT 0001010100111111
|
|
word: SLICEC.K1.INIT 0000011101110111
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C27:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: A1 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: A4 V02S0101
|
|
arc: A5 H02E0701
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 S1_V02N0101
|
|
arc: B1 N1_V02S0101
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 H00R0000
|
|
arc: B6 H02E0101
|
|
arc: B7 S1_V02N0701
|
|
arc: C1 E1_H02W0601
|
|
arc: C3 V02S0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 H02W0401
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 H02W0401
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00B0100
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V02N0401
|
|
arc: D5 V01N0001
|
|
arc: D6 V02N0401
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: LSR0 V00T0000
|
|
arc: M0 H02W0601
|
|
arc: M2 N1_V01N0001
|
|
arc: M5 V01S0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0501 Q7
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1110110010100000
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110101011000000
|
|
word: SLICEC.K1.INIT 0000011101110111
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 0001010100111111
|
|
word: SLICEC.K0.INIT 0001001101011111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C28:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A1 V02S0501
|
|
arc: A3 V00T0000
|
|
arc: A5 N1_V01N0101
|
|
arc: A6 N1_V01N0101
|
|
arc: B1 N1_V02S0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B5 H02E0301
|
|
arc: B6 E1_H02W0101
|
|
arc: C1 E1_H02W0401
|
|
arc: C3 H02W0601
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 V00T0100
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H00R0000
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 V01N0001
|
|
arc: D6 H02W0201
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 V01S0100
|
|
arc: M3 H00L0000
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N3_V06N0103 Q1
|
|
arc: V00B0000 F6
|
|
arc: V01S0100 F4
|
|
word: SLICEB.K1.INIT 0000011101110111
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110101011000000
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
word: SLICEC.K1.INIT 1110101011000000
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C29:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A1 W1_H02E0701
|
|
arc: A3 H02E0501
|
|
arc: A5 V02S0101
|
|
arc: A6 H02E0701
|
|
arc: A7 H00R0000
|
|
arc: B1 E1_H02W0301
|
|
arc: B3 H02W0101
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 H02W0101
|
|
arc: B7 H02W0101
|
|
arc: C1 H02W0601
|
|
arc: C3 H02E0401
|
|
arc: C5 H02W0401
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02S0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D5 H02E0201
|
|
arc: D6 V00B0000
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0401 F6
|
|
arc: V00B0100 F7
|
|
arc: V01S0100 F0
|
|
word: SLICED.K1.INIT 0001010100111111
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110110010100000
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
word: SLICEC.K1.INIT 1110110010100000
|
|
word: SLICEB.K1.INIT 0001001101011111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C2:PLC2
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: A0 V02S0701
|
|
arc: A2 S1_V02N0701
|
|
arc: A4 F7
|
|
arc: A7 Q7
|
|
arc: B0 V02S0101
|
|
arc: B2 H01W0100
|
|
arc: B4 H00L0000
|
|
arc: B7 V01S0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 H02E0601
|
|
arc: C4 Q4
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D2 S1_V02N0201
|
|
arc: D4 V02S0401
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 Q1
|
|
word: SLICED.K1.INIT 0101001100000000
|
|
word: SLICEB.K0.INIT 1111111000000000
|
|
word: SLICEC.K0.INIT 0100000001000100
|
|
word: SLICEA.K0.INIT 1111001011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R24C30:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0100 H02W0301
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A1 E1_H01E0001
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 H02E0501
|
|
arc: A7 V02S0301
|
|
arc: B1 V02N0101
|
|
arc: B4 H02W0301
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 E1_H02W0301
|
|
arc: C1 W1_H02E0401
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 W1_H02E0401
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 V00T0100
|
|
arc: CE0 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02E0201
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 H02E0001
|
|
arc: D6 E1_H02W0201
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: N3_V06N0203 Q7
|
|
arc: S3_V06S0203 F4
|
|
arc: V00B0100 F7
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0601 F4
|
|
arc: W3_H06W0203 F4
|
|
word: SLICED.K0.INIT 0001001101011111
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110101011000000
|
|
word: SLICED.K1.INIT 0001001101011111
|
|
word: SLICEC.K0.INIT 0000000000000011
|
|
word: SLICEC.K1.INIT 0000011101110111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C31:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A2 V00T0000
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 V00B0000
|
|
arc: A5 H02E0701
|
|
arc: A6 V02N0101
|
|
arc: A7 H00L0000
|
|
arc: B0 H02E0101
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 V02N0701
|
|
arc: B6 H01E0101
|
|
arc: B7 V02S0501
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F4
|
|
arc: LSR0 H02E0301
|
|
arc: M2 W1_H02E0601
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0201 Q2
|
|
arc: W1_H02W0001 F2
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C32:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 H02E0701
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 V02N0701
|
|
arc: A4 V02S0301
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 V02N0101
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B3 V02N0301
|
|
arc: B4 H02E0301
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0100
|
|
arc: B7 V00T0000
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F7
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0001 Q2
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 F4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C33:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 V01N0001
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A0 V02N0701
|
|
arc: A1 H00L0100
|
|
arc: A2 V02N0501
|
|
arc: A5 E1_H02W0701
|
|
arc: A7 V02N0101
|
|
arc: B0 V00T0000
|
|
arc: B1 H02E0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B6 E1_H02W0301
|
|
arc: CE0 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q5
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 H02W0301
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0101 Q1
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0701 F5
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0003 F3
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C34:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N3_V06N0003 H01E0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 V02N0701
|
|
arc: F0 F0_SLICE
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R24C35:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: B0 V01N0001
|
|
arc: B1 V01N0001
|
|
arc: C1 S1_V02N0601
|
|
arc: CE0 V02N0201
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 Q4
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEA.K1.INIT 1100000011000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C36:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02W0501
|
|
arc: C0 E1_H02W0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C37:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W3_H06W0203 E1_H02W0401
|
|
arc: A0 H00L0000
|
|
arc: A4 V02N0101
|
|
arc: A5 S1_V02N0101
|
|
arc: A7 V02N0301
|
|
arc: B0 N1_V02S0101
|
|
arc: B2 S1_V02N0301
|
|
arc: B5 V00B0100
|
|
arc: B6 V02N0701
|
|
arc: C0 V02N0401
|
|
arc: C1 H02W0601
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C4 V01N0101
|
|
arc: C5 V01N0101
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 V01S0100
|
|
arc: D2 V02N0201
|
|
arc: D3 H02E0001
|
|
arc: D4 F0
|
|
arc: D5 F0
|
|
arc: D6 F0
|
|
arc: D7 H00L0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0100 F7
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F7
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0401 F4
|
|
word: SLICEA.K0.INIT 0001010101000101
|
|
word: SLICEB.K0.INIT 1111000000110000
|
|
word: SLICED.K1.INIT 0000101000000000
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICED.K0.INIT 1111001100000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0000101000000000
|
|
word: SLICEC.K1.INIT 1010110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C38:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 V02N0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A5 Q5
|
|
arc: A6 H00L0000
|
|
arc: A7 V00T0100
|
|
arc: B2 V02S0301
|
|
arc: B4 H00R0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F4
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M2 N1_V01N0001
|
|
arc: M3 H01W0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0401 F6
|
|
arc: V00B0000 Q6
|
|
arc: V00T0100 Q3
|
|
word: SLICED.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C39:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 V02N0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: A1 H00L0100
|
|
arc: A5 V00T0100
|
|
arc: A6 V02S0301
|
|
arc: B0 V00T0000
|
|
arc: B5 H01E0101
|
|
arc: B6 H02W0101
|
|
arc: C5 H02W0601
|
|
arc: C6 H01E0001
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 H02E0201
|
|
arc: D6 F0
|
|
arc: E1_H01E0001 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 F6
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02E0601
|
|
arc: M3 H02W0201
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0701 F5
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 F1
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0101010101011010
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICED.K0.INIT 1000010000100001
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C3:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 H02W0301
|
|
arc: A2 V02N0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 V02S0301
|
|
arc: A7 S1_V02N0301
|
|
arc: B1 Q1
|
|
arc: B2 V02S0101
|
|
arc: B3 Q3
|
|
arc: B4 F3
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 F4
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 E1_H01E0101
|
|
arc: C7 W1_H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 H01E0101
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 V00B0000
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 H00L0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K1.INIT 0000010100010001
|
|
word: SLICED.K1.INIT 0011001100010011
|
|
word: SLICEC.K0.INIT 0010000000110000
|
|
word: SLICEB.K0.INIT 1100100011111011
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C40:PLC2
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
|
|
.tile R24C41:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R24C44:PLC2
|
|
arc: N1_V02N0201 H06E0103
|
|
|
|
.tile R24C4:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q6
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C5:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: B1 Q1
|
|
arc: C0 H00R0100
|
|
arc: C1 S1_V02N0401
|
|
arc: CE0 V02S0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 V00B0100
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0000
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111110000001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R24C6:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H00L0100
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0501
|
|
arc: A3 V02N0501
|
|
arc: A4 V02S0301
|
|
arc: A6 S1_V02N0301
|
|
arc: B0 V02S0301
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0301
|
|
arc: B3 Q3
|
|
arc: B4 E1_H02W0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: C3 F4
|
|
arc: C4 Q4
|
|
arc: C6 E1_H02W0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V02S0001
|
|
arc: D2 V02S0001
|
|
arc: D3 F0
|
|
arc: D4 V02S0601
|
|
arc: D6 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F2
|
|
arc: M0 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F6
|
|
arc: N3_V06N0103 F1
|
|
arc: V00B0000 Q6
|
|
arc: W1_H02W0201 F2
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0010000000000000
|
|
word: SLICED.K0.INIT 0101010100010101
|
|
word: SLICEC.K0.INIT 0000100000101010
|
|
word: SLICEA.K0.INIT 1010101010101000
|
|
word: SLICEB.K1.INIT 0000110100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C7:PLC2
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A2 V00B0000
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 H00L0000
|
|
arc: A7 E1_H02W0701
|
|
arc: B2 H00R0000
|
|
arc: B3 Q3
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 H02W0301
|
|
arc: B7 H02W0301
|
|
arc: C5 V00T0000
|
|
arc: C6 H02E0601
|
|
arc: C7 V00T0000
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 V02N0601
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F6
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F7
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 W1_H02E0401
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F5
|
|
arc: N3_V06N0203 F7
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0401 F6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K1.INIT 0000000010000000
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 0000000010000000
|
|
word: SLICEB.K0.INIT 1010101011001100
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R24C8:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A2 V00T0000
|
|
arc: A6 V02N0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B6 V02S0501
|
|
arc: C2 H02E0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 Q2
|
|
arc: D6 W1_H02E0201
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: E3_H06E0303 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F6
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V00T0000 Q0
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEB.K0.INIT 0000010000000111
|
|
word: SLICED.K0.INIT 0000000010001000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R24C9:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: B0 V00T0000
|
|
arc: B7 V00T0000
|
|
arc: C0 H00R0100
|
|
arc: C7 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 F7
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0011000011111100
|
|
word: SLICED.K1.INIT 1111001111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R25C10:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A2 V00B0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V02N0101
|
|
arc: C0 H02E0601
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W1_H02W0101 Q1
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1111101001010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R25C11:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: A2 E1_H01E0001
|
|
arc: A4 H02W0701
|
|
arc: A5 H02W0701
|
|
arc: A6 H02W0701
|
|
arc: A7 Q7
|
|
arc: B1 Q1
|
|
arc: B4 V02N0501
|
|
arc: B5 H02W0101
|
|
arc: B6 V02N0501
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0100
|
|
arc: C2 E1_H01W0000
|
|
arc: C4 V00T0000
|
|
arc: C5 E1_H01E0101
|
|
arc: C6 V00T0000
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V01S0100
|
|
arc: D4 F2
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 F2
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F7
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M3 H00L0000
|
|
arc: M5 H02W0001
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0201 F2
|
|
arc: W3_H06W0103 F2
|
|
word: SLICED.K0.INIT 0000100000000000
|
|
word: SLICEC.K0.INIT 0000010000000000
|
|
word: SLICEC.K1.INIT 0000000010000000
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICED.K1.INIT 0010001100000000
|
|
word: SLICEB.K0.INIT 0000101000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R25C12:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 H02W0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0501
|
|
arc: A5 N1_V02S0101
|
|
arc: A6 V00T0100
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 N1_V02S0101
|
|
arc: B5 V00B0100
|
|
arc: B6 V00B0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 H00L0100
|
|
arc: C3 H02E0601
|
|
arc: C5 H02E0601
|
|
arc: C6 V00B0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02E0001
|
|
arc: D3 H02W0201
|
|
arc: D5 H02W0201
|
|
arc: D6 H02W0201
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F6
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0401 F6
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 F6
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0303 F6
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K1.INIT 0000000000100000
|
|
word: SLICED.K0.INIT 0000000000001000
|
|
word: SLICEB.K1.INIT 0000000010000000
|
|
word: SLICEA.K1.INIT 0101000001010000
|
|
word: SLICEB.K0.INIT 0000010000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R25C13:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 V02N0201
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A0 V01N0101
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0501
|
|
arc: A5 H02W0501
|
|
arc: A6 H00R0000
|
|
arc: B0 E1_H02W0101
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 V02N0301
|
|
arc: B5 H00L0000
|
|
arc: B6 S1_V02N0701
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 H02E0401
|
|
arc: C5 H02E0401
|
|
arc: C6 V00T0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 Q2
|
|
arc: D3 V02N0201
|
|
arc: D5 V02N0401
|
|
arc: D6 F2
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 F6
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0303 F5
|
|
arc: V00T0000 F0
|
|
arc: V01S0000 F5
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEC.K1.INIT 0010000000000000
|
|
word: SLICEB.K1.INIT 0000000010000000
|
|
word: SLICEB.K0.INIT 0000000100001101
|
|
word: SLICEA.K0.INIT 1010101000101010
|
|
word: SLICED.K0.INIT 0000000010110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R25C14:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: B1 Q1
|
|
arc: C0 H00R0100
|
|
arc: C1 H00L0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F0
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M5 W1_H02E0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R25C15:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 H02E0501
|
|
arc: A6 V02N0101
|
|
arc: A7 N1_V01N0101
|
|
arc: B0 W1_H02E0301
|
|
arc: B6 V00B0000
|
|
arc: B7 V02N0701
|
|
arc: C0 H00R0100
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 N1_V02S0001
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 E1_H02W0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0501 Q5
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111110011111010
|
|
word: SLICED.K0.INIT 1101111100000000
|
|
word: SLICED.K1.INIT 0000000011001110
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R25C16:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0100 H02W0501
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 H00L0000
|
|
arc: A2 E1_H01E0001
|
|
arc: A4 F5
|
|
arc: A5 N1_V01N0101
|
|
arc: B0 V02N0301
|
|
arc: B2 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 H02E0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 V02N0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V00T0100
|
|
arc: CE0 V02N0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 S1_V02N0201
|
|
arc: D4 F2
|
|
arc: D5 S1_V02N0401
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: M0 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: V00B0000 F4
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F0
|
|
word: SLICEB.K0.INIT 1100110011001000
|
|
word: SLICEC.K1.INIT 0100011100000000
|
|
word: SLICEC.K0.INIT 0100010100000000
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C17:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: B1 Q1
|
|
arc: C0 W1_H02E0401
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H02E0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0201 F0
|
|
arc: V01S0100 Q5
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R25C18:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A3 V02S0501
|
|
arc: A7 Q7
|
|
arc: B3 Q3
|
|
arc: B7 V02S0501
|
|
arc: C3 H02W0401
|
|
arc: C7 H02W0401
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V02S0001
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H02E0301 F3
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: M3 H00L0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
word: SLICEB.K1.INIT 0100010101010101
|
|
word: SLICED.K1.INIT 0010001100110011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R25C19:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 S1_V02N0701
|
|
arc: A4 N1_V01N0101
|
|
arc: B0 V00B0000
|
|
arc: B2 H01W0100
|
|
arc: B4 S1_V02N0501
|
|
arc: C0 H00L0100
|
|
arc: C2 H02E0401
|
|
arc: C4 E1_H01E0101
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 N1_V02S0001
|
|
arc: D4 F2
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEB.K0.INIT 0000110100001111
|
|
word: SLICEA.K0.INIT 0000000100001011
|
|
word: SLICEC.K0.INIT 0000101100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R25C20:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A3 V02S0701
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: B0 V00B0000
|
|
arc: B3 Q3
|
|
arc: B5 V02S0701
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 W1_H02E0601
|
|
arc: C5 H02E0401
|
|
arc: C6 E1_H01E0101
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V02S0201
|
|
arc: D3 V02N0001
|
|
arc: D5 H02E0001
|
|
arc: D6 F0
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: V00B0000 Q6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111111110000
|
|
word: SLICEC.K1.INIT 0010001100110011
|
|
word: SLICEB.K1.INIT 1000101000000000
|
|
word: SLICED.K0.INIT 0000010100001111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R25C21:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 H02W0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: B1 V00B0000
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0100
|
|
arc: C2 W1_H02E0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 W1_H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0201 F0
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R25C22:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: A0 H02E0501
|
|
arc: B0 H01W0100
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00T0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 F0
|
|
word: SLICEA.K0.INIT 1111001011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R25C23:PLC2
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: V01S0100 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C24:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A7 N1_V02S0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D7 V02S0601
|
|
arc: E3_H06E0003 Q0
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 Q0
|
|
word: SLICED.K1.INIT 1111111101010101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C25:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0100 H02E0101
|
|
arc: A1 V02S0701
|
|
arc: B1 N1_V02S0301
|
|
arc: B3 V01N0001
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 V02N0401
|
|
arc: C4 V01N0101
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H00R0000
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 E1_H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 E1_H02W0601
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q7
|
|
arc: N3_V06N0203 Q4
|
|
arc: S1_V02S0301 Q3
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1110110010100000
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C26:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A2 H02W0501
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 H02E0501
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B2 V02N0101
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 V01S0000
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V00B0000
|
|
arc: B7 H01E0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F6
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 H02W0401
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F7
|
|
arc: N1_V02N0601 F4
|
|
arc: N1_V02N0701 F5
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C27:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0000
|
|
arc: A2 V01N0101
|
|
arc: A3 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0301
|
|
arc: B4 V01S0000
|
|
arc: B6 V00B0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 F2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M2 H02E0601
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F5
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F3
|
|
word: SLICED.K1.INIT 1010101010101010
|
|
word: SLICED.K0.INIT 1100110011001100
|
|
word: SLICEC.K1.INIT 1010101010101010
|
|
word: SLICEC.K0.INIT 1100110011001100
|
|
word: SLICEB.K1.INIT 1010101010101010
|
|
word: SLICEB.K0.INIT 1010101010101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C28:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: B4 V01S0000
|
|
arc: B6 V02N0701
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 1010101010101010
|
|
word: SLICED.K0.INIT 1100110011001100
|
|
word: SLICEC.K1.INIT 1010101010101010
|
|
word: SLICEC.K0.INIT 1100110011001100
|
|
word: SLICEB.K1.INIT 1100110011001100
|
|
word: SLICEB.K0.INIT 1010101010101010
|
|
word: SLICEA.K1.INIT 1100110011001100
|
|
word: SLICEA.K0.INIT 1100110011001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C29:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: B0 V00T0000
|
|
arc: C6 S1_V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 E1_H02W0001
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F0
|
|
arc: N3_V06N0303 F6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F6
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1100110011001100
|
|
word: SLICED.K0.INIT 0000111100000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C2:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0501 Q5
|
|
arc: V01S0000 Q2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C30:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 H02E0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0100
|
|
arc: A6 V02N0301
|
|
arc: A7 H00L0000
|
|
arc: B0 H02E0301
|
|
arc: B2 H00R0000
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0701
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F3
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0201 F2
|
|
word: SLICED.K1.INIT 1001100110011010
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011010
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R25C31:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A0 H00L0000
|
|
arc: A1 H02W0701
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 H02E0501
|
|
arc: A4 V00B0000
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 H00R0000
|
|
arc: A7 V02N0301
|
|
arc: B0 V00T0000
|
|
arc: B1 H02E0101
|
|
arc: B2 V02N0101
|
|
arc: B3 H02W0301
|
|
arc: B4 V02N0701
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02N0501
|
|
arc: B7 E1_H02W0301
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F4
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F0
|
|
word: SLICED.K1.INIT 1001100110011010
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICEC.K1.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011010
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R25C32:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 V02N0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A4 V00T0100
|
|
arc: A5 W1_H02E0701
|
|
arc: B0 H02W0101
|
|
arc: B1 V00B0000
|
|
arc: B5 H00L0000
|
|
arc: C4 V02N0201
|
|
arc: C5 V00B0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02E0201
|
|
arc: D5 H00R0100
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00T0000
|
|
arc: M3 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F1
|
|
arc: S3_V06S0103 F2
|
|
arc: V00T0100 Q3
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
word: SLICEC.K1.INIT 0001010100111111
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C33:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A1 F5
|
|
arc: A2 V00B0000
|
|
arc: B1 E1_H02W0101
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C5 E1_H01E0101
|
|
arc: D1 V00B0100
|
|
arc: D2 V00T0100
|
|
arc: D5 H00R0100
|
|
arc: E1_H02E0001 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 H02W0601
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0103 F2
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEC.K1.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111110110101000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R25C34:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 H00R0000
|
|
arc: B0 E1_H02W0301
|
|
arc: C0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0011000100110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R25C35:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W3_H06W0103 V01N0101
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
arc: A1 E1_H01E0001
|
|
arc: B0 H02W0301
|
|
arc: B1 H02W0301
|
|
arc: C0 H00R0100
|
|
arc: C1 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 V00T0100
|
|
arc: E1_H01E0001 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00R0100 Q5
|
|
arc: M0 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0303 Q5
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 0011001100110000
|
|
word: SLICEA.K1.INIT 0011000000110010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C36:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: C0 V02N0401
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C37:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00B0100 V02S0101
|
|
arc: A0 F5
|
|
arc: A1 H00L0100
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 N1_V01N0101
|
|
arc: B0 H02W0101
|
|
arc: B1 F3
|
|
arc: B3 H02W0101
|
|
arc: B5 V00B0100
|
|
arc: C0 H00R0100
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 F4
|
|
arc: C4 V02N0001
|
|
arc: C5 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 N1_V01S0000
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02S0401
|
|
arc: D5 V01N0001
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q1
|
|
arc: N3_V06N0103 Q1
|
|
arc: S1_V02S0601 F4
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K1.INIT 1111111110111010
|
|
word: SLICEA.K0.INIT 0011001000100010
|
|
word: SLICEC.K1.INIT 1000000000100000
|
|
word: SLICEC.K0.INIT 0000101010100000
|
|
word: SLICEB.K1.INIT 1100111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C38:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: A0 N1_V02S0701
|
|
arc: B0 V02S0101
|
|
arc: C0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 F0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 0000000010000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C39:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R25C3:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: B1 Q1
|
|
arc: C0 H00R0100
|
|
arc: C1 V02N0401
|
|
arc: CE0 H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 H00R0000
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H00R0100 Q7
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0100 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C44:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R25C4:PLC2
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: A0 E1_H02W0701
|
|
arc: A4 F7
|
|
arc: A7 Q7
|
|
arc: B0 V02N0101
|
|
arc: B4 S1_V02N0701
|
|
arc: B7 H02E0101
|
|
arc: C0 H00L0000
|
|
arc: C4 Q4
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D4 F0
|
|
arc: D7 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 F4
|
|
arc: M0 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0100 Q3
|
|
word: SLICED.K1.INIT 0000110001000100
|
|
word: SLICEA.K0.INIT 1100110011001000
|
|
word: SLICEC.K0.INIT 0101000100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R25C5:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A4 V02N0301
|
|
arc: B1 Q1
|
|
arc: B4 N1_V01S0000
|
|
arc: C0 V02N0401
|
|
arc: C1 H00L0000
|
|
arc: C4 Q4
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0201
|
|
arc: D4 H02W0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M4 W1_H02E0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEC.K0.INIT 1000000010001000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R25C6:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A0 H00L0100
|
|
arc: A7 H00L0000
|
|
arc: B0 V02N0301
|
|
arc: B7 H02E0301
|
|
arc: C0 S1_V02N0401
|
|
arc: C7 V02N0201
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 F7
|
|
arc: M0 H01E0001
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: S3_V06S0203 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R25C7:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 H02W0701
|
|
arc: A2 H00L0100
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 F7
|
|
arc: A6 H02W0701
|
|
arc: A7 Q7
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 V01S0000
|
|
arc: B5 V00B0100
|
|
arc: B6 V02N0701
|
|
arc: B7 V00T0000
|
|
arc: C0 V02N0401
|
|
arc: C1 H02E0401
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 Q4
|
|
arc: C5 E1_H01E0101
|
|
arc: C6 H02E0401
|
|
arc: C7 F4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 V02S0001
|
|
arc: D3 V02N0001
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 H02E0001
|
|
arc: D6 E1_H02W0201
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F6
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: S3_V06S0103 F1
|
|
arc: V00T0000 F0
|
|
arc: V01S0000 Q2
|
|
arc: W3_H06W0103 F1
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 0000000011110111
|
|
word: SLICEC.K0.INIT 0000010100010001
|
|
word: SLICEA.K0.INIT 1100110001001100
|
|
word: SLICED.K1.INIT 0000100000001100
|
|
word: SLICEB.K0.INIT 0000000010001010
|
|
word: SLICEC.K1.INIT 1100100011111011
|
|
word: SLICEA.K1.INIT 0100000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R25C8:PLC2
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 V01N0101
|
|
arc: A5 E1_H02W0501
|
|
arc: B0 V01N0001
|
|
arc: B2 S1_V02N0101
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 V02N0501
|
|
arc: C0 V02N0601
|
|
arc: C2 H00L0000
|
|
arc: C5 V00T0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 H02E0201
|
|
arc: D4 N1_V02S0401
|
|
arc: D5 H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0601 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEC.K1.INIT 0010000000000000
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1111111110101010
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R25C9:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: A2 F7
|
|
arc: A4 V02N0101
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B4 S1_V02N0501
|
|
arc: B7 V02N0501
|
|
arc: C0 S1_V02N0601
|
|
arc: C2 F4
|
|
arc: C4 V01N0101
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 H01E0101
|
|
arc: D4 W1_H02E0001
|
|
arc: D7 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M2 H02W0601
|
|
arc: M5 H00L0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICED.K1.INIT 1011000000000000
|
|
word: SLICEC.K0.INIT 0101000101010101
|
|
word: SLICEB.K0.INIT 0000010101010101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C10:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 V02N0701
|
|
arc: A1 H00L0000
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0101
|
|
arc: B6 E1_H02W0301
|
|
arc: C6 V02N0001
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q6
|
|
arc: V01S0100 F0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 1111001111000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R26C11:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: A0 H01E0001
|
|
arc: A1 W1_H02E0501
|
|
arc: A6 H02W0701
|
|
arc: A7 H02W0701
|
|
arc: B0 H02W0301
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 N1_V02S0501
|
|
arc: C1 H00L0000
|
|
arc: C2 W1_H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C6 W1_H02E0601
|
|
arc: C7 W1_H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0201
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 W1_H02E0201
|
|
arc: D6 N1_V02S0601
|
|
arc: D7 N1_V02S0601
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 F6
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0101 F6
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1111101000001010
|
|
word: SLICEB.K1.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 0010000000000000
|
|
word: SLICED.K0.INIT 0001000000000000
|
|
word: SLICEA.K0.INIT 1110111000100010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R26C12:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0303 V06N0303
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 V06N0303
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: A7 Q7
|
|
arc: B1 Q1
|
|
arc: B2 V02S0301
|
|
arc: B5 H00L0000
|
|
arc: B6 H02W0301
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H00L0100
|
|
arc: C2 V02N0601
|
|
arc: C5 V01N0101
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02W0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 F0
|
|
arc: D5 V02N0401
|
|
arc: D6 F2
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 F6
|
|
arc: M0 V00B0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 W1_H02E0001
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1011101011111111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0010000000110000
|
|
word: SLICED.K1.INIT 1011000000000000
|
|
word: SLICED.K0.INIT 1100100011111011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R26C13:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 V00T0100
|
|
arc: A5 V00T0100
|
|
arc: A6 V00T0100
|
|
arc: A7 V00T0100
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0101
|
|
arc: B4 H02W0301
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 H02W0301
|
|
arc: C0 V02N0401
|
|
arc: C1 V02S0401
|
|
arc: C2 H02E0601
|
|
arc: C3 V02S0401
|
|
arc: C4 V00B0100
|
|
arc: C5 V00B0100
|
|
arc: C6 V00B0100
|
|
arc: C7 V00B0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00B0100
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 V00B0100
|
|
arc: D4 V02S0401
|
|
arc: D5 V02S0401
|
|
arc: D6 V02S0601
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F4
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F6
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 F7
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 0100000000000000
|
|
word: SLICEC.K0.INIT 0000000001000000
|
|
word: SLICEB.K1.INIT 0010000000000000
|
|
word: SLICEA.K0.INIT 0011111111000000
|
|
word: SLICEC.K1.INIT 0000000001000000
|
|
word: SLICED.K0.INIT 0100000000000000
|
|
word: SLICEA.K1.INIT 0000001000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C14:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A6 V02S0301
|
|
arc: B2 H02W0301
|
|
arc: B6 H02E0101
|
|
arc: C2 V02N0601
|
|
arc: C6 V00T0100
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 W1_H02E0001
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0601 F6
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICED.K0.INIT 0000010000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C15:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 V01N0101
|
|
arc: A2 V01N0101
|
|
arc: B0 V01N0001
|
|
arc: B2 V02N0301
|
|
arc: C0 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D2 S1_V02N0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEA.K0.INIT 0100010101000100
|
|
word: SLICEB.K0.INIT 0101010100000100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C16:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A3 V02N0501
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: B1 Q1
|
|
arc: B3 H02E0101
|
|
arc: B5 V02N0701
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0000
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 V00T0100
|
|
arc: C6 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 V02N0001
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 V02N0601
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 F6
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0001 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 0010000000110000
|
|
word: SLICEC.K1.INIT 1011000000000000
|
|
word: SLICED.K0.INIT 1111101000110011
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C17:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: A0 H00L0100
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 F0
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M3 H00L0000
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C18:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H00L0000
|
|
arc: A5 F7
|
|
arc: A7 Q7
|
|
arc: B0 H02W0301
|
|
arc: B5 V00B0100
|
|
arc: B7 V00T0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C5 V02N0201
|
|
arc: C7 V02N0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D5 F0
|
|
arc: D7 S1_V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 1100110011001000
|
|
word: SLICED.K1.INIT 0011000001010000
|
|
word: SLICEC.K1.INIT 0100010100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C19:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00B0000 H02W0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 V02N0701
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 F7
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 V02N0101
|
|
arc: A7 V02N0301
|
|
arc: B0 V02N0301
|
|
arc: B2 H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 V01S0000
|
|
arc: B5 F3
|
|
arc: B7 V00B0100
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 F4
|
|
arc: C3 H02E0601
|
|
arc: C4 V02N0001
|
|
arc: C5 V00T0000
|
|
arc: C7 V01N0101
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 H02E0001
|
|
arc: D3 V02S0201
|
|
arc: D4 V02N0401
|
|
arc: D5 V01N0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 H02W0601
|
|
arc: M2 H02W0601
|
|
arc: M4 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0303 F5
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q4
|
|
word: SLICEC.K0.INIT 0011000001010000
|
|
word: SLICEA.K0.INIT 1111000011100000
|
|
word: SLICED.K1.INIT 0000010100010001
|
|
word: SLICEB.K1.INIT 0100010100000000
|
|
word: SLICEB.K0.INIT 0000100000001010
|
|
word: SLICEC.K1.INIT 1010100011111101
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C20:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: B0 V00B0000
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V00T0100
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q7
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0001 F0
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q1
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEA.K1.INIT 1111111100001111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R26C21:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A2 F5
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: B2 H00L0000
|
|
arc: B4 V02N0701
|
|
arc: B5 V01S0000
|
|
arc: C2 F4
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 W1_H02E0401
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0001
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 W1_H02E0001
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q1
|
|
word: SLICEC.K1.INIT 0011010100000000
|
|
word: SLICEC.K0.INIT 1100110011001000
|
|
word: SLICEB.K0.INIT 0100000001010000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R26C22:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A2 V02N0701
|
|
arc: A4 V02N0101
|
|
arc: B1 Q1
|
|
arc: B2 V02N0301
|
|
arc: B4 V01S0000
|
|
arc: B6 V00T0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H00L0100
|
|
arc: C2 V02N0601
|
|
arc: C4 V01N0101
|
|
arc: C6 F4
|
|
arc: CE0 H00L0000
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 Q2
|
|
arc: D4 H02E0201
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M4 H02W0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0001 F0
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEB.K0.INIT 0101010100010101
|
|
word: SLICEC.K0.INIT 1000000010100000
|
|
word: SLICED.K0.INIT 0000001100001111
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R26C23:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 H00R0000
|
|
arc: A2 H02E0501
|
|
arc: A4 V02N0301
|
|
arc: A6 N1_V01N0101
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B4 V02N0701
|
|
arc: B6 H02W0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 V02N0401
|
|
arc: C2 V02N0601
|
|
arc: C4 V02N0201
|
|
arc: C6 F4
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 H02E0001
|
|
arc: D4 H02E0201
|
|
arc: D6 F2
|
|
arc: E1_H01E0001 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 F0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q6
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEA.K1.INIT 1111110011111100
|
|
word: SLICEC.K0.INIT 1100110011001000
|
|
word: SLICEB.K0.INIT 0101001100000000
|
|
word: SLICED.K0.INIT 0000000010110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R26C24:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: A0 H00R0000
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0601
|
|
arc: CE0 H00L0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V01S0100
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0100 Q5
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
word: SLICEA.K1.INIT 1111111111110000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R26C25:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A2 V02S0501
|
|
arc: A4 V00T0000
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 V02S0301
|
|
arc: B0 V02S0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B5 N1_V01S0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F4
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0401 F6
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R26C26:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: A7 V02N0101
|
|
arc: B2 F3
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 F3
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 E1_H02W0301
|
|
arc: C4 H01E0001
|
|
arc: C5 H02W0601
|
|
arc: C6 H02W0601
|
|
arc: C7 S1_V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H01E0101
|
|
arc: D3 H02E0201
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0203 F7
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0001 Q2
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEC.K1.INIT 0000001100000000
|
|
word: SLICED.K1.INIT 1010000000000000
|
|
word: SLICEB.K0.INIT 1100110000000000
|
|
word: SLICEC.K0.INIT 1100000011000000
|
|
word: SLICEB.K1.INIT 0000000011001100
|
|
word: SLICED.K0.INIT 0011000000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C27:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: B6 V02N0701
|
|
arc: C6 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 V02N0401
|
|
arc: E1_H01E0001 F6
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F6
|
|
arc: LSR1 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0601 F6
|
|
word: SLICED.K0.INIT 0000001100000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C28:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0100 H02W0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 V02S0501
|
|
arc: A1 V02N0501
|
|
arc: A3 V01N0101
|
|
arc: B0 H01W0100
|
|
arc: B1 V02N0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B6 V02S0501
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C3 V02N0601
|
|
arc: C4 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D3 V02S0201
|
|
arc: D4 V02N0601
|
|
arc: D6 N1_V02S0401
|
|
arc: E1_H01E0001 F1
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F4
|
|
arc: LSR0 H02W0301
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0301 F1
|
|
arc: V00B0000 F6
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K1.INIT 0001000000010000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000011010101
|
|
word: SLICEC.K0.INIT 0011000000000000
|
|
word: SLICEA.K0.INIT 1111110111111100
|
|
word: SLICED.K0.INIT 0000000011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R26C29:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 H02W0501
|
|
arc: A3 V00B0000
|
|
arc: B0 V02N0301
|
|
arc: C3 V02N0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D3 N1_V01S0000
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEA.K0.INIT 1100110010001000
|
|
word: SLICEB.K1.INIT 1010111110101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R26C2:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: C1 H00R0100
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 H02W0201
|
|
arc: D3 V02N0001
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 F3
|
|
arc: M0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C30:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0000 V02N0201
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A0 V02S0501
|
|
arc: B4 V02S0501
|
|
arc: C0 S1_V02N0401
|
|
arc: C4 V01N0101
|
|
arc: CE0 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D4 S1_V02N0401
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 Q0
|
|
arc: S1_V02S0601 Q4
|
|
word: SLICEC.K0.INIT 1111000011000000
|
|
word: SLICEA.K0.INIT 1111101000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C31:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 H02E0301
|
|
arc: A2 V00T0000
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 H02W0501
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 Q7
|
|
arc: B0 V02S0301
|
|
arc: B2 H02W0301
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V01S0000
|
|
arc: B6 H02W0101
|
|
arc: B7 S1_V02N0701
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 F3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F7
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 Q6
|
|
arc: N3_V06N0303 F5
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q5
|
|
arc: W1_H02W0401 F4
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICEC.K1.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C32:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 N3_V06S0303
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00L0100
|
|
arc: A2 H02W0501
|
|
arc: A3 V00B0000
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 V01S0000
|
|
arc: B5 H00L0000
|
|
arc: B6 H02W0301
|
|
arc: B7 V00T0000
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H02E0201
|
|
arc: M4 H02E0401
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0401 F6
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 1001100110011010
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEA.K0.INIT 1001100110011100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C33:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 H00L0000
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V02N0101
|
|
arc: A6 V02N0301
|
|
arc: A7 H02W0501
|
|
arc: B0 H01W0100
|
|
arc: B1 H02W0301
|
|
arc: B4 H02E0101
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0100
|
|
arc: B7 H02E0101
|
|
arc: C4 V02N0001
|
|
arc: C5 V01N0101
|
|
arc: C6 H02E0601
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V01N0001
|
|
arc: D5 H02E0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 H02W0401
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 F0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
word: SLICED.K1.INIT 1000110010101111
|
|
word: SLICEC.K0.INIT 1010001011110011
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICED.K0.INIT 1000010010000100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R26C34:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 V06N0003
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0203 E1_H02W0401
|
|
arc: A4 V00B0000
|
|
arc: A5 V00T0000
|
|
arc: A6 H00R0000
|
|
arc: B2 E1_H02W0301
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0501
|
|
arc: C0 E1_H02W0401
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V02N0001
|
|
arc: C6 H02E0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 V02S0001
|
|
arc: D4 V01N0001
|
|
arc: D5 V02N0401
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0601 F6
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEC.K1.INIT 0000000001001111
|
|
word: SLICEC.K0.INIT 1101000011011101
|
|
word: SLICED.K0.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1100110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C35:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E3_H06E0203 V06N0203
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: B1 V02S0301
|
|
arc: C0 V02N0601
|
|
arc: C2 S1_V02N0601
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 H02E0201
|
|
arc: D2 V02S0001
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q1
|
|
arc: N3_V06N0103 Q1
|
|
arc: V01S0000 Q6
|
|
arc: W1_H02W0001 Q2
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C36:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A0 S1_V02N0501
|
|
arc: A4 V02S0301
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 V02S0401
|
|
arc: C4 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D4 V00B0000
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR0 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: S1_V02S0001 F0
|
|
arc: S3_V06S0003 Q0
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEC.K0.INIT 1010111111111111
|
|
word: SLICEA.K0.INIT 0011010111001010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R26C37:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A2 V01N0101
|
|
arc: B2 E1_H02W0101
|
|
arc: C0 V02S0401
|
|
arc: C2 V02S0401
|
|
arc: CE0 H02W0101
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 H02E0001
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
word: SLICEB.K0.INIT 1100101001000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C38:PLC2
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R26C39:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
|
|
.tile R26C3:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0000 V02S0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: A0 H00L0000
|
|
arc: A2 E1_H01E0001
|
|
arc: B0 E1_H02W0101
|
|
arc: B2 E1_H02W0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 H01E0101
|
|
arc: E1_H01E0001 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0000
|
|
arc: M2 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 F2
|
|
arc: V00T0000 F0
|
|
word: SLICEA.K0.INIT 1000000011000000
|
|
word: SLICEB.K0.INIT 1101110011111111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C44:PLC2
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
|
|
.tile R26C4:PLC2
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: A3 E1_H02W0701
|
|
arc: A7 N1_V01N0101
|
|
arc: B3 Q3
|
|
arc: B7 F3
|
|
arc: C3 H02W0601
|
|
arc: C7 V02N0001
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 S1_V02N0201
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0101 F7
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M3 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
word: SLICEB.K1.INIT 1111000011100000
|
|
word: SLICED.K1.INIT 0000100000001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C5:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: B0 H02W0101
|
|
arc: C0 E1_H01W0000
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C6:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 V06N0203
|
|
arc: A0 H00R0000
|
|
arc: A2 H00L0100
|
|
arc: A3 H02W0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V00B0000
|
|
arc: A6 N1_V02S0101
|
|
arc: A7 W1_H02E0501
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0101
|
|
arc: B4 V02S0501
|
|
arc: B5 H00L0000
|
|
arc: B6 V02N0501
|
|
arc: B7 V02S0701
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F6
|
|
arc: E3_H06E0003 F3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R26C7:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 N1_V02S0501
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 H00L0100
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 H02E0501
|
|
arc: A5 V00B0000
|
|
arc: A6 H00L0000
|
|
arc: A7 H02W0501
|
|
arc: B0 H00R0100
|
|
arc: B1 H02W0301
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B4 V02S0501
|
|
arc: B5 H00R0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0701
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F1
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R26C8:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 H00L0100
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V02S0301
|
|
arc: A5 V02S0301
|
|
arc: A6 V02S0301
|
|
arc: A7 V02S0301
|
|
arc: B0 H00R0100
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B4 H02W0301
|
|
arc: B5 H00L0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0601 F4
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: M1 E1_H02W0001
|
|
arc: M4 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0601 Q4
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C9:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0103 N3_V06S0103
|
|
arc: W3_H06W0203 N3_V06S0203
|
|
arc: A0 N1_V02S0501
|
|
arc: A1 V02S0501
|
|
arc: A2 H00L0100
|
|
arc: A3 H02W0501
|
|
arc: A4 V02S0101
|
|
arc: A5 V00T0000
|
|
arc: A6 H00R0000
|
|
arc: A7 V00T0100
|
|
arc: B0 V02S0301
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 H02E0101
|
|
arc: B5 H02E0101
|
|
arc: B6 H02E0101
|
|
arc: B7 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M3 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0601 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C10:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 H02E0501
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 V00T0000
|
|
arc: B1 V02S0101
|
|
arc: B2 H02E0301
|
|
arc: B3 V02S0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V00B0100
|
|
arc: B6 V00B0000
|
|
arc: B7 V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0601 F6
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 F6
|
|
arc: V01S0100 F2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C11:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0000
|
|
arc: A4 H02W0701
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B4 E1_H02W0101
|
|
arc: C4 V00T0000
|
|
arc: CE0 V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V00B0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0103 F1
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: M1 H02W0001
|
|
arc: M4 H02W0401
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 F1
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0010000000000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R27C12:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0101
|
|
arc: A6 V02S0301
|
|
arc: A7 Q7
|
|
arc: B0 V02N0101
|
|
arc: B1 Q1
|
|
arc: B2 V02N0101
|
|
arc: B3 Q3
|
|
arc: B4 H02W0301
|
|
arc: B6 H02W0101
|
|
arc: B7 V02S0501
|
|
arc: C0 H02E0401
|
|
arc: C2 H02E0601
|
|
arc: C5 V00B0100
|
|
arc: C6 V00T0100
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: D2 H01E0101
|
|
arc: D3 V02N0201
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 H02W0201
|
|
arc: D7 S1_V02N0401
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0701 F7
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F6
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
word: SLICED.K1.INIT 1000000011000000
|
|
word: SLICEC.K0.INIT 1110111011101110
|
|
word: SLICEC.K1.INIT 1111010110100000
|
|
word: SLICED.K0.INIT 0010000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R27C13:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V02S0701
|
|
arc: A3 V02S0701
|
|
arc: A4 N1_V01S0100
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 H02E0701
|
|
arc: B0 V02N0101
|
|
arc: B1 H02E0301
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 H02W0301
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V02S0401
|
|
arc: C2 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C4 S1_V02N0201
|
|
arc: C6 F4
|
|
arc: C7 V02S0201
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 N1_V02S0201
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 E1_H02W0201
|
|
arc: D6 F0
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F1
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 Q7
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q6
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F6
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICED.K1.INIT 0000010000000000
|
|
word: SLICEB.K1.INIT 0000001000000000
|
|
word: SLICEB.K0.INIT 0010000000000000
|
|
word: SLICEA.K1.INIT 0000010000000000
|
|
word: SLICEA.K0.INIT 0000000000011101
|
|
word: SLICEC.K0.INIT 0100010101010101
|
|
word: SLICED.K0.INIT 0000000010110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R27C14:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0301
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 W1_H02E0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 W1_H02E0201
|
|
arc: D2 V02S0001
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R27C15:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0103 H01E0101
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 F5
|
|
arc: A6 V02S0101
|
|
arc: B0 H00R0100
|
|
arc: B1 H02W0101
|
|
arc: B2 W1_H02E0301
|
|
arc: B5 V02N0701
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C2 F4
|
|
arc: C4 H02E0401
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 W1_H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0401 F4
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F4
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
word: SLICED.K1.INIT 0000111100001100
|
|
word: SLICEA.K0.INIT 0101010100000100
|
|
word: SLICEA.K1.INIT 0101010100000100
|
|
word: SLICEB.K0.INIT 0101010100000100
|
|
word: SLICEC.K1.INIT 1100110000000000
|
|
word: SLICED.K0.INIT 1010000010100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C16:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: B1 Q1
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F0
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V02N0501 Q7
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R27C17:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H00L0000
|
|
arc: B0 H02E0301
|
|
arc: C0 H02W0401
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0100 F0
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C18:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C19:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0100 H02W0301
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: A0 E1_H02W0501
|
|
arc: B0 H01W0100
|
|
arc: C0 S1_V02N0601
|
|
arc: CE1 H00L0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 Q6
|
|
word: SLICEA.K0.INIT 1011101011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R27C20:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: A2 H00L0100
|
|
arc: A3 F5
|
|
arc: A4 V02S0301
|
|
arc: A5 V02N0301
|
|
arc: A7 N1_V01N0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 Q3
|
|
arc: B4 H02W0101
|
|
arc: B5 H02E0301
|
|
arc: B7 H02E0101
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 H02W0401
|
|
arc: C7 V00B0100
|
|
arc: CE0 V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02N0201
|
|
arc: D3 V02S0001
|
|
arc: D4 V01N0001
|
|
arc: D5 H02E0201
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 W1_H02E0301
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 H02E0601
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: V00B0100 Q7
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEB.K0.INIT 0000000010001100
|
|
word: SLICEC.K0.INIT 1100100011111011
|
|
word: SLICEC.K1.INIT 1111000011100000
|
|
word: SLICED.K1.INIT 0001110100000000
|
|
word: SLICEB.K1.INIT 0000100000001010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C21:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 V02N0301
|
|
arc: C0 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0001 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0000 F2
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M5 H00R0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0501 Q7
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0103 F2
|
|
arc: N3_V06N0303 Q5
|
|
arc: V01S0100 F0
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C22:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02W0001
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: A0 H00R0000
|
|
arc: A2 V01N0101
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: B5 H02E0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V01S0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V01S0100
|
|
arc: D5 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 N1_V01N0001
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 H02W0401
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 F0
|
|
arc: S1_V02S0501 F5
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICEB.K0.INIT 1100110010101010
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
word: SLICEC.K1.INIT 1111110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R27C23:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V00T0000
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F1
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N3_V06N0103 F1
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0101 F1
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R27C24:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: A0 H00L0100
|
|
arc: A3 S1_V02N0701
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 V02N0301
|
|
arc: B0 V00T0000
|
|
arc: B3 V02N0301
|
|
arc: B5 H02W0301
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 N1_V02S0701
|
|
arc: C0 H02W0401
|
|
arc: C3 H02E0401
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 F4
|
|
arc: C7 N1_V02S0201
|
|
arc: D0 V00B0100
|
|
arc: D3 H02W0001
|
|
arc: D5 V02N0601
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 E1_H01E0101
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V02N0201 F2
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000010000100001
|
|
word: SLICED.K0.INIT 0110000000000000
|
|
word: SLICEA.K0.INIT 1000010000100001
|
|
word: SLICED.K1.INIT 1001000000001001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0100000110000010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C25:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: B2 V01N0001
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D2 W1_H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 Q2
|
|
word: SLICEB.K0.INIT 1100110000000000
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C26:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 V01N0101
|
|
arc: B0 S1_V02N0301
|
|
arc: B2 V01N0001
|
|
arc: C1 V02N0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q2
|
|
word: SLICEA.K0.INIT 1000100010001000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1100110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C27:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A2 V01N0101
|
|
arc: C0 H00L0100
|
|
arc: C1 S1_V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0301 Q1
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0301 Q1
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C28:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: A0 H00L0000
|
|
arc: B0 H01W0100
|
|
arc: C0 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000101100001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C29:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: A4 H02W0501
|
|
arc: A7 V02S0101
|
|
arc: B0 H02E0301
|
|
arc: B2 V02N0301
|
|
arc: B3 H00L0000
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V00T0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q2
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V02N0301 F3
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 F6
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C2:PLC2
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: C2 V02S0401
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02W0201
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M5 V01S0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0101 Q1
|
|
arc: V01S0000 Q2
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R27C30:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 V02N0701
|
|
arc: A2 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: A5 E1_H01W0000
|
|
arc: A7 V02N0101
|
|
arc: B1 E1_H01W0100
|
|
arc: B3 H00R0000
|
|
arc: B6 S1_V02N0501
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0101 F3
|
|
arc: S1_V02S0401 F6
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 F4
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R27C31:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: A0 V01N0101
|
|
arc: A4 H02E0501
|
|
arc: A5 H02E0501
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 H00R0000
|
|
arc: B1 V02N0101
|
|
arc: B4 H02E0101
|
|
arc: B6 V00B0100
|
|
arc: B7 H02W0101
|
|
arc: C5 H02E0401
|
|
arc: C6 H02W0601
|
|
arc: C7 H02W0401
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 H00R0100
|
|
arc: D6 H02E0201
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0201 F0
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICED.K1.INIT 1000010000100001
|
|
word: SLICED.K0.INIT 1001000000001001
|
|
word: SLICEC.K0.INIT 1100110010001000
|
|
word: SLICEC.K1.INIT 1111101000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C32:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 N1_V02S0501
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 V02N0101
|
|
arc: A7 Q7
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0701 Q7
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0501 Q5
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICED.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C33:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: A2 V02S0501
|
|
arc: A3 V00T0000
|
|
arc: A4 N1_V01S0100
|
|
arc: A6 V02S0101
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 V00B0000
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0301 F3
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0401 F6
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0501 F5
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C34:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: B0 V00T0000
|
|
arc: B1 H02E0301
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F0
|
|
arc: V01S0000 F1
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R27C35:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H00R0000
|
|
arc: A4 V02S0101
|
|
arc: B0 V02S0101
|
|
arc: B4 N1_V01S0000
|
|
arc: C0 H00L0000
|
|
arc: C4 S1_V02N0001
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D4 E1_H01W0100
|
|
arc: E1_H01E0001 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V02N0201 F0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEC.K0.INIT 0010011100000000
|
|
word: SLICEA.K0.INIT 1010100000100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C36:PLC2
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: B1 S1_V02N0301
|
|
arc: C1 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK2 CLK0
|
|
arc: W1_H02W0601 Q4
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1111111110101010
|
|
word: SLICEA.K1.INIT 1111111011101110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C37:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: H00L0100 H02W0101
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: A0 H00L0100
|
|
arc: B0 V00T0000
|
|
arc: C0 N1_V01N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0101000001010100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C38:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0401 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C39:PLC2
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
|
|
.tile R27C3:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: A2 V00T0000
|
|
arc: B2 V02N0101
|
|
arc: C2 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 S1_V02N0201
|
|
arc: E1_H01E0001 F2
|
|
arc: F2 F2_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: M2 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 Q2
|
|
word: SLICEB.K0.INIT 0100011100000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C41:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R27C42:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R27C44:PLC2
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 H06E0203
|
|
|
|
.tile R27C45:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R27C4:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H02E0001
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C5:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: C4 W1_H02E0401
|
|
arc: C7 W1_H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H00R0100
|
|
arc: D7 N1_V02S0601
|
|
arc: E3_H06E0203 F4
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0203 F4
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 Q0
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 1111111100001111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C6:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: A1 H00L0000
|
|
arc: A2 H02W0701
|
|
arc: A4 V02S0301
|
|
arc: A5 V02S0301
|
|
arc: A7 V02S0301
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V02S0301
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 H02E0301
|
|
arc: B5 H02E0301
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 H02E0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 H00L0100
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V02S0201
|
|
arc: C5 V02N0201
|
|
arc: C6 V00B0100
|
|
arc: C7 V02N0201
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 V02S0201
|
|
arc: D2 V00T0100
|
|
arc: D3 V02S0001
|
|
arc: D4 H02E0201
|
|
arc: D5 H02E0001
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F4
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0601 F4
|
|
arc: S3_V06S0103 F1
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F5
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEC.K0.INIT 0010000000000000
|
|
word: SLICEB.K0.INIT 1011101110001000
|
|
word: SLICED.K0.INIT 1111110000001100
|
|
word: SLICEB.K1.INIT 1111001111000000
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 0010000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C7:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W3_H06W0303 V01N0101
|
|
arc: A2 V00B0000
|
|
arc: A3 H00L0100
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 H02E0701
|
|
arc: A6 H00L0000
|
|
arc: A7 H02E0501
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 H02W0101
|
|
arc: B3 H02E0101
|
|
arc: B4 H02E0301
|
|
arc: B5 V01S0000
|
|
arc: B6 V02S0701
|
|
arc: B7 V00B0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q2
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F4
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00T0000
|
|
arc: M2 H02E0601
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 Q4
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C88:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R27C8:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A0 H00L0000
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 V00T0000
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 V00B0000
|
|
arc: A5 H02E0501
|
|
arc: A6 H02E0701
|
|
arc: A7 Q7
|
|
arc: B0 V02S0101
|
|
arc: B1 H02E0301
|
|
arc: B2 H00R0100
|
|
arc: B3 H02E0101
|
|
arc: B4 V00B0100
|
|
arc: B5 V00B0100
|
|
arc: B6 V00B0100
|
|
arc: B7 V02S0501
|
|
arc: CE0 H00R0000
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F6
|
|
arc: LSR0 H02W0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0101 F1
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0401 F4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C9:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0003 V06S0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 V06S0203
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: A4 H02E0501
|
|
arc: A5 H02E0701
|
|
arc: A6 H02E0501
|
|
arc: A7 H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0101
|
|
arc: B3 H02E0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V00B0100
|
|
arc: B6 H02E0101
|
|
arc: B7 V02S0701
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F3
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F0
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C10:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 V02N0501
|
|
arc: A3 V00T0000
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 W1_H02E0701
|
|
arc: B2 W1_H02E0101
|
|
arc: B4 W1_H02E0301
|
|
arc: B7 V00B0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q7
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011010
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C11:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 V02S0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A6 W1_H02E0501
|
|
arc: B2 V02S0101
|
|
arc: B3 H00L0000
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 H00R0000
|
|
arc: B7 V00T0000
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1001100110011010
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C12:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A0 V02S0701
|
|
arc: A6 W1_H02E0501
|
|
arc: B1 V00B0000
|
|
arc: B2 V02S0301
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 H00R0000
|
|
arc: B7 V00T0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C13:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A0 V02S0701
|
|
arc: A5 Q5
|
|
arc: A6 N1_V02S0101
|
|
arc: A7 N1_V02S0101
|
|
arc: B1 W1_H02E0101
|
|
arc: B4 W1_H02E0301
|
|
arc: B6 V00T0000
|
|
arc: B7 V00T0000
|
|
arc: C4 V00B0100
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H01W0000
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 W1_H02E0201
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0101 Q3
|
|
arc: E3_H06E0203 F7
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: M0 H02E0601
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F6
|
|
arc: V00B0100 Q7
|
|
arc: W1_H02W0601 F4
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1111110000110000
|
|
word: SLICEC.K1.INIT 1010101011111111
|
|
word: SLICED.K0.INIT 0100000000000000
|
|
word: SLICED.K1.INIT 0000010000000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R28C14:PLC2
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 F7
|
|
arc: A4 V00T0100
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B4 H02W0101
|
|
arc: B7 H02W0101
|
|
arc: C0 F4
|
|
arc: C4 Q4
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F0
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 H02W0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q3
|
|
word: SLICEC.K0.INIT 0001110100000000
|
|
word: SLICED.K1.INIT 1111000011100000
|
|
word: SLICEA.K0.INIT 0000100000001010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R28C15:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0501
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 E1_H01W0000
|
|
arc: A7 F5
|
|
arc: B0 H00R0100
|
|
arc: B1 V00B0000
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 H01E0101
|
|
arc: B7 W1_H02E0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 N1_V01S0100
|
|
arc: C4 N1_V02S0001
|
|
arc: C5 V02N0201
|
|
arc: C7 F4
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D4 V02S0601
|
|
arc: D5 W1_H02E0001
|
|
arc: D7 E1_H01W0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0100 Q1
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEA.K0.INIT 0101010100000100
|
|
word: SLICEA.K1.INIT 0101010100000100
|
|
word: SLICEC.K0.INIT 0000110100000000
|
|
word: SLICEC.K1.INIT 1000101000000000
|
|
word: SLICED.K1.INIT 1100100011111011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R28C16:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 H00L0100
|
|
arc: B0 N1_V02S0301
|
|
arc: B2 H02E0101
|
|
arc: B3 Q3
|
|
arc: C0 V02N0601
|
|
arc: C2 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 V00B0100
|
|
arc: D3 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F0
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R28C17:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A4 N1_V01S0100
|
|
arc: B3 Q3
|
|
arc: B4 V02N0701
|
|
arc: C2 H00R0100
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 V02N0201
|
|
arc: CE0 H02E0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 W1_H02E0201
|
|
arc: D4 E1_H01W0100
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F2
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 H02E0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N3_V06N0203 F4
|
|
arc: V01S0000 Q4
|
|
word: SLICEC.K0.INIT 1101110111010001
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R28C18:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W3_H06W0003 V06N0003
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A3 W1_H02E0701
|
|
arc: A5 Q5
|
|
arc: A7 F5
|
|
arc: B3 Q3
|
|
arc: B5 V01S0000
|
|
arc: B7 F3
|
|
arc: C3 H02E0401
|
|
arc: C5 H02E0401
|
|
arc: C7 V00B0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 H02W0001
|
|
arc: D5 V02N0601
|
|
arc: D7 V02N0401
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: M0 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q0
|
|
word: SLICEC.K1.INIT 0011010100000000
|
|
word: SLICEB.K1.INIT 1111111000000000
|
|
word: SLICED.K1.INIT 0100000001000100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C19:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: B1 Q1
|
|
arc: C0 V02S0401
|
|
arc: C1 V02S0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V01S0100
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0001 F0
|
|
arc: V00T0100 Q3
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R28C20:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A0 H00L0000
|
|
arc: A3 V02S0501
|
|
arc: A4 V02S0101
|
|
arc: B0 V00B0000
|
|
arc: B2 F3
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: C0 V02S0401
|
|
arc: C2 F4
|
|
arc: C3 W1_H02E0601
|
|
arc: C4 H02E0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0001
|
|
arc: D4 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 W1_H02E0301
|
|
arc: M0 V00T0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0201 F0
|
|
arc: V00B0000 Q6
|
|
word: SLICEC.K0.INIT 0100010101010101
|
|
word: SLICEB.K1.INIT 1000101000000000
|
|
word: SLICEA.K0.INIT 0000000001010011
|
|
word: SLICEB.K0.INIT 0000001100110011
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R28C21:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R28C22:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02S0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: B0 V00B0000
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 F0
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 F0
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0003 F0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C23:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: B0 S1_V02N0301
|
|
arc: C0 H00L0000
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0201 Q0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C24:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 H02W0701
|
|
arc: B1 H02W0101
|
|
arc: B4 H02E0301
|
|
arc: C2 E1_H01W0000
|
|
arc: C4 H02W0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D4 E1_H02W0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q1
|
|
arc: N3_V06N0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C25:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A2 V00B0000
|
|
arc: B0 H02W0301
|
|
arc: B3 H02E0101
|
|
arc: B4 H00L0000
|
|
arc: B5 H01E0101
|
|
arc: B6 V00T0000
|
|
arc: B7 N1_V01S0000
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: N1_V01N0001 F7
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R28C26:PLC2
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: A2 V01N0101
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 V00B0000
|
|
arc: B1 V01N0001
|
|
arc: B3 H02W0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02S0501
|
|
arc: E1_H01E0001 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F2
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R28C27:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0101
|
|
arc: A7 V02N0101
|
|
arc: B0 V02S0301
|
|
arc: B1 V00B0000
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0201
|
|
arc: C7 V02N0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V02N0401
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F4
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F1
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000010100000
|
|
word: SLICEC.K1.INIT 0101000000000000
|
|
word: SLICED.K1.INIT 0000000001010000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R28C28:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00L0100 V02N0101
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: C0 H00L0000
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C29:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00T0000 H02W0201
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 H00R0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V02S0501
|
|
arc: C0 H02W0601
|
|
arc: C2 H02W0601
|
|
arc: C3 H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 H02W0201
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q3
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1111101000000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C2:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: V01S0100 Q3
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C30:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A4 S1_V02N0101
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H00L0100
|
|
arc: C4 V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D4 V02S0401
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q0
|
|
arc: V01S0100 Q4
|
|
word: SLICEC.K0.INIT 1111101000000000
|
|
word: SLICEA.K0.INIT 1111000011000000
|
|
word: SLICEA.K1.INIT 0000111100001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C31:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: C0 H02E0401
|
|
arc: C1 H00L0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
word: SLICEA.K0.INIT 1111000011000000
|
|
word: SLICEA.K1.INIT 1111000011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C32:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A0 H02W0501
|
|
arc: A1 E1_H01E0001
|
|
arc: A3 V02S0701
|
|
arc: A4 F5
|
|
arc: A5 N1_V01N0101
|
|
arc: A7 H00L0000
|
|
arc: B0 V02S0101
|
|
arc: B1 F3
|
|
arc: B3 H00R0000
|
|
arc: B5 W1_H02E0301
|
|
arc: B7 V00T0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C3 H02W0401
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V02S0001
|
|
arc: C7 H02W0601
|
|
arc: CE0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 H02E0001
|
|
arc: D3 W1_H02E0201
|
|
arc: D4 V02S0401
|
|
arc: D5 E1_H02W0001
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0100 F1
|
|
word: SLICEC.K0.INIT 1010000000000000
|
|
word: SLICEC.K1.INIT 1111110001010100
|
|
word: SLICED.K1.INIT 1011000010111011
|
|
word: SLICEB.K1.INIT 1000001001000001
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1100110010001000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C33:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A1 F5
|
|
arc: A4 V00B0000
|
|
arc: A5 N1_V01S0100
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V00T0000
|
|
arc: B4 H02E0301
|
|
arc: B5 H02E0301
|
|
arc: C0 V02N0601
|
|
arc: C1 F4
|
|
arc: C4 H02E0601
|
|
arc: C5 V02S0201
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 H00R0000
|
|
arc: D4 H02E0001
|
|
arc: D5 W1_H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F1
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEC.K0.INIT 0000110111011101
|
|
word: SLICEC.K1.INIT 1111001101010001
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1111110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C34:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: B0 S1_V02N0101
|
|
arc: C0 H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C35:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 V02N0301
|
|
arc: A7 H02W0701
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0301
|
|
arc: B5 V02N0501
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 V02N0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 V02N0601
|
|
arc: C5 V00B0100
|
|
arc: C7 V00B0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 H02W0201
|
|
arc: D3 E1_H02W0001
|
|
arc: D5 E1_H02W0001
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0001 F0
|
|
arc: N3_V06N0003 F3
|
|
arc: N3_V06N0103 F2
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEC.K1.INIT 0100000000000000
|
|
word: SLICEB.K1.INIT 0001000000000000
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICED.K1.INIT 0010000000000000
|
|
word: SLICEB.K0.INIT 0100000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R28C36:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 H02W0501
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 H00R0000
|
|
arc: A7 F5
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 V01N0001
|
|
arc: B3 H00R0000
|
|
arc: B4 V02N0501
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 E1_H02W0101
|
|
arc: C1 V02N0401
|
|
arc: C2 H02E0401
|
|
arc: C3 V02N0401
|
|
arc: C4 H02E0601
|
|
arc: C5 V01N0101
|
|
arc: C6 V01N0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D2 V00T0100
|
|
arc: D3 V02N0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H02W0201
|
|
arc: D6 H02W0201
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 F3
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0203 F7
|
|
arc: N3_V06N0303 F6
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0203 F7
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 0100000000000000
|
|
word: SLICEC.K1.INIT 0010000000000000
|
|
word: SLICED.K1.INIT 1010101000000000
|
|
word: SLICEC.K0.INIT 0001000000000000
|
|
word: SLICEB.K0.INIT 0000000010000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET SET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C37:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 F7
|
|
arc: A7 V02N0101
|
|
arc: B0 H00R0100
|
|
arc: B1 V00T0000
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C7 V01N0101
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 V02N0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 Q7
|
|
arc: H01W0100 F7
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q1
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K1.INIT 1111111111111100
|
|
word: SLICEA.K0.INIT 1100110011111010
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
word: SLICED.K1.INIT 0000101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET SET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET SET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R28C38:PLC2
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 V06S0003
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R28C39:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: V00B0100 H02E0701
|
|
arc: B0 V02N0101
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0011001100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C3:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: A0 H02W0701
|
|
arc: A1 E1_H01E0001
|
|
arc: A3 H02E0701
|
|
arc: B0 F3
|
|
arc: B1 V02N0301
|
|
arc: B3 Q3
|
|
arc: C0 H00L0000
|
|
arc: C1 H02W0401
|
|
arc: C3 N1_V02S0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 N1_V02S0201
|
|
arc: D3 V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0100 Q7
|
|
word: SLICEB.K1.INIT 0000110100001111
|
|
word: SLICEA.K0.INIT 0100000001000100
|
|
word: SLICEA.K1.INIT 1100100011111011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C44:PLC2
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
|
|
.tile R28C4:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N3_V06N0003 V01N0001
|
|
arc: N3_V06N0103 H01E0101
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00T0000 H02E0001
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A5 Q5
|
|
arc: A6 N1_V01N0101
|
|
arc: B2 V02N0101
|
|
arc: B3 Q3
|
|
arc: B5 H00L0000
|
|
arc: B6 F3
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 E1_H02W0601
|
|
arc: C5 V02N0201
|
|
arc: C6 Q6
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 N1_V02S0201
|
|
arc: D5 H02E0201
|
|
arc: D6 V02N0601
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F2
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEC.K1.INIT 0000010100000011
|
|
word: SLICEB.K0.INIT 0000000100100011
|
|
word: SLICEB.K1.INIT 1101111100000000
|
|
word: SLICED.K0.INIT 0100000001000100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C5:PLC2
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: A0 H00L0000
|
|
arc: A4 V00T0000
|
|
arc: A7 Q7
|
|
arc: B0 N1_V02S0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B7 V00B0000
|
|
arc: C0 E1_H02W0401
|
|
arc: C4 Q4
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D4 E1_H02W0001
|
|
arc: D7 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 F7
|
|
arc: V00B0000 F4
|
|
arc: V00T0000 Q2
|
|
word: SLICEC.K0.INIT 0000000000011101
|
|
word: SLICEA.K0.INIT 0010001100110011
|
|
word: SLICED.K1.INIT 0010001100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R28C6:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: B0 V02N0101
|
|
arc: C0 N1_V02S0401
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C7:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 V02N0301
|
|
arc: A6 V02N0301
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B4 H02W0301
|
|
arc: B5 V02N0501
|
|
arc: B6 V02N0501
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 H00L0000
|
|
arc: C4 V00T0100
|
|
arc: C5 V00T0000
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 H02W0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D5 H00R0100
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F6
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0601 F6
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F3
|
|
word: SLICED.K0.INIT 0010000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
word: SLICEC.K0.INIT 1100101011001010
|
|
word: SLICEB.K1.INIT 0011001100000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C8:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H02W0501
|
|
arc: A2 F7
|
|
arc: A4 H02E0501
|
|
arc: A5 V02N0101
|
|
arc: A6 V02N0101
|
|
arc: A7 H00L0000
|
|
arc: B0 V02N0101
|
|
arc: B1 H02W0101
|
|
arc: B2 V02N0301
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 V02S0701
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 H02W0301
|
|
arc: B7 V02N0701
|
|
arc: C1 H00L0100
|
|
arc: C2 H02W0401
|
|
arc: C3 H00L0100
|
|
arc: C6 N1_V02S0001
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 H00R0000
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 V02S0201
|
|
arc: D4 H00L0100
|
|
arc: D5 H00R0100
|
|
arc: D7 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0501 Q5
|
|
word: SLICED.K0.INIT 1101100011011000
|
|
word: SLICEB.K1.INIT 1111110000001100
|
|
word: SLICEC.K0.INIT 1100110010101010
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
word: SLICEC.K1.INIT 1110111001000100
|
|
word: SLICED.K1.INIT 1011000000000000
|
|
word: SLICEB.K0.INIT 1100111110001011
|
|
word: SLICEA.K0.INIT 1011101110001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R28C9:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 F7
|
|
arc: A7 H02W0501
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 H00L0000
|
|
arc: B6 F3
|
|
arc: B7 V02N0501
|
|
arc: C0 V02S0401
|
|
arc: C1 N1_V02S0601
|
|
arc: C3 W1_H02E0401
|
|
arc: C4 V02S0201
|
|
arc: C6 V02S0001
|
|
arc: C7 H02W0401
|
|
arc: CE0 H00L0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 V02N0201
|
|
arc: D3 N1_V02S0201
|
|
arc: D5 V02N0601
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0401 F6
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEC.K0.INIT 1110001011100010
|
|
word: SLICEA.K0.INIT 1111010110100000
|
|
word: SLICEB.K1.INIT 0000000011011111
|
|
word: SLICED.K1.INIT 1011000000000000
|
|
word: SLICED.K0.INIT 0001010100010101
|
|
word: SLICEB.K0.INIT 0101010110101010
|
|
word: SLICEC.K1.INIT 1111111101010101
|
|
word: SLICEA.K1.INIT 1111101001010000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R29C10:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: A0 H00L0000
|
|
arc: A2 N1_V02S0701
|
|
arc: A4 V00B0000
|
|
arc: A5 H02E0501
|
|
arc: A6 H00R0000
|
|
arc: B1 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B7 V00T0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N3_V06N0203 Q4
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C11:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A2 V00B0000
|
|
arc: A4 N1_V02S0301
|
|
arc: A5 H02E0501
|
|
arc: A6 H00R0000
|
|
arc: B0 V00T0000
|
|
arc: B1 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B7 N1_V02S0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C12:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: A6 H00R0000
|
|
arc: B3 Q3
|
|
arc: B5 H02W0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C2 H00L0100
|
|
arc: C3 H00R0100
|
|
arc: C4 V02S0201
|
|
arc: C5 V02S0201
|
|
arc: C6 V02S0201
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02E0001
|
|
arc: D3 V02S0201
|
|
arc: D4 H02W0201
|
|
arc: D6 H02W0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q6
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 F4
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0601 F4
|
|
arc: N3_V06N0203 F4
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000011110000
|
|
word: SLICEC.K1.INIT 0000110000001100
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICED.K0.INIT 0000000001010011
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C13:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0303 H01E0101
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 V01N0101
|
|
arc: A3 H02E0701
|
|
arc: A4 F7
|
|
arc: A5 Q5
|
|
arc: A6 N1_V02S0301
|
|
arc: A7 F5
|
|
arc: B1 Q1
|
|
arc: B3 V02S0101
|
|
arc: B4 V02S0701
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 V00B0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C3 H00L0100
|
|
arc: C4 H02W0601
|
|
arc: C5 V00B0100
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D3 V02N0001
|
|
arc: D4 N1_V02S0601
|
|
arc: D5 H01W0000
|
|
arc: D6 V02S0401
|
|
arc: D7 F0
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M0 H02E0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F6
|
|
arc: W3_H06W0203 F4
|
|
word: SLICED.K0.INIT 0000000010000000
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEC.K1.INIT 0000101100001111
|
|
word: SLICEB.K1.INIT 1100010000000000
|
|
word: SLICED.K1.INIT 0000010100001111
|
|
word: SLICEC.K0.INIT 1111010111000101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C14:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A2 V00B0000
|
|
arc: A3 W1_H02E0501
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 F7
|
|
arc: A7 W1_H02E0701
|
|
arc: B1 Q1
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 Q3
|
|
arc: B5 V02S0501
|
|
arc: B6 F3
|
|
arc: B7 H02E0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 H02W0601
|
|
arc: C3 W1_H02E0401
|
|
arc: C5 H02E0401
|
|
arc: C6 H01E0001
|
|
arc: C7 V00B0100
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D2 V02N0001
|
|
arc: D3 F0
|
|
arc: D5 V02S0601
|
|
arc: D6 V02N0401
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0303 F5
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F2
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K1.INIT 0000100000000000
|
|
word: SLICEB.K0.INIT 0000010000000000
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 0100010100000000
|
|
word: SLICED.K1.INIT 1100010000000000
|
|
word: SLICED.K0.INIT 1110000011101111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C15:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 F0
|
|
arc: M0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C16:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 V02S0201
|
|
arc: E1_H02E0101 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0001 F0
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R29C17:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: A0 H00L0000
|
|
arc: A2 F5
|
|
arc: A3 V01N0101
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 F3
|
|
arc: B2 H01W0100
|
|
arc: B3 H02E0101
|
|
arc: B4 V02N0701
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 W1_H02E0101
|
|
arc: C0 F4
|
|
arc: C2 H02W0401
|
|
arc: C3 W1_H02E0401
|
|
arc: C4 V02S0201
|
|
arc: C5 E1_H02W0401
|
|
arc: C7 W1_H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D2 V00B0100
|
|
arc: D3 V02S0201
|
|
arc: D4 H02E0001
|
|
arc: D5 W1_H02E0201
|
|
arc: D7 W1_H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: M0 H02W0601
|
|
arc: M2 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V02N0201 F0
|
|
arc: V00B0100 F7
|
|
word: SLICEB.K1.INIT 0000001100000101
|
|
word: SLICEC.K0.INIT 0000000011011111
|
|
word: SLICEA.K0.INIT 0010000000110000
|
|
word: SLICED.K1.INIT 1111000011100000
|
|
word: SLICEC.K1.INIT 0011000001010000
|
|
word: SLICEB.K0.INIT 0100010100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C18:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: C0 V02S0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C19:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: B0 E1_H02W0301
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 N1_V02S0401
|
|
arc: CE0 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00T0100
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0100 Q7
|
|
arc: V00T0100 Q1
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEA.K1.INIT 1111111100001111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R29C20:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: B2 V01N0001
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 E1_H02W0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 E1_H02W0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 W1_H02E0301
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M4 E1_H02W0401
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0201 F0
|
|
arc: N3_V06N0103 F2
|
|
arc: V00B0000 Q4
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R29C21:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: B1 V02N0101
|
|
arc: C1 V02N0601
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H00R0000
|
|
arc: E1_H01E0001 F1
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 F1
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 F1
|
|
arc: W1_H02W0301 Q1
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R29C22:PLC2
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0003 H01E0001
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 V02N0701
|
|
arc: B0 H02W0301
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H02E0001
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1110111000100010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C23:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00T0000 Q0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C24:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A2 V01N0101
|
|
arc: A5 V00T0000
|
|
arc: B0 W1_H02E0301
|
|
arc: B3 V01N0001
|
|
arc: B4 V02N0501
|
|
arc: B6 V02N0701
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M3 H00L0000
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0401 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q3
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICED.K1.INIT 1111111111110000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C25:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: C2 N1_V01S0100
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 W1_H02E0001
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0501 Q5
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C26:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A2 V02S0501
|
|
arc: A4 V00B0000
|
|
arc: A5 V02S0301
|
|
arc: B0 V02S0101
|
|
arc: B6 V00B0000
|
|
arc: C1 N1_V01S0100
|
|
arc: C4 V00T0000
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 V00T0000
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D4 H00R0100
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 W1_H02E0301
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0401 F6
|
|
word: SLICEC.K1.INIT 0000101000000000
|
|
word: SLICEC.K0.INIT 0101000000000000
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
word: SLICED.K0.INIT 0011000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R29C27:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: H00L0000 H02W0201
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A5 H02W0701
|
|
arc: A6 H02W0701
|
|
arc: A7 V02N0301
|
|
arc: B0 W1_H02E0101
|
|
arc: B2 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 H00L0000
|
|
arc: B6 V00T0000
|
|
arc: B7 F3
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V00T0000
|
|
arc: C6 H02W0601
|
|
arc: CE0 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D2 V02N0001
|
|
arc: D3 F2
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 H02W0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F6
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0201 F2
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 F7
|
|
arc: V00T0000 F2
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0501 F7
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 1100110000000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 1101110111001100
|
|
word: SLICED.K0.INIT 0000000000001000
|
|
word: SLICEC.K1.INIT 0000000010000000
|
|
word: SLICEC.K0.INIT 0000001100000011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R29C28:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0003 V06N0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A1 F5
|
|
arc: A4 V00B0000
|
|
arc: A5 V00B0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V02N0101
|
|
arc: B2 H00R0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 H00L0000
|
|
arc: B5 H00L0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 H02W0601
|
|
arc: C7 V00T0100
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 H02E0001
|
|
arc: D2 Q2
|
|
arc: D3 V00T0100
|
|
arc: D4 H00R0100
|
|
arc: D5 H00L0100
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q3
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0501 F5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 Q4
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEC.K1.INIT 0000001000000000
|
|
word: SLICEA.K1.INIT 1010110000000000
|
|
word: SLICEA.K0.INIT 0011110000000000
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0011000011000000
|
|
word: SLICEB.K1.INIT 0011000011000000
|
|
word: SLICEC.K0.INIT 0110000010100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C29:PLC2
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 V02N0701
|
|
arc: B0 E1_H01W0100
|
|
arc: B5 V01S0000
|
|
arc: C4 H02W0401
|
|
arc: C5 V02N0201
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D4 H01W0000
|
|
arc: D5 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N3_V06N0203 Q4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEA.K0.INIT 0000000000010001
|
|
word: SLICEC.K1.INIT 1100111111000000
|
|
word: SLICEC.K0.INIT 0000000011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R29C2:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C30:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 H00R0000
|
|
arc: A1 F5
|
|
arc: A2 F7
|
|
arc: A3 V00B0000
|
|
arc: A6 F5
|
|
arc: A7 N1_V01N0101
|
|
arc: B0 H01W0100
|
|
arc: B1 V02N0301
|
|
arc: B2 F3
|
|
arc: B3 S1_V02N0301
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 H00L0000
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 V00T0000
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 H02W0201
|
|
arc: D3 V02N0201
|
|
arc: D5 N1_V02S0601
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEA.K1.INIT 1111111110001000
|
|
word: SLICEA.K0.INIT 0000110100001100
|
|
word: SLICEC.K1.INIT 0000000011110000
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 1000110010101111
|
|
word: SLICEB.K0.INIT 0100010000000000
|
|
word: SLICED.K0.INIT 0000000000010000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C31:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: A0 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A3 V00T0000
|
|
arc: A4 W1_H02E0701
|
|
arc: A7 H00R0000
|
|
arc: B0 V01N0001
|
|
arc: B3 E1_H02W0101
|
|
arc: B7 V02N0701
|
|
arc: C0 V02N0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 V01N0101
|
|
arc: C6 H02E0601
|
|
arc: C7 S1_V02N0201
|
|
arc: D0 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0201
|
|
arc: D4 V02N0401
|
|
arc: D6 H02E0201
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F0
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: N1_V02N0601 F4
|
|
arc: V00B0000 F6
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0201 F2
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 0000101000001111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000101100000001
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 0000000000001000
|
|
word: SLICEB.K0.INIT 1111111100000101
|
|
word: SLICEB.K1.INIT 0010001000100011
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C32:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: A0 V01N0101
|
|
arc: A2 H02E0701
|
|
arc: A4 S1_V02N0301
|
|
arc: A7 F5
|
|
arc: B0 S1_V02N0101
|
|
arc: B3 S1_V02N0301
|
|
arc: B5 W1_H02E0101
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 F3
|
|
arc: C0 H00R0100
|
|
arc: C2 V02N0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V02N0201
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 S1_V02N0201
|
|
arc: C7 F4
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D2 H02E0201
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0601
|
|
arc: D6 V02N0601
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0701 F7
|
|
arc: N3_V06N0203 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0301 F3
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K0.INIT 0000110000000000
|
|
word: SLICEB.K0.INIT 1111111101010000
|
|
word: SLICEA.K0.INIT 1111111111111110
|
|
word: SLICEB.K1.INIT 1111000011000000
|
|
word: SLICEC.K0.INIT 0000000001010000
|
|
word: SLICED.K1.INIT 0000000000000010
|
|
word: SLICEC.K1.INIT 0000110011001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R29C33:PLC2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 S1_V02N0501
|
|
arc: B0 H02E0301
|
|
arc: B2 S1_V02N0301
|
|
arc: C0 H02E0401
|
|
arc: C2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 F0
|
|
word: SLICEB.K0.INIT 1100110011001111
|
|
word: SLICEA.K0.INIT 1100100011000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C34:PLC2
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: A0 N1_V02S0501
|
|
arc: A4 V00T0000
|
|
arc: C0 V02N0401
|
|
arc: C4 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D4 V02S0401
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0100 F0
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0203 F4
|
|
arc: S1_V02S0001 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K0.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 0000000000000101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R29C35:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: A0 F7
|
|
arc: A1 F7
|
|
arc: A2 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: B0 V02N0101
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B7 H01E0101
|
|
arc: C0 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C7 H02W0401
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V02N0201
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0001 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 F0
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02W0601
|
|
arc: M2 V00B0000
|
|
arc: M3 H01W0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0203 F7
|
|
arc: V00T0100 Q3
|
|
arc: W3_H06W0103 F2
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
word: SLICEA.K0.INIT 1000111110001000
|
|
word: SLICEA.K1.INIT 1010101000000000
|
|
word: SLICEB.K0.INIT 1011000110100000
|
|
word: SLICEB.K1.INIT 1111010111100100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C36:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A1 H00R0000
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: A5 E1_H01W0000
|
|
arc: A7 E1_H01W0000
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 V02S0301
|
|
arc: B5 V01S0000
|
|
arc: B6 V01S0000
|
|
arc: B7 E1_H02W0301
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H00R0100
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 V00B0100
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 F4
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0001
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H00L0100
|
|
arc: D6 V02N0401
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0601 F6
|
|
arc: N3_V06N0303 F6
|
|
arc: S1_V02S0201 F0
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F2
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 1100000000000000
|
|
word: SLICEB.K0.INIT 0011000010111010
|
|
word: SLICEB.K1.INIT 0000000010101010
|
|
word: SLICED.K1.INIT 0100000000000000
|
|
word: SLICEC.K1.INIT 0000000001000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C37:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A0 H02W0701
|
|
arc: A4 V02N0101
|
|
arc: C1 V02N0601
|
|
arc: C2 H00L0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02W0201
|
|
arc: D4 H02E0001
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEA.K0.INIT 0000000010101010
|
|
word: SLICEC.K0.INIT 0000000010101010
|
|
word: SLICEA.K1.INIT 0000000011110000
|
|
word: SLICEB.K0.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C38:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 V01N0101
|
|
arc: A6 S1_V02N0101
|
|
arc: B1 V01N0001
|
|
arc: B2 V02S0101
|
|
arc: B6 E1_H02W0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 S1_V02N0001
|
|
arc: D6 H00L0100
|
|
arc: E1_H02E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0601 F6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICEA.K1.INIT 1111110000001100
|
|
word: SLICEB.K0.INIT 0000000011001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C39:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: V00B0100 V02N0101
|
|
arc: A2 N1_V02S0501
|
|
arc: A6 V00T0100
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 V00T0000
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0201
|
|
arc: D3 W1_H02E0001
|
|
arc: D6 H02E0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F6
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0301 Q1
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0401 F6
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
word: SLICEB.K0.INIT 0010001000100010
|
|
word: SLICEB.K1.INIT 0011001100000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C3:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A4 V00B0000
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 F5
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: B4 H02W0101
|
|
arc: B5 E1_H02W0301
|
|
arc: C2 N1_V01N0001
|
|
arc: C4 H02W0601
|
|
arc: C5 V02S0201
|
|
arc: C6 F4
|
|
arc: CE0 H00R0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0201
|
|
arc: D3 V02S0201
|
|
arc: D4 F2
|
|
arc: D5 H02W0201
|
|
arc: D6 H02E0201
|
|
arc: E1_H01E0101 F6
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: V00B0000 Q4
|
|
word: SLICEB.K0.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
word: SLICEC.K0.INIT 1000110000000000
|
|
word: SLICEC.K1.INIT 0000000010111111
|
|
word: SLICED.K0.INIT 0000010100001111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C40:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: W1_H02W0101 H01E0101
|
|
|
|
.tile R29C41:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C43:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
|
|
.tile R29C44:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M5 V01S0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 Q7
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R29C47:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C4:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: A2 F5
|
|
arc: A3 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B2 H01W0100
|
|
arc: B3 V02N0301
|
|
arc: B5 E1_H02W0301
|
|
arc: B7 E1_H02W0101
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 H00L0000
|
|
arc: C5 V02S0001
|
|
arc: C7 V00T0100
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 Q2
|
|
arc: D3 H01E0101
|
|
arc: D5 H02E0201
|
|
arc: D7 H02E0201
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: M1 H00R0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F3
|
|
arc: V00T0000 F2
|
|
arc: V00T0100 Q1
|
|
word: SLICED.K1.INIT 0001000100000011
|
|
word: SLICEC.K1.INIT 0000101100001111
|
|
word: SLICEB.K0.INIT 0010001000000010
|
|
word: SLICEB.K1.INIT 1110000011101111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C50:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R29C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C56:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C5:PLC2
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 H02W0701
|
|
arc: A2 V02S0701
|
|
arc: A4 V02S0101
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 Q7
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 E1_H02W0301
|
|
arc: B4 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V00B0000
|
|
arc: C0 H00L0100
|
|
arc: C2 H00L0000
|
|
arc: C4 Q4
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 H02W0401
|
|
arc: CE0 V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 Q2
|
|
arc: D4 E1_H02W0201
|
|
arc: D6 F0
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 F4
|
|
word: SLICEA.K0.INIT 1100111011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0001101100000000
|
|
word: SLICEB.K0.INIT 1100110011001000
|
|
word: SLICED.K1.INIT 0010001100000000
|
|
word: SLICED.K0.INIT 1100100011111011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R29C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C68:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R29C6:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A4 V02S0101
|
|
arc: B0 V00B0000
|
|
arc: B2 H01W0100
|
|
arc: B4 H02W0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C2 F4
|
|
arc: C4 Q4
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D2 E1_H02W0001
|
|
arc: D4 E1_H01W0100
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 F0
|
|
word: SLICEA.K0.INIT 0000010100000011
|
|
word: SLICEC.K0.INIT 0011000100110011
|
|
word: SLICEB.K0.INIT 0100000001010000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C74:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R29C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C7:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0100 H02W0301
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 E1_H01E0001
|
|
arc: A3 H00L0100
|
|
arc: A4 H02W0501
|
|
arc: A5 H02W0501
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 H01W0100
|
|
arc: B3 H02E0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 H02E0301
|
|
arc: B6 H02W0301
|
|
arc: B7 H02E0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C3 H02W0601
|
|
arc: C4 V00B0100
|
|
arc: C5 V00B0100
|
|
arc: C6 H02W0601
|
|
arc: C7 H02W0601
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D2 Q2
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0001
|
|
arc: D5 V00B0000
|
|
arc: D6 H02E0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 F4
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F6
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 0100000000000000
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 0000100000000000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0110101010101010
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C80:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C86:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C88:PLC2
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 W1_H02E0401
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0701 F7
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
word: SLICED.K0.INIT 0000111100001111
|
|
word: SLICED.K1.INIT 0000111100001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R29C8:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: A0 S1_V02N0701
|
|
arc: A5 H02E0701
|
|
arc: A7 H02E0501
|
|
arc: B2 H00L0000
|
|
arc: B3 H02E0301
|
|
arc: B4 H00R0000
|
|
arc: B6 V00B0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
word: SLICED.K1.INIT 1001100110011010
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICEC.K1.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C9:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: A2 N1_V02S0701
|
|
arc: A5 H02E0701
|
|
arc: A7 H02E0501
|
|
arc: B0 V00T0000
|
|
arc: B1 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B4 H00R0000
|
|
arc: B6 V00B0000
|
|
word: SLICED.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 1001100110011100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R2C15:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: D2 V02N0201
|
|
arc: F2 F2_SLICE
|
|
arc: N1_V01N0001 F2
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
|
|
.tile R2C27:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R2C28:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
|
|
.tile R2C33:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R2C34:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R2C40:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R2C41:PLC2
|
|
arc: E1_H02E0201 V06N0103
|
|
|
|
.tile R2C42:PLC2
|
|
arc: D1 H02E0201
|
|
arc: F1 F1_SLICE
|
|
arc: N1_V02N0301 F1
|
|
word: SLICEA.K1.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R2C46:PLC2
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
|
|
.tile R2C47:PLC2
|
|
arc: D3 V02N0001
|
|
arc: F3 F3_SLICE
|
|
arc: N1_V02N0301 F3
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R2C48:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R30C10:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R30C11:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: V00B0100 H02W0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 W1_H02E0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 S1_V02N0301
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B1 E1_H02W0101
|
|
arc: B3 Q3
|
|
arc: B4 N1_V01S0000
|
|
arc: B7 F3
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 V02N0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 V02S0001
|
|
arc: C7 V02S0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 V02N0201
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 E1_H01W0100
|
|
arc: D7 F0
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M5 H02W0001
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0301 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K1.INIT 0000001000000000
|
|
word: SLICEA.K0.INIT 1010101010101000
|
|
word: SLICEB.K1.INIT 0000101000100010
|
|
word: SLICED.K1.INIT 0010001100000000
|
|
word: SLICEC.K0.INIT 1011101011111111
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R30C12:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A3 F7
|
|
arc: A4 F5
|
|
arc: A5 Q5
|
|
arc: A6 V02S0301
|
|
arc: A7 N1_V02S0101
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: B4 H02E0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 F3
|
|
arc: B7 H02W0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 N1_V01N0001
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V02N0001
|
|
arc: C5 N1_V02S0201
|
|
arc: C6 H01E0001
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 N1_V02S0201
|
|
arc: D3 V00T0100
|
|
arc: D4 V02S0601
|
|
arc: D5 H02W0201
|
|
arc: D6 V00B0000
|
|
arc: D7 N1_V02S0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F0
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N3_V06N0303 F6
|
|
arc: V00B0000 F4
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEC.K1.INIT 1100110011001000
|
|
word: SLICED.K1.INIT 0000111100000111
|
|
word: SLICEB.K1.INIT 0000100000001010
|
|
word: SLICEC.K0.INIT 0000100000001010
|
|
word: SLICED.K0.INIT 1010111110001101
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R30C13:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: CE1 H00R0000
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q6
|
|
arc: M3 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C14:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02S0101
|
|
arc: A2 V00T0000
|
|
arc: B0 H01W0100
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0101
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V01S0100
|
|
arc: D2 H02E0201
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q1
|
|
word: SLICEB.K0.INIT 1011000011110000
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111100110011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R30C15:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A2 E1_H01E0001
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 V02S0301
|
|
arc: C1 N1_V01N0001
|
|
arc: C2 V02S0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 N1_V02S0201
|
|
arc: D2 F0
|
|
arc: E1_H01E0001 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1101110011111111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R30C16:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 N1_V02S0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C17:PLC2
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00T0100 V02N0501
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0701 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C18:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
|
|
.tile R30C19:PLC2
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: B0 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: C0 S1_V02N0601
|
|
arc: C3 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D3 H02E0201
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEB.K1.INIT 1111110000110000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C20:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00L0100 H02E0101
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: S3_V06S0303 Q6
|
|
arc: V00B0000 Q6
|
|
arc: V01S0100 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C21:PLC2
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A1 V02N0701
|
|
arc: A4 H02W0501
|
|
arc: B1 E1_H01W0100
|
|
arc: C1 S1_V02N0401
|
|
arc: C4 H01E0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 N1_V02S0401
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0103 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 F1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W1_H02W0101 F1
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K1.INIT 1011100010111000
|
|
word: SLICEC.K0.INIT 1010111110100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C22:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 V02N0701
|
|
arc: A2 F5
|
|
arc: B0 V01N0001
|
|
arc: B2 V02S0301
|
|
arc: B4 H00L0000
|
|
arc: B5 H02W0301
|
|
arc: C0 V02N0601
|
|
arc: C2 F4
|
|
arc: C3 H00L0000
|
|
arc: C5 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0401
|
|
arc: D5 W1_H02E0201
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q0
|
|
arc: M1 H00R0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0003 F3
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0601 F4
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q5
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEC.K1.INIT 0000000000000011
|
|
word: SLICEC.K0.INIT 1111111100110011
|
|
word: SLICEA.K0.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1101110111011111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R30C23:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: V00B0000 H02W0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 H00R0000
|
|
arc: C0 W1_H02E0601
|
|
arc: CE0 V02S0201
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR1 H02W0301
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0100 Q5
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C24:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A0 H00R0000
|
|
arc: A4 V00T0100
|
|
arc: A7 N1_V01S0100
|
|
arc: B2 V02S0101
|
|
arc: B3 H02E0301
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C25:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 V02S0501
|
|
arc: A2 V00T0000
|
|
arc: A4 H02W0701
|
|
arc: A7 E1_H02W0501
|
|
arc: B3 H00R0000
|
|
arc: B5 H00L0000
|
|
arc: B6 N1_V01S0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0101 Q1
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C26:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 V02S0501
|
|
arc: A4 V00B0000
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 H02E0501
|
|
arc: A7 E1_H02W0501
|
|
arc: B4 H01E0101
|
|
arc: B5 H02E0101
|
|
arc: B6 V02N0701
|
|
arc: B7 H02E0101
|
|
arc: C4 H01E0001
|
|
arc: C5 N1_V02S0001
|
|
arc: C6 F4
|
|
arc: C7 N1_V02S0001
|
|
arc: CE0 H02W0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H00R0100
|
|
arc: D5 H02W0001
|
|
arc: D6 H01W0000
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F7
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q3
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICED.K1.INIT 0100000000000000
|
|
word: SLICEC.K1.INIT 0000010000000000
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 0000000000010000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C27:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A1 H00L0100
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 H02E0001
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: N3_V06N0103 Q1
|
|
arc: S1_V02S0101 Q1
|
|
word: SLICEA.K0.INIT 0011000000000000
|
|
word: SLICEA.K1.INIT 0011000000110010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R30C28:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 H02E0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A2 V00T0000
|
|
arc: A4 F5
|
|
arc: B2 H00R0000
|
|
arc: B3 V02N0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02S0501
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 H00L0000
|
|
arc: C3 F4
|
|
arc: C4 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D2 V00B0100
|
|
arc: D3 H02E0001
|
|
arc: D4 V00B0000
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q0
|
|
arc: M2 H02E0601
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0203 Q7
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000000010111010
|
|
word: SLICEB.K1.INIT 0000001100000000
|
|
word: SLICEC.K1.INIT 1100110000000000
|
|
word: SLICEC.K0.INIT 0100010100000101
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R30C29:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: A0 F7
|
|
arc: B0 V01N0001
|
|
arc: B7 V00B0100
|
|
arc: C0 H02E0401
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D7 V02N0601
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N3_V06N0003 Q0
|
|
arc: V00B0100 Q5
|
|
word: SLICED.K1.INIT 1111110000001100
|
|
word: SLICEA.K0.INIT 0000000010101100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C2:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M3 H01W0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: V01S0100 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C30:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: A0 H00L0100
|
|
arc: A1 H02W0501
|
|
arc: A6 H02W0501
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 S1_V02N0301
|
|
arc: B6 F3
|
|
arc: C0 H00L0000
|
|
arc: C1 W1_H02E0601
|
|
arc: C3 H00L0000
|
|
arc: C6 N1_V02S0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 N1_V02S0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D6 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0301 F3
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 F6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0010101010101010
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICEA.K0.INIT 0000110100001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R30C31:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 F5
|
|
arc: A1 H00L0100
|
|
arc: A2 H02E0501
|
|
arc: A3 H02W0701
|
|
arc: B0 H02E0101
|
|
arc: B1 V00B0000
|
|
arc: B2 H02W0301
|
|
arc: B3 H00R0100
|
|
arc: B4 H02E0301
|
|
arc: B5 H02W0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H02E0601
|
|
arc: C2 V02S0401
|
|
arc: C3 V02N0401
|
|
arc: C4 H02W0601
|
|
arc: C5 F4
|
|
arc: C6 V00T0100
|
|
arc: C7 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D1 H02W0001
|
|
arc: D2 V00B0100
|
|
arc: D3 V00T0100
|
|
arc: D4 V00B0000
|
|
arc: D5 H02W0201
|
|
arc: D6 V02N0601
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0601 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F7
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: V00T0100 Q1
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEC.K0.INIT 0000000011000000
|
|
word: SLICEB.K0.INIT 1000110010101111
|
|
word: SLICEC.K1.INIT 0000000000110000
|
|
word: SLICEB.K1.INIT 0010000000110011
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1110101011101110
|
|
word: SLICEA.K1.INIT 0001000111110001
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R30C32:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A2 H02E0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A6 F7
|
|
arc: B2 E1_H02W0301
|
|
arc: B6 F3
|
|
arc: B7 H01E0101
|
|
arc: C0 H02E0601
|
|
arc: C2 H00L0100
|
|
arc: C7 E1_H02W0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D6 H02E0201
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 Q2
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F3
|
|
arc: N3_V06N0003 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 0000000010101010
|
|
word: SLICED.K0.INIT 0000000000010001
|
|
word: SLICEB.K0.INIT 0011000000110010
|
|
word: SLICED.K1.INIT 0000001100110011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R30C33:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: A1 F5
|
|
arc: A2 V00B0000
|
|
arc: A3 W1_H02E0701
|
|
arc: A6 V00T0100
|
|
arc: A7 F5
|
|
arc: B0 H02E0301
|
|
arc: B1 F3
|
|
arc: B6 H01E0101
|
|
arc: B7 V02N0501
|
|
arc: C2 V02N0601
|
|
arc: C5 H02E0401
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 H02E0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 H01E0101
|
|
arc: D2 F0
|
|
arc: D3 H02E0001
|
|
arc: D5 F0
|
|
arc: D6 H00R0100
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H00R0000 F6
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0100 F3
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
word: SLICEC.K1.INIT 0000000011110000
|
|
word: SLICEA.K1.INIT 0001000100000000
|
|
word: SLICED.K1.INIT 0000000011111110
|
|
word: SLICEB.K0.INIT 0000000000000101
|
|
word: SLICED.K0.INIT 0000010000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C34:PLC2
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 H00L0000
|
|
arc: B0 V02N0301
|
|
arc: C0 V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: M0 H02E0601
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0201 F0
|
|
arc: V01S0000 Q6
|
|
word: SLICEA.K0.INIT 1011101011111010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C35:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A1 S1_V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A7 V02N0301
|
|
arc: B1 H00R0100
|
|
arc: B2 V02N0101
|
|
arc: B7 V02N0701
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 H00L0000
|
|
arc: C7 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 S1_V02N0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F0
|
|
arc: LSR0 H02E0501
|
|
arc: M0 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0201 F0
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 F7
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0100000001000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C36:PLC2
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: A0 V02N0701
|
|
arc: C0 E1_H01W0000
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C37:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: A0 H02W0501
|
|
arc: A3 V01N0101
|
|
arc: A4 V00B0000
|
|
arc: A5 V02N0301
|
|
arc: B2 V01N0001
|
|
arc: B6 H01E0101
|
|
arc: B7 V02N0501
|
|
arc: E1_H01E0101 F7
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F3
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R30C38:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 V01N0101
|
|
arc: A2 V00B0000
|
|
arc: A4 V02S0101
|
|
arc: A6 E1_H01W0000
|
|
arc: B1 V01N0001
|
|
arc: B3 V02N0301
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 V02N0701
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F2
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0000 F3
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R30C39:PLC2
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: A7 N1_V01N0101
|
|
arc: B0 V02S0301
|
|
arc: B1 H00R0100
|
|
arc: B4 H02E0301
|
|
arc: B5 F1
|
|
arc: B7 N1_V01S0000
|
|
arc: C4 H02E0601
|
|
arc: C5 V02S0001
|
|
arc: C7 E1_H01E0101
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0601
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q5
|
|
arc: N1_V02N0201 F0
|
|
arc: V01S0000 F7
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 1100110011110000
|
|
word: SLICEC.K1.INIT 1111000011001100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C3:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: V00B0000 H02E0601
|
|
arc: A0 V02S0701
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: B0 N1_V02S0101
|
|
arc: B5 V02S0701
|
|
arc: B6 V02S0501
|
|
arc: C0 H00L0000
|
|
arc: C5 N1_V02S0201
|
|
arc: C6 Q6
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 F0
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 H02E0601
|
|
arc: M2 H02E0601
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICEA.K0.INIT 0000001010001010
|
|
word: SLICEC.K1.INIT 1111111000000000
|
|
word: SLICED.K0.INIT 0000000010100010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C40:PLC2
|
|
arc: H00R0100 H02E0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02W0701
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V01S0000 Q2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C41:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile R30C44:PLC2
|
|
arc: N1_V02N0401 H06E0203
|
|
|
|
.tile R30C46:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R30C4:PLC2
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 H02W0701
|
|
arc: A5 Q5
|
|
arc: B0 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: B5 V01S0000
|
|
arc: C0 N1_V02S0601
|
|
arc: C2 N1_V01N0001
|
|
arc: C5 E1_H01E0101
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D2 Q2
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F2
|
|
word: SLICEB.K0.INIT 0000001000010011
|
|
word: SLICEA.K0.INIT 0000101100001111
|
|
word: SLICEC.K1.INIT 0010000000110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R30C52:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R30C58:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R30C5:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0303 V06N0303
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V02S0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00T0100
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H02W0001
|
|
arc: M3 H00L0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0701 Q5
|
|
arc: V00T0100 Q3
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C64:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R30C6:PLC2
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 V02S0501
|
|
arc: A2 V02S0501
|
|
arc: A6 N1_V01N0101
|
|
arc: B0 N1_V02S0101
|
|
arc: B2 N1_V02S0101
|
|
arc: B6 V02S0701
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 H00L0000
|
|
arc: C6 Q6
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 S1_V02N0001
|
|
arc: D6 F2
|
|
arc: E1_H01E0001 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 F0
|
|
arc: V01S0000 Q7
|
|
word: SLICEB.K0.INIT 1111111000000000
|
|
word: SLICEA.K0.INIT 0000100000101010
|
|
word: SLICED.K0.INIT 0101000100000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C70:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R30C76:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R30C7:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A7 V02N0101
|
|
arc: B7 S1_V02N0501
|
|
arc: C7 V00B0100
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0301 Q1
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 F7
|
|
arc: M1 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K1.INIT 0000000010000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C82:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R30C88:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
|
|
.tile R30C8:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 H00L0000
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A5 Q5
|
|
arc: A6 F5
|
|
arc: A7 Q7
|
|
arc: B0 N1_V02S0301
|
|
arc: B2 H02E0301
|
|
arc: B3 Q3
|
|
arc: B5 V02S0501
|
|
arc: B6 F3
|
|
arc: B7 N1_V02S0701
|
|
arc: C0 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 V00B0100
|
|
arc: C6 V02N0001
|
|
arc: C7 H01E0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 V02S0001
|
|
arc: D3 F0
|
|
arc: D5 F2
|
|
arc: D6 V02S0601
|
|
arc: D7 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0000
|
|
arc: M3 H02W0201
|
|
arc: M5 H02E0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0303 F6
|
|
arc: V00B0100 F7
|
|
word: SLICEA.K0.INIT 0000000010111111
|
|
word: SLICED.K1.INIT 0000000000011101
|
|
word: SLICEB.K0.INIT 1101111100000000
|
|
word: SLICEC.K1.INIT 0000101100000000
|
|
word: SLICEB.K1.INIT 0000110100000000
|
|
word: SLICED.K0.INIT 1110111000001111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R30C9:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: A1 E1_H01E0001
|
|
arc: A5 N1_V02S0301
|
|
arc: B1 Q1
|
|
arc: B5 V00B0100
|
|
arc: C1 W1_H02E0401
|
|
arc: C5 N1_V02S0201
|
|
arc: CE0 H00L0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V02S0001
|
|
arc: D5 W1_H02E0201
|
|
arc: E1_H01E0001 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 F1
|
|
arc: M1 W1_H02E0001
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0100 Q5
|
|
word: SLICEA.K1.INIT 0000010100000011
|
|
word: SLICEC.K1.INIT 1000101010101010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C10:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: A0 F5
|
|
arc: A5 V02N0301
|
|
arc: A7 V02N0301
|
|
arc: B0 N1_V02S0301
|
|
arc: B5 V01S0000
|
|
arc: B7 V00B0100
|
|
arc: C0 H00R0100
|
|
arc: C5 E1_H02W0601
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D5 V01N0001
|
|
arc: D7 N1_V02S0401
|
|
arc: E1_H02E0101 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 F0
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q6
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q1
|
|
word: SLICEC.K1.INIT 1000101000000000
|
|
word: SLICED.K1.INIT 0100000001010000
|
|
word: SLICEA.K0.INIT 1100100011111011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C11:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A4 N1_V02S0101
|
|
arc: B0 V00T0000
|
|
arc: B4 H02E0101
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 V02N0401
|
|
arc: C4 Q4
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0201
|
|
arc: D4 W1_H02E0201
|
|
arc: E1_H01E0001 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q7
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1111000011111111
|
|
word: SLICEC.K0.INIT 0010001000001010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C12:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 V02N0501
|
|
arc: A2 F7
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B2 H00L0000
|
|
arc: B7 H02W0101
|
|
arc: C0 H02E0401
|
|
arc: C2 N1_V02S0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D2 F0
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 1010101010101000
|
|
word: SLICED.K1.INIT 0000110001000100
|
|
word: SLICEB.K0.INIT 0100010100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R31C13:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 V01N0101
|
|
arc: A4 V02N0301
|
|
arc: A5 H02E0701
|
|
arc: A7 F5
|
|
arc: B0 V01N0001
|
|
arc: B2 V02N0301
|
|
arc: B4 V01S0000
|
|
arc: B5 V00B0100
|
|
arc: B7 V00T0000
|
|
arc: C0 H02E0601
|
|
arc: C2 H02E0401
|
|
arc: C4 H02E0601
|
|
arc: C5 V02N0001
|
|
arc: C7 N1_V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 Q2
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V02N0401
|
|
arc: D7 F0
|
|
arc: E1_H01E0001 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: V00B0000 F4
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q1
|
|
word: SLICEC.K0.INIT 1000101000000000
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0010001000000010
|
|
word: SLICEC.K1.INIT 1101000000000000
|
|
word: SLICED.K1.INIT 1110000011101111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C14:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 H00L0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0100 F0
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C15:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B2 N1_V02S0101
|
|
arc: B5 V02S0701
|
|
arc: B7 W1_H02E0301
|
|
arc: C2 S1_V02N0401
|
|
arc: C5 E1_H01E0101
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 H00L0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0201
|
|
arc: D5 H02E0001
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M2 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0701 F5
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F7
|
|
word: SLICED.K1.INIT 0010001100110011
|
|
word: SLICEB.K0.INIT 0001000100000011
|
|
word: SLICEC.K1.INIT 0000100000001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C16:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A0 H01E0001
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 F7
|
|
arc: A7 Q7
|
|
arc: B0 V01N0001
|
|
arc: B3 Q3
|
|
arc: B4 V01S0000
|
|
arc: B5 V00B0100
|
|
arc: B7 N1_V02S0501
|
|
arc: C0 N1_V02S0601
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 H00L0100
|
|
arc: C4 V02N0001
|
|
arc: C5 F4
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 F0
|
|
arc: D7 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0303 F5
|
|
arc: V01S0000 Q4
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICED.K1.INIT 0000101100000000
|
|
word: SLICEC.K0.INIT 1101000000000000
|
|
word: SLICEC.K1.INIT 1100100011111011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C17:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 H02E0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: B2 H00R0000
|
|
arc: B3 Q3
|
|
arc: C2 N1_V01N0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 W1_H02E0201
|
|
arc: F2 F5B_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 F2
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: S1_V02S0401 Q4
|
|
word: SLICEB.K0.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C18:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 H02W0701
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A3 N1_V02S0701
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: C0 H02E0401
|
|
arc: C1 N1_V01N0001
|
|
arc: C3 H02W0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 H02E0201
|
|
arc: D3 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0101 F3
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 1101000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C19:PLC2
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A1 V02S0701
|
|
arc: A2 V00B0000
|
|
arc: B0 H02E0101
|
|
arc: C0 V02N0401
|
|
arc: C1 H02E0401
|
|
arc: C2 N1_V01N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D2 H02E0001
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1010101011110000
|
|
word: SLICEB.K0.INIT 1111010110100000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C20:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0100 H02E0301
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0701 Q5
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C21:PLC2
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A5 F7
|
|
arc: A7 H00L0000
|
|
arc: B5 H00R0000
|
|
arc: C0 H00L0000
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V02N0201
|
|
arc: C7 E1_H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F0
|
|
arc: M0 V00B0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M5 V01S0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 Q1
|
|
word: SLICED.K1.INIT 1111010111110101
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 0000001101010111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C22:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 H01E0001
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: A3 N1_V02S0501
|
|
arc: A6 N1_V01N0101
|
|
arc: B0 H02W0301
|
|
arc: B3 Q3
|
|
arc: B6 V02N0701
|
|
arc: C0 E1_H01W0000
|
|
arc: C3 V02N0601
|
|
arc: C6 V02N0201
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D3 V00B0100
|
|
arc: D6 V01N0001
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M2 V00T0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F3
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 Q5
|
|
word: SLICEB.K1.INIT 1101000011011101
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C23:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: B0 H01W0100
|
|
arc: B1 V02S0301
|
|
arc: C0 H02W0601
|
|
arc: C1 H00L0100
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 S1_V02N0001
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q7
|
|
arc: LSR1 H02W0301
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q6
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C24:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 V00T0000
|
|
arc: A7 V02N0301
|
|
arc: B0 H02E0301
|
|
arc: B1 H02W0101
|
|
arc: B2 H02E0301
|
|
arc: B3 H00R0000
|
|
arc: B7 H02E0301
|
|
arc: C0 H02E0601
|
|
arc: C1 H00L0100
|
|
arc: C3 N1_V01S0100
|
|
arc: C7 V01N0101
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 H01E0101
|
|
arc: D2 H02W0001
|
|
arc: D3 V00B0100
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F7
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q5
|
|
arc: W1_H02W0501 Q5
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K1.INIT 1010001011000000
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1111110000001100
|
|
word: SLICEB.K0.INIT 1011101110001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C25:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A0 V02S0501
|
|
arc: A2 H02E0501
|
|
arc: A3 V00T0000
|
|
arc: B2 V02S0101
|
|
arc: B4 V02N0701
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 H00L0000
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 H02W0601
|
|
arc: C4 V00T0100
|
|
arc: C5 E1_H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 H01E0101
|
|
arc: D4 N1_V02S0601
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0101 Q3
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0301
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M6 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q5
|
|
arc: S1_V02S0201 Q0
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q6
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEC.K0.INIT 1100111111000000
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C26:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: B0 H02W0101
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: E1_H01E0001 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q5
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C27:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R31C28:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: A0 F7
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B7 N1_V02S0701
|
|
arc: C0 S1_V02N0401
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: E1_H01E0001 Q3
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H02W0001
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICED.K1.INIT 1100101011001010
|
|
word: SLICEA.K0.INIT 0000000010101100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C29:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: B2 S1_V02N0101
|
|
arc: C2 H02E0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02W0001
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0201 Q2
|
|
arc: V00T0100 Q1
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R31C2:PLC2
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
|
|
.tile R31C30:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: B3 Q3
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D3 V02N0201
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M3 H02W0201
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0301 F3
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q5
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C31:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A1 H00L0100
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 V00T0000
|
|
arc: B4 E1_H02W0301
|
|
arc: C1 H02W0401
|
|
arc: C5 V00T0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D4 H02E0001
|
|
arc: D5 V02N0601
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 F4
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
word: SLICEC.K1.INIT 0000000000001111
|
|
word: SLICEA.K1.INIT 0000110000001110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C32:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 V02N0701
|
|
arc: A3 H01E0001
|
|
arc: A5 E1_H02W0501
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 S1_V02N0101
|
|
arc: B5 H02E0301
|
|
arc: C1 H00L0100
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C5 E1_H02W0401
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 N1_V02S0201
|
|
arc: D3 H02E0201
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F5
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00B0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEB.K0.INIT 1111111110000000
|
|
word: SLICEB.K1.INIT 1111001101010001
|
|
word: SLICEA.K0.INIT 0100010000000000
|
|
word: SLICEA.K1.INIT 0100111100001111
|
|
word: SLICEC.K1.INIT 0000010000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C33:PLC2
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A1 V02N0701
|
|
arc: A2 H00L0100
|
|
arc: A3 E1_H01E0001
|
|
arc: B1 V02N0301
|
|
arc: B3 Q3
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 F4
|
|
arc: C3 H02E0401
|
|
arc: C4 H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D2 H01E0101
|
|
arc: D3 H01E0101
|
|
arc: D4 V00B0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0401 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 F0
|
|
arc: M0 V00T0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEB.K0.INIT 1111111110100000
|
|
word: SLICEB.K1.INIT 1111111111111000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000100000000000
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R31C34:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
arc: A0 H00L0100
|
|
arc: A1 E1_H01E0001
|
|
arc: A4 V02N0101
|
|
arc: A5 F7
|
|
arc: A6 V00T0100
|
|
arc: B0 H01W0100
|
|
arc: B6 V02N0501
|
|
arc: B7 F3
|
|
arc: C0 H02E0401
|
|
arc: C2 H02E0601
|
|
arc: C3 E1_H02W0401
|
|
arc: C6 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 F2
|
|
arc: D2 H00R0000
|
|
arc: D3 F2
|
|
arc: D4 V02N0601
|
|
arc: D5 H00R0100
|
|
arc: D6 V02N0401
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 F6
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0601 Q4
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0401 F4
|
|
word: SLICEA.K1.INIT 0101010111111111
|
|
word: SLICEB.K1.INIT 0000111111111111
|
|
word: SLICEC.K0.INIT 1111111110101010
|
|
word: SLICEB.K0.INIT 0000000011110000
|
|
word: SLICED.K1.INIT 0011001100000000
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1111010001000100
|
|
word: SLICEC.K1.INIT 0101010111111111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C35:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 E1_H01E0001
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 V02N0301
|
|
arc: A6 F7
|
|
arc: B0 H02E0101
|
|
arc: B2 H02E0301
|
|
arc: B4 H01E0101
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 H01E0101
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 F4
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0601
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 V00T0000
|
|
arc: C6 V02N0001
|
|
arc: C7 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 F2
|
|
arc: D2 S1_V02N0001
|
|
arc: D4 V01N0001
|
|
arc: D5 V00B0000
|
|
arc: D6 H00R0100
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 F1
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0601 F6
|
|
word: SLICED.K0.INIT 0100000000000000
|
|
word: SLICEC.K0.INIT 0101111100010011
|
|
word: SLICEB.K0.INIT 1111111000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010111100000000
|
|
word: SLICEC.K1.INIT 0000100010000000
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
word: SLICEA.K0.INIT 0010111100101111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R31C36:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A1 F5
|
|
arc: A2 H01E0001
|
|
arc: A5 V00B0000
|
|
arc: A6 F7
|
|
arc: A7 H02W0501
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 W1_H02E0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B7 H01E0101
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 H00L0100
|
|
arc: C4 H01E0001
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 F4
|
|
arc: C7 S1_V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D4 V02N0601
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 E1_H02W0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00T0000
|
|
arc: M2 N1_V01N0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V02N0201 F0
|
|
arc: N3_V06N0003 F0
|
|
arc: N3_V06N0303 F6
|
|
arc: V01S0000 F1
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0303 F6
|
|
word: SLICED.K1.INIT 0000000011010001
|
|
word: SLICED.K0.INIT 0000101000000000
|
|
word: SLICEC.K1.INIT 0101000100000000
|
|
word: SLICEA.K1.INIT 1010000000100010
|
|
word: SLICEC.K0.INIT 0000000011110000
|
|
word: SLICEB.K0.INIT 1111000011100000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111111111001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R31C37:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A1 V02S0501
|
|
arc: A4 V00T0000
|
|
arc: B0 H01W0100
|
|
arc: B1 H01W0100
|
|
arc: B2 H01W0100
|
|
arc: B3 H01W0100
|
|
arc: B4 V01S0000
|
|
arc: C0 V02N0601
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V00T0100
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 V00B0100
|
|
arc: D2 H02W0201
|
|
arc: D3 V02N0201
|
|
arc: D4 H01W0000
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q1
|
|
word: SLICEC.K0.INIT 0000000000000010
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1110111000100010
|
|
word: SLICEB.K0.INIT 1100111100000011
|
|
word: SLICEB.K1.INIT 1111110000110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C38:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 V02S0501
|
|
arc: A1 N1_V02S0701
|
|
arc: A3 H02E0501
|
|
arc: A5 F7
|
|
arc: A7 H00L0000
|
|
arc: B2 S1_V02N0301
|
|
arc: B5 H01E0101
|
|
arc: B7 V00T0000
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C5 H02W0601
|
|
arc: C7 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 V00B0100
|
|
arc: D3 V02S0201
|
|
arc: D5 N1_V02S0601
|
|
arc: D7 W1_H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q1
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q3
|
|
arc: W1_H02W0501 F5
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 1100111111000000
|
|
word: SLICEB.K1.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICEA.K1.INIT 1010111110100000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C39:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: B1 N1_V02S0101
|
|
arc: C1 W1_H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02S0001
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
word: SLICEA.K1.INIT 1100111111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C3:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
|
|
.tile R31C40:PLC2
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
|
|
.tile R31C41:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R31C44:PLC2
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R31C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R31C4:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: A2 S1_V02N0501
|
|
arc: B0 V02N0101
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V02N0001
|
|
arc: E1_H01E0001 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K0.INIT 0101010100000000
|
|
word: SLICEA.K0.INIT 0000000011001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R31C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R31C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R31C5:PLC2
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A2 N1_V02S0501
|
|
arc: A3 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: A7 H02E0701
|
|
arc: B0 V01N0001
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B4 V02S0501
|
|
arc: B7 F3
|
|
arc: C0 V02S0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 F4
|
|
arc: C4 Q4
|
|
arc: C7 N1_V02S0001
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 H00R0000
|
|
arc: D2 H02W0201
|
|
arc: D3 F2
|
|
arc: D4 E1_H02W0201
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00B0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 F0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEC.K0.INIT 0000000011110111
|
|
word: SLICEB.K0.INIT 1101000000000000
|
|
word: SLICEB.K1.INIT 0000000001011111
|
|
word: SLICED.K1.INIT 1111001110100011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C6:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: B0 V01N0001
|
|
arc: B2 E1_H02W0301
|
|
arc: C2 V02N0401
|
|
arc: C3 E1_H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 V02N0201
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
word: SLICEB.K1.INIT 1111111100001111
|
|
word: SLICEA.K0.INIT 0000000011001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R31C71:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C7:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A2 F5
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B2 H00R0100
|
|
arc: B5 E1_H02W0101
|
|
arc: B7 V00T0000
|
|
arc: C2 H02E0401
|
|
arc: C5 N1_V02S0001
|
|
arc: C7 N1_V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 Q2
|
|
arc: D5 V01N0001
|
|
arc: D7 E1_H02W0201
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0001 F2
|
|
word: SLICED.K1.INIT 0011000001010000
|
|
word: SLICEC.K1.INIT 1111111000000000
|
|
word: SLICEB.K0.INIT 0010001000000010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C8:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0303 N3_V06S0303
|
|
arc: A0 E1_H01E0001
|
|
arc: A3 N1_V02S0701
|
|
arc: B0 H02E0301
|
|
arc: B3 Q3
|
|
arc: C0 N1_V02S0401
|
|
arc: C3 H02E0401
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: E1_H01E0001 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M3 H02E0201
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0001 F0
|
|
arc: V00T0100 F3
|
|
word: SLICEB.K1.INIT 1101000000000000
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C9:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 N1_V02S0501
|
|
arc: A4 F7
|
|
arc: A7 Q7
|
|
arc: B2 H00L0000
|
|
arc: B4 V02S0701
|
|
arc: B7 N1_V02S0701
|
|
arc: C1 F4
|
|
arc: C2 W1_H02E0401
|
|
arc: C4 Q4
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 N1_V02S0201
|
|
arc: D4 H02W0201
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F1
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K1.INIT 0000010000000111
|
|
word: SLICEB.K0.INIT 0000110100001111
|
|
word: SLICEC.K0.INIT 0100000001000100
|
|
word: SLICEA.K1.INIT 0000010100001111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C10:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A2 H02E0501
|
|
arc: A4 F5
|
|
arc: A5 H02E0501
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 Q7
|
|
arc: B1 Q1
|
|
arc: B2 H02E0301
|
|
arc: B4 V01S0000
|
|
arc: B5 H02E0101
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02W0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 H02W0601
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H02E0001
|
|
arc: D2 Q2
|
|
arc: D4 H00R0100
|
|
arc: D5 V01N0001
|
|
arc: D6 F2
|
|
arc: D7 V02S0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 F4
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F0
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEB.K0.INIT 1111000011100000
|
|
word: SLICED.K0.INIT 0010001100000000
|
|
word: SLICEC.K1.INIT 0000111100000111
|
|
word: SLICED.K1.INIT 0000000100110001
|
|
word: SLICEC.K0.INIT 0000000010001010
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111110000001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C11:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A3 F5
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 Q1
|
|
arc: B3 Q3
|
|
arc: B5 V02N0501
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 N1_V01S0100
|
|
arc: C3 H02W0401
|
|
arc: C5 V02S0201
|
|
arc: C7 V02S0201
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 W1_H02E0201
|
|
arc: D3 V00B0100
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M3 H00L0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H02W0001
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q4
|
|
arc: V00B0100 F7
|
|
word: SLICED.K1.INIT 1100110011001000
|
|
word: SLICEC.K1.INIT 0101001100000000
|
|
word: SLICEB.K1.INIT 0100010100000000
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C12:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A0 V01N0101
|
|
arc: A2 V02S0501
|
|
arc: A5 F7
|
|
arc: A7 Q7
|
|
arc: B1 Q1
|
|
arc: B2 H02W0301
|
|
arc: B7 W1_H02E0101
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 H00L0000
|
|
arc: C5 H01E0001
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 H02E0001
|
|
arc: D5 F2
|
|
arc: D7 H02W0001
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00T0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0701 F5
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICED.K1.INIT 0000000010111111
|
|
word: SLICEB.K0.INIT 1100010000000000
|
|
word: SLICEC.K1.INIT 0000000001011111
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C13:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: A0 H02E0701
|
|
arc: B0 N1_V02S0301
|
|
arc: B3 Q3
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 H02W0401
|
|
arc: C3 V02S0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 H00R0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 F2
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0101 Q1
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1100111111000000
|
|
word: SLICEA.K0.INIT 1111001011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C14:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: C1 H00R0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 V02S0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 F0
|
|
arc: M0 V00T0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0000
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C15:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A1 V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A5 Q5
|
|
arc: A7 F5
|
|
arc: B0 V01N0001
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B5 W1_H02E0101
|
|
arc: B7 V00B0100
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H00R0100
|
|
arc: C2 N1_V01N0001
|
|
arc: C5 S1_V02N0201
|
|
arc: C7 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 F0
|
|
arc: D2 W1_H02E0201
|
|
arc: D5 W1_H02E0001
|
|
arc: D7 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: M1 H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M5 H02W0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q2
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEB.K0.INIT 0000000000011101
|
|
word: SLICEC.K1.INIT 0000000010111111
|
|
word: SLICED.K1.INIT 0000000010001010
|
|
word: SLICEA.K0.INIT 0000001100110011
|
|
word: SLICEA.K1.INIT 1100100011111011
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R32C16:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: B0 H00R0100
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 H00L0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 H02E0201
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F0
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C17:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: A2 V00T0000
|
|
arc: A4 F7
|
|
arc: A7 Q7
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 V02S0101
|
|
arc: B4 V01S0000
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 H02E0601
|
|
arc: C2 V02S0401
|
|
arc: C4 H02W0401
|
|
arc: C7 V02S0201
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D4 F2
|
|
arc: D7 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 F0
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEB.K0.INIT 0001110100000000
|
|
word: SLICED.K1.INIT 1111111000000000
|
|
word: SLICEC.K0.INIT 0000000010001010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C18:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q2
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C19:PLC2
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 V06S0203
|
|
|
|
.tile R32C20:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02S0501
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q4
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 V00B0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N3_V06N0203 Q4
|
|
arc: V01S0100 Q4
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C21:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0000 V02N0201
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00T0100 V02S0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: LSR0 V00T0100
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N3_V06N0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C22:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 V01N0101
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 F5
|
|
arc: A4 V00B0000
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 H02W0501
|
|
arc: A7 V02S0301
|
|
arc: B0 V00T0000
|
|
arc: B1 V02N0101
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 V02N0701
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 H00L0000
|
|
arc: C3 F4
|
|
arc: C4 H02W0401
|
|
arc: C5 V02N0001
|
|
arc: C6 V00B0100
|
|
arc: C7 S1_V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 H02E0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 F2
|
|
arc: D4 V01N0001
|
|
arc: D5 H00R0100
|
|
arc: D6 E1_H02W0001
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M1 H00L0100
|
|
arc: M5 W1_H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0701 F7
|
|
arc: V00B0100 Q5
|
|
arc: V01S0100 Q5
|
|
word: SLICEB.K0.INIT 1010111100100011
|
|
word: SLICEC.K0.INIT 1111010100110001
|
|
word: SLICEC.K1.INIT 1100010011110101
|
|
word: SLICEA.K1.INIT 1101110100001101
|
|
word: SLICEA.K0.INIT 1111010100110001
|
|
word: SLICED.K1.INIT 1111010100110001
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 1000010010100101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R32C23:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 W1_H02E0501
|
|
arc: A2 H00L0100
|
|
arc: A3 V02N0501
|
|
arc: A4 V00T0100
|
|
arc: A5 V00T0000
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 H00R0000
|
|
arc: B2 V01N0001
|
|
arc: B3 H00L0000
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02S0501
|
|
arc: B6 V02S0701
|
|
arc: B7 H02E0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q4
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 1001100110011010
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C24:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 V02N0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02W0501
|
|
arc: A3 V02S0701
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V00B0000
|
|
arc: A6 H00R0000
|
|
arc: A7 N1_V02S0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0301
|
|
arc: B3 H02E0101
|
|
arc: B4 V02S0501
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: B7 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0201 Q0
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: M0 H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M2 H02E0601
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 H02E0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICED.K1.INIT 1001100110011010
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C25:PLC2
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 H02W0501
|
|
arc: B0 V00T0000
|
|
arc: B1 E1_H01W0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 F2
|
|
arc: F2 F2_SLICE
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0301 Q3
|
|
arc: W3_H06W0003 Q3
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1001100110011100
|
|
word: SLICEA.K0.INIT 1001100110011100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C26:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
arc: A3 F5
|
|
arc: A5 Q5
|
|
arc: C2 N1_V01N0001
|
|
arc: C5 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V01S0100
|
|
arc: D3 V00T0100
|
|
arc: D5 H02E0001
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0003 F3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 H02W0601
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M5 W1_H02E0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: V00T0000 F2
|
|
arc: V00T0100 Q3
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 0000000001010000
|
|
word: SLICEB.K1.INIT 0000000010101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C27:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 E1_H01E0001
|
|
arc: A7 N1_V02S0101
|
|
arc: B0 H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICED.K1.INIT 1111111100010001
|
|
word: SLICEA.K0.INIT 1111100010001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C28:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 E1_H01E0001
|
|
arc: B0 H01W0100
|
|
arc: B4 V01S0000
|
|
arc: C0 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D4 W1_H02E0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0003 F3
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0301 F3
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEC.K0.INIT 1111110000001100
|
|
word: SLICEA.K0.INIT 0000000010101100
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C29:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A6 E1_H01W0000
|
|
arc: B0 E1_H02W0101
|
|
arc: B6 V00B0100
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 E1_H02W0601
|
|
arc: C5 E1_H01E0101
|
|
arc: C6 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 V02N0601
|
|
arc: D6 H02W0001
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F7
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K1.INIT 0000000011001100
|
|
word: SLICEA.K0.INIT 1111110011111100
|
|
word: SLICEC.K1.INIT 0000000011110000
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R32C2:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 H02E0201
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: B1 V02N0301
|
|
arc: C0 V02N0401
|
|
arc: C6 V02N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D3 V02N0001
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H01W0100
|
|
arc: M4 V00T0100
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
word: SLICED.K0.INIT 0000111100001111
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R32C30:PLC2
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: A1 F7
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V02N0101
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 E1_H02W0701
|
|
arc: B1 V02N0101
|
|
arc: B2 V02S0301
|
|
arc: B3 H00R0100
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 V02S0701
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 V02N0601
|
|
arc: C1 F4
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 F4
|
|
arc: C6 F4
|
|
arc: C7 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 V02S0201
|
|
arc: D3 V02S0001
|
|
arc: D5 F2
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F4
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 F3
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEC.K0.INIT 1000100010001000
|
|
word: SLICEB.K0.INIT 0001000100110011
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
word: SLICEB.K1.INIT 0000011101110111
|
|
word: SLICED.K1.INIT 0001001101011111
|
|
word: SLICEA.K1.INIT 1100010001000100
|
|
word: SLICEC.K1.INIT 1000000010101010
|
|
word: SLICED.K0.INIT 0001010100111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R32C31:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: C0 V02N0401
|
|
arc: C2 H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D2 E1_H02W0201
|
|
arc: E1_H01E0001 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F2
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C32:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 V00B0000
|
|
arc: A3 F7
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 V02N0301
|
|
arc: B1 H01W0100
|
|
arc: B2 V02S0101
|
|
arc: B3 H01W0100
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0701
|
|
arc: B6 H02E0301
|
|
arc: C0 V02N0601
|
|
arc: C1 F4
|
|
arc: C3 H00L0100
|
|
arc: C4 V00T0000
|
|
arc: C5 F6
|
|
arc: C7 V00B0100
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 H02E0001
|
|
arc: D2 Q2
|
|
arc: D3 F2
|
|
arc: D4 V00B0000
|
|
arc: D5 F2
|
|
arc: D6 H01W0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02W0501
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0301 F1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K0.INIT 0010001000000000
|
|
word: SLICEC.K0.INIT 0000000000000010
|
|
word: SLICEA.K0.INIT 0000101010100000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000010001
|
|
word: SLICEA.K1.INIT 0001000000000000
|
|
word: SLICEB.K1.INIT 0000100000000000
|
|
word: SLICED.K1.INIT 0000010100000101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R32C33:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 H01E0101
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C34:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 V02N0501
|
|
arc: A5 V00B0000
|
|
arc: A6 F7
|
|
arc: A7 V02N0301
|
|
arc: B0 V00T0000
|
|
arc: B2 V02N0301
|
|
arc: B6 V00B0000
|
|
arc: B7 V02N0501
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 V02N0401
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D2 V02N0001
|
|
arc: D4 H00R0100
|
|
arc: D5 W1_H02E0201
|
|
arc: D6 W1_H02E0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 F4
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 F4
|
|
word: SLICED.K0.INIT 0000100010000000
|
|
word: SLICEC.K1.INIT 0000000000001010
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
word: SLICED.K1.INIT 0000000000010000
|
|
word: SLICEB.K0.INIT 0000000000000010
|
|
word: SLICEA.K0.INIT 1110110010100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R32C35:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 H02W0301
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A0 H01E0001
|
|
arc: A1 H00L0000
|
|
arc: A3 H02W0501
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 V00T0100
|
|
arc: B0 F3
|
|
arc: B1 E1_H02W0301
|
|
arc: B3 H02E0301
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 H02W0101
|
|
arc: C0 V02S0401
|
|
arc: C1 H02E0401
|
|
arc: C3 H00L0100
|
|
arc: C6 V00T0100
|
|
arc: C7 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 H01E0101
|
|
arc: D5 V02N0401
|
|
arc: D6 H02E0201
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F1
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEA.K1.INIT 0000000001000000
|
|
word: SLICED.K0.INIT 0000000001110011
|
|
word: SLICED.K1.INIT 0000000010001010
|
|
word: SLICEC.K1.INIT 1010101000000000
|
|
word: SLICEB.K1.INIT 0001000000000000
|
|
word: SLICEA.K0.INIT 1111100010001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R32C36:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0203 E1_H02W0401
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 H00L0100
|
|
arc: A4 F5
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 V02N0301
|
|
arc: B0 V00B0000
|
|
arc: B2 H00L0000
|
|
arc: B4 H00L0000
|
|
arc: B6 N1_V02S0701
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 V02S0401
|
|
arc: C4 H01E0001
|
|
arc: C6 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 W1_H02E0001
|
|
arc: D2 V02N0001
|
|
arc: D4 V02S0401
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 H00L0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 F6
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 Q0
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 F5
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEC.K1.INIT 0000000010101010
|
|
word: SLICED.K0.INIT 1000100010100000
|
|
word: SLICEC.K0.INIT 0000101110111011
|
|
word: SLICEA.K1.INIT 1111111100001010
|
|
word: SLICEA.K0.INIT 0000000000111010
|
|
word: SLICEB.K0.INIT 1111111000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R32C37:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0103 V01N0101
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B0 V00T0000
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00L0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q3
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEA.K0.INIT 1111111100110011
|
|
word: SLICEB.K0.INIT 0000111100000010
|
|
word: SLICEB.K1.INIT 0010110000100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C38:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: A2 H01E0001
|
|
arc: B1 V00B0000
|
|
arc: B2 H01W0100
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 E1_H01W0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D2 V01S0100
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 H02E0301
|
|
arc: M2 V00B0100
|
|
arc: M4 H02W0401
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 Q6
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q7
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 0000000000000100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R32C39:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: A0 H02E0701
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C3:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: H00L0100 H02E0101
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: A0 H00L0100
|
|
arc: A4 E1_H01W0000
|
|
arc: B0 H02E0301
|
|
arc: B4 V01S0000
|
|
arc: B5 V01S0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C4 V00T0000
|
|
arc: C5 V00T0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D4 H02E0001
|
|
arc: D5 E1_H01W0100
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 F4
|
|
arc: N3_V06N0103 Q2
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0100010101000100
|
|
word: SLICEC.K0.INIT 1111111111111000
|
|
word: SLICEC.K1.INIT 1111110011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C40:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: B0 V02N0301
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 0000000011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R32C41:PLC2
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
|
|
.tile R32C42:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R32C43:PLC2
|
|
arc: V00B0100 H02W0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02W0501
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C44:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00R0100 H02W0701
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W1_H02W0701 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C45:PLC2
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02E0501
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W1_H02W0701 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C47:PLC2
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
|
|
.tile R32C4:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: B5 V02S0501
|
|
arc: C0 V02N0601
|
|
arc: C5 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D5 H00R0100
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00B0100 F5
|
|
arc: V01S0000 Q0
|
|
word: SLICEC.K1.INIT 1100110011001111
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C5:PLC2
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 H02E0201
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0101
|
|
arc: B0 H02W0101
|
|
arc: B2 V02N0301
|
|
arc: B3 H02E0101
|
|
arc: B6 V02N0501
|
|
arc: B7 V00B0000
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F4
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F3
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0100 F7
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R32C6:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 H02W0501
|
|
arc: A2 V00T0000
|
|
arc: A5 N1_V01S0100
|
|
arc: A7 H00L0000
|
|
arc: B3 V02N0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B6 V02N0701
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F2
|
|
arc: M0 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q6
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F1
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C7:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A4 V02S0101
|
|
arc: B3 Q3
|
|
arc: B4 H01E0101
|
|
arc: C2 H00L0000
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 Q4
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 V01S0100
|
|
arc: D4 E1_H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F4
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0100 Q6
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1111110000001100
|
|
word: SLICEC.K0.INIT 0000101000100010
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C8:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: B1 Q1
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0001
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0001 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C9:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 F5
|
|
arc: A3 H00L0100
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 Q5
|
|
arc: B0 H02W0301
|
|
arc: B2 F3
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 W1_H02E0101
|
|
arc: C0 H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 V00T0000
|
|
arc: C5 S1_V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 H01E0101
|
|
arc: D3 W1_H02E0201
|
|
arc: D4 F0
|
|
arc: D5 H02W0001
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0001 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: M0 H02W0601
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: V00T0000 F2
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K0.INIT 1101110011111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0100011100000000
|
|
word: SLICEC.K1.INIT 1111111000000000
|
|
word: SLICEB.K0.INIT 0010001000000010
|
|
word: SLICEC.K0.INIT 1100100011111011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C10:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q4
|
|
arc: M0 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C11:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: A0 H01E0001
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 F5
|
|
arc: A4 V02S0301
|
|
arc: A5 V02S0301
|
|
arc: A6 H02W0701
|
|
arc: A7 V02N0101
|
|
arc: B0 V02N0101
|
|
arc: B2 H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 W1_H02E0101
|
|
arc: B6 F3
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 H00L0000
|
|
arc: C2 F4
|
|
arc: C3 N1_V01N0001
|
|
arc: C4 Q4
|
|
arc: C5 H02W0601
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 V00B0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D2 F0
|
|
arc: D3 H02W0201
|
|
arc: D4 V02S0401
|
|
arc: D5 H02E0201
|
|
arc: D6 F2
|
|
arc: D7 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00T0000
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F7
|
|
arc: N3_V06N0303 F6
|
|
arc: V00B0100 Q7
|
|
word: SLICED.K1.INIT 0000000000011011
|
|
word: SLICEC.K1.INIT 0101000101010101
|
|
word: SLICEB.K1.INIT 0000100000001010
|
|
word: SLICEA.K0.INIT 0001110100000000
|
|
word: SLICEC.K0.INIT 1010101010101000
|
|
word: SLICEB.K0.INIT 0000000011010000
|
|
word: SLICED.K0.INIT 1111010111000101
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C12:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H02W0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q1
|
|
arc: H01W0100 Q4
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: W1_H02W0601 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C13:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 V00B0000
|
|
arc: A4 F5
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 N1_V01N0101
|
|
arc: B1 Q1
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 Q3
|
|
arc: B4 F3
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 H02E0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H00R0100
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0001
|
|
arc: C5 V02S0001
|
|
arc: C6 N1_V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 V02N0201
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 N1_V02S0201
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 H02E0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 H00L0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0001 F0
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K1.INIT 0011010100000000
|
|
word: SLICEC.K1.INIT 1111000011100000
|
|
word: SLICEC.K0.INIT 0010000000100010
|
|
word: SLICEB.K0.INIT 1100100011111011
|
|
word: SLICED.K0.INIT 0000010100000011
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C14:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
arc: A0 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: B0 V02N0101
|
|
arc: B2 H00R0000
|
|
arc: B4 H02E0301
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 S1_V02N0601
|
|
arc: C4 V02N0201
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D2 F0
|
|
arc: D4 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q1
|
|
arc: M0 V00T0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 0000000000011101
|
|
word: SLICEC.K0.INIT 0010001100110011
|
|
word: SLICEB.K0.INIT 0000000010001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R33C15:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A2 V00T0000
|
|
arc: A7 Q7
|
|
arc: B2 V02N0101
|
|
arc: B7 S1_V02N0501
|
|
arc: C2 H00L0100
|
|
arc: C7 W1_H02E0601
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0201
|
|
arc: D7 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M4 V00B0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 F7
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEB.K0.INIT 1011000011110000
|
|
word: SLICED.K1.INIT 0000101100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C16:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W3_H06W0103 N3_V06S0103
|
|
|
|
.tile R33C17:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A2 H00L0100
|
|
arc: A4 F7
|
|
arc: A7 Q7
|
|
arc: B2 H01W0100
|
|
arc: B4 V01S0000
|
|
arc: B7 H02E0301
|
|
arc: C2 S1_V02N0401
|
|
arc: C4 W1_H02E0601
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02E0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02N0201
|
|
arc: D4 F2
|
|
arc: D7 W1_H02E0201
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q2
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEB.K0.INIT 0000010100000011
|
|
word: SLICED.K1.INIT 0010001100110011
|
|
word: SLICEC.K0.INIT 0000000010001010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R33C18:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A6 H00L0000
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 E1_H02W0601
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 H02W0201
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1100111111001111
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R33C19:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: A0 S1_V02N0501
|
|
arc: A6 H00L0000
|
|
arc: B6 H02E0301
|
|
arc: C0 H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00L0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 E1_H02W0201
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 1010111110101111
|
|
word: SLICED.K0.INIT 1010101010001000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C20:PLC2
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 H00R0000
|
|
arc: B0 V00T0000
|
|
arc: B1 H02E0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H02E0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1111111111101100
|
|
word: SLICEA.K1.INIT 1111111111101100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET SET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C21:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 H02W0601
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A2 S1_V02N0501
|
|
arc: B0 V02S0301
|
|
arc: C0 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D2 E1_H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N3_V06N0103 F2
|
|
arc: S1_V02S0201 Q0
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K0.INIT 1111111111111100
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C22:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: A0 E1_H02W0701
|
|
arc: A3 V02S0701
|
|
arc: A4 E1_H01W0000
|
|
arc: A7 V02S0301
|
|
arc: B0 E1_H02W0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 H00L0000
|
|
arc: B6 H02W0101
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 H02W0401
|
|
arc: C3 H02W0601
|
|
arc: C4 V02S0001
|
|
arc: C7 V00T0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D3 V00B0100
|
|
arc: D4 E1_H02W0001
|
|
arc: D6 E1_H02W0001
|
|
arc: D7 H02E0201
|
|
arc: E1_H02E0101 Q3
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F0
|
|
arc: LSR0 H02E0301
|
|
arc: M0 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0501 F7
|
|
arc: V00B0000 F6
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0000000000000010
|
|
word: SLICEB.K1.INIT 1000101011001111
|
|
word: SLICED.K0.INIT 0000000011001100
|
|
word: SLICEC.K0.INIT 1000000011000000
|
|
word: SLICEA.K0.INIT 1011000000001011
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
|
|
.tile R33C23:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A3 H02E0701
|
|
arc: C3 E1_H01W0000
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 E1_H02W0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0303 Q6
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 H02W0601
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICEB.K1.INIT 1010101011110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C24:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 F5
|
|
arc: A5 W1_H02E0501
|
|
arc: B0 E1_H02W0301
|
|
arc: B5 V01S0000
|
|
arc: C0 V02N0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D5 H02W0201
|
|
arc: E1_H01E0101 Q3
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0003 Q3
|
|
arc: V01S0000 Q5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEC.K1.INIT 1010101011001100
|
|
word: SLICEA.K0.INIT 0000101000001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C25:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A0 F5
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: B0 V00T0000
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 V02N0401
|
|
arc: C4 S1_V02N0201
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D4 H01W0000
|
|
arc: D5 H01W0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0401 F4
|
|
arc: V00B0000 Q4
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
word: SLICEC.K1.INIT 1100110010101010
|
|
word: SLICEA.K0.INIT 0000101000001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C26:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 F7
|
|
arc: A7 H02E0501
|
|
arc: B0 V00T0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q2
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICED.K1.INIT 1010101011110000
|
|
word: SLICEA.K0.INIT 0000000010101100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C27:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: B0 E1_H02W0101
|
|
arc: C0 V02S0401
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0401 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M3 H01W0100
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C28:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q3
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C29:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0303 H06W0303
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A1 H00L0100
|
|
arc: A3 H02E0501
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 H02W0501
|
|
arc: A7 V02N0301
|
|
arc: B1 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 H02E0101
|
|
arc: B5 H02E0101
|
|
arc: B7 V02S0501
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 V00T0000
|
|
arc: C7 V00B0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 H02E0201
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 V02S0601
|
|
arc: D5 H01W0000
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F7
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: S1_V02S0001 F2
|
|
arc: V00T0100 Q3
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 0000111111111111
|
|
word: SLICEA.K1.INIT 0001001101011111
|
|
word: SLICED.K1.INIT 0001001101011111
|
|
word: SLICEC.K1.INIT 0101111100010011
|
|
word: SLICEC.K0.INIT 0101111100010011
|
|
word: SLICEB.K0.INIT 0000111111111111
|
|
word: SLICEB.K1.INIT 0000011101110111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C2:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: C0 E1_H02W0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M5 V01S0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0501 Q5
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q6
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R33C30:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 H01E0001
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 Q5
|
|
arc: A6 H02E0701
|
|
arc: A7 H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 H01W0100
|
|
arc: B3 H01W0100
|
|
arc: B4 H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C0 H02E0401
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 E1_H01W0000
|
|
arc: C4 V02N0001
|
|
arc: C6 V02S0201
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02W0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D4 H01W0000
|
|
arc: D5 H02E0001
|
|
arc: D6 H02E0001
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M1 V01S0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: S1_V02S0001 Q0
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F4
|
|
word: SLICEB.K0.INIT 1100110010100000
|
|
word: SLICEB.K1.INIT 1100110011111111
|
|
word: SLICEC.K0.INIT 1110110000100000
|
|
word: SLICEC.K1.INIT 1010101011111111
|
|
word: SLICEA.K0.INIT 1100110000001111
|
|
word: SLICED.K0.INIT 1111000001010101
|
|
word: SLICED.K1.INIT 0011001000110000
|
|
word: SLICEA.K1.INIT 1100010001000100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C31:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A0 H02W0501
|
|
arc: A1 H00R0000
|
|
arc: A2 H00L0100
|
|
arc: A7 V00T0100
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C7 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 V02S0001
|
|
arc: D2 V00B0100
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q6
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V00T0000 F2
|
|
arc: V00T0100 Q1
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEB.K0.INIT 1010000011101100
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000010101110
|
|
word: SLICEA.K0.INIT 0010000000101001
|
|
word: SLICED.K1.INIT 0000101000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R33C32:PLC2
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H00R0000
|
|
arc: A2 V02N0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: A6 F5
|
|
arc: A7 F5
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 V02N0501
|
|
arc: B5 N1_V01S0000
|
|
arc: C0 H00L0100
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 V02S0001
|
|
arc: C6 F4
|
|
arc: C7 F4
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D2 H02W0201
|
|
arc: D3 H02W0201
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 V02N0401
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0001 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F4
|
|
arc: LSR1 V00B0000
|
|
arc: M2 E1_H02W0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0001 F0
|
|
arc: V00B0000 F6
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEB.K1.INIT 1100111111111111
|
|
word: SLICEB.K0.INIT 0100010101010101
|
|
word: SLICEC.K1.INIT 0100010001010000
|
|
word: SLICEC.K0.INIT 0101000001000100
|
|
word: SLICEA.K0.INIT 0001000001000100
|
|
word: SLICED.K0.INIT 1111101011111111
|
|
word: SLICED.K1.INIT 1111111111110101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R33C33:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: V00T0100 H02W0301
|
|
arc: A0 H02W0701
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 H00L0000
|
|
arc: C2 E1_H01W0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEA.K0.INIT 1010000011101100
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C34:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A0 F5
|
|
arc: A1 F7
|
|
arc: A3 W1_H02E0501
|
|
arc: A5 V02S0101
|
|
arc: A7 H00L0000
|
|
arc: B0 N1_V02S0301
|
|
arc: B3 E1_H02W0101
|
|
arc: B7 V01S0000
|
|
arc: C0 V02S0401
|
|
arc: C1 F4
|
|
arc: C3 W1_H02E0401
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 F4
|
|
arc: C7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00B0100
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 V02S0401
|
|
arc: D5 H00R0100
|
|
arc: D7 N1_V02S0601
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F2
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 1011101000110000
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 0101000001010101
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000100000
|
|
word: SLICED.K1.INIT 0000000010001100
|
|
word: SLICEA.K1.INIT 1010101010101111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R33C35:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: V00B0000 V02S0201
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0100
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0101
|
|
arc: C0 V02S0401
|
|
arc: C1 V02S0401
|
|
arc: C2 N1_V01S0100
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 E1_H02W0001
|
|
arc: E1_H02E0001 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 F0
|
|
arc: LSR0 V00B0000
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 1100100001000000
|
|
word: SLICEA.K1.INIT 0000100000000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C36:PLC2
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: B1 V02N0301
|
|
arc: B3 H01W0100
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 S1_V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D3 S1_V02N0001
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 F3
|
|
arc: S1_V02S0101 F1
|
|
arc: V00T0100 F1
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
word: SLICEB.K1.INIT 0011001100000000
|
|
word: SLICEA.K1.INIT 1100110011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R33C37:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A3 H00L0100
|
|
arc: B0 H01W0100
|
|
arc: B1 V00B0000
|
|
arc: B3 E1_H01W0100
|
|
arc: C3 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D3 W1_H02E0001
|
|
arc: E1_H01E0101 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M5 V01S0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q5
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0103 F2
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 Q6
|
|
arc: W3_H06W0103 F2
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C38:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: E1_H01E0001 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 H02E0301
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: M5 V01S0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0303 Q5
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q7
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C39:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: C0 V02S0401
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0100
|
|
arc: M3 H01W0100
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: S1_V02S0301 Q3
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R33C3:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 V02S0201
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: A1 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 E1_H02W0101
|
|
arc: B7 V00B0000
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 H00L0000
|
|
arc: C7 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 H02E0201
|
|
arc: D2 V00B0100
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0301 Q1
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 0000000011000000
|
|
word: SLICEA.K1.INIT 0101010100010000
|
|
word: SLICEB.K0.INIT 1111111100000010
|
|
word: SLICED.K1.INIT 0000001000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C40:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
|
|
.tile R33C42:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile R33C44:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
|
|
.tile R33C45:PLC2
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R33C4:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: A0 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A7 V00T0100
|
|
arc: B0 H02E0301
|
|
arc: B2 H02E0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 H01E0101
|
|
arc: C0 H00L0000
|
|
arc: C1 H02E0401
|
|
arc: C2 H00L0000
|
|
arc: C3 H02W0401
|
|
arc: C4 H01E0001
|
|
arc: C5 H02E0401
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V00B0100
|
|
arc: D2 Q2
|
|
arc: D3 H02E0201
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 S1_V02N0401
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F4
|
|
arc: N3_V06N0203 F4
|
|
arc: N3_V06N0303 F5
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0601 F4
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F1
|
|
word: SLICEC.K1.INIT 0000000011000000
|
|
word: SLICEA.K1.INIT 1111111100001111
|
|
word: SLICEB.K0.INIT 0000000011111110
|
|
word: SLICEA.K0.INIT 1111111000000000
|
|
word: SLICED.K1.INIT 0000111100000001
|
|
word: SLICEB.K1.INIT 0000000011110011
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R33C50:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R33C56:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R33C5:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A1 V02S0701
|
|
arc: A3 F5
|
|
arc: A4 F7
|
|
arc: A5 W1_H02E0501
|
|
arc: A7 W1_H02E0501
|
|
arc: B1 W1_H02E0101
|
|
arc: B3 H00L0000
|
|
arc: B4 H00L0000
|
|
arc: B5 H01E0101
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 H01E0101
|
|
arc: C0 H02W0401
|
|
arc: C1 H02E0601
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V00T0100
|
|
arc: C7 V00T0100
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D5 H02E0001
|
|
arc: D6 V02N0401
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F3
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
arc: N3_V06N0303 F6
|
|
arc: S1_V02S0401 F4
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q5
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
word: SLICEA.K1.INIT 1010101010101000
|
|
word: SLICEB.K0.INIT 0000000011110000
|
|
word: SLICEC.K1.INIT 0000000000000100
|
|
word: SLICEB.K1.INIT 0010000000000000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 0010000000000000
|
|
word: SLICED.K0.INIT 1100110000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C62:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R33C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R33C6:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A1 V02S0701
|
|
arc: A3 H01E0001
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 N1_V01N0101
|
|
arc: B3 H00L0000
|
|
arc: B5 H01E0101
|
|
arc: B6 V00T0000
|
|
arc: B7 V00T0000
|
|
arc: C0 V02S0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 N1_V02S0201
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D3 H02W0201
|
|
arc: D5 H02W0201
|
|
arc: D6 H00L0100
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F4
|
|
arc: LSR0 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V00B0000 F6
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
word: SLICEA.K1.INIT 0000000010101010
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 0000000010000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000100000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C74:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R33C7:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A2 V02S0701
|
|
arc: A3 V00T0000
|
|
arc: A5 V00B0000
|
|
arc: B0 H02E0301
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B5 W1_H02E0101
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C5 S1_V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D5 E1_H02W0201
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEC.K1.INIT 0000000000000010
|
|
word: SLICEA.K0.INIT 0000000011001100
|
|
word: SLICEB.K0.INIT 1010101010101000
|
|
word: SLICEB.K1.INIT 1010101010101000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C80:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R33C86:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R33C88:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
|
|
.tile R33C8:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: B1 Q1
|
|
arc: C0 V02N0401
|
|
arc: C1 H00L0000
|
|
arc: CE0 H00R0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0100 Q7
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C9:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: B0 V02N0101
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0201 F0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C10:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
arc: A1 H00R0000
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0001 F0
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110010101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R35C11:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: V00B0100 V02S0101
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C12:PLC2
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: C1 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0201
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W1_H02W0301 Q1
|
|
word: SLICEA.K1.INIT 0000111100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R35C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V02N0401 Q6
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C14:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C15:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C16:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: C3 H02W0401
|
|
arc: D3 E1_H02W0201
|
|
arc: F3 F3_SLICE
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEB.K1.INIT 1111000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R35C17:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 H02E0701
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 H02E0101
|
|
arc: B3 H02W0301
|
|
arc: B4 F3
|
|
arc: C0 H00R0100
|
|
arc: C2 H02W0601
|
|
arc: C3 W1_H02E0601
|
|
arc: C4 V02S0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0201
|
|
arc: D2 F0
|
|
arc: D3 H02E0201
|
|
arc: D4 F2
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: H01W0100 Q5
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICEB.K1.INIT 0000000011011111
|
|
word: SLICEB.K0.INIT 1000110000000000
|
|
word: SLICEC.K0.INIT 0000000000111111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C18:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A0 E1_H01E0001
|
|
arc: B0 S1_V02N0301
|
|
arc: C0 E1_H01W0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEA.K0.INIT 1111110011111110
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C19:PLC2
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A6 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 H01E0001
|
|
arc: C6 H01E0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D2 W1_H02E0201
|
|
arc: D3 H02E0001
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 E1_H02W0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F3
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0501 Q7
|
|
arc: N3_V06N0303 F5
|
|
arc: S3_V06S0303 Q5
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEB.K0.INIT 0101010111111111
|
|
word: SLICED.K0.INIT 0101010100000101
|
|
word: SLICEA.K0.INIT 1111111101010101
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET SET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R35C20:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H02E0701
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: C0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 V01S0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
word: SLICEA.K0.INIT 0010001000110010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R35C21:PLC2
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: A2 H02E0701
|
|
arc: C0 N1_V02S0601
|
|
arc: C2 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D2 E1_H02W0001
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 H02W0301
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q4
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 1010111110100000
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R35C22:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: B3 V01N0001
|
|
arc: C7 V02S0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V02N0201
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0203 Q4
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N3_V06N0003 F3
|
|
arc: V00B0100 F7
|
|
arc: V01S0100 F7
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
word: SLICED.K1.INIT 1111000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C23:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A0 H02W0701
|
|
arc: B0 N1_V02S0101
|
|
arc: C0 H02W0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: E1_H02E0301 Q3
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00B0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 W1_H02E0201
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0501 Q5
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 0000110000001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C24:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: CE0 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00T0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: W1_H02W0701 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C25:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 H02W0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 H02E0501
|
|
arc: B0 V00T0000
|
|
arc: C0 H02E0401
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 Q5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000110000001010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C26:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A2 E1_H01E0001
|
|
arc: B0 V00B0000
|
|
arc: C0 H02E0601
|
|
arc: C2 W1_H02E0601
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D2 N1_V02S0201
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M4 H02W0401
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 Q2
|
|
arc: V00B0000 Q6
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1010101011110000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C27:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: W1_H02W0501 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C28:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A0 V02S0501
|
|
arc: B0 H02E0301
|
|
arc: C0 H02W0601
|
|
arc: CE0 H00L0000
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 0011000100100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C29:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A0 E1_H01E0001
|
|
arc: C0 E1_H01W0000
|
|
arc: CE0 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 Q6
|
|
word: SLICEA.K0.INIT 1010000011110101
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C2:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: C0 H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V01S0100
|
|
arc: D4 H01W0000
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 F4
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F2
|
|
arc: LSR1 H02W0501
|
|
arc: M3 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0101 Q3
|
|
word: SLICED.K1.INIT 0000000011111111
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET SET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C30:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: V00T0000 H02E0201
|
|
arc: A0 H01E0001
|
|
arc: A2 N1_V02S0701
|
|
arc: B2 N1_V02S0101
|
|
arc: C0 H00L0000
|
|
arc: C2 V02S0401
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 H02W0301
|
|
arc: M2 V00T0000
|
|
arc: M3 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
word: SLICEB.K0.INIT 0101000111110011
|
|
word: SLICEA.K0.INIT 1010000011110101
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C31:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: B0 V00B0000
|
|
arc: C0 H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1111001100000011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C32:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A0 H00L0100
|
|
arc: A1 V02S0501
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: A6 H00R0000
|
|
arc: B0 V02S0101
|
|
arc: B1 H01W0100
|
|
arc: B3 V02S0101
|
|
arc: B6 V01S0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H00L0000
|
|
arc: C3 V02N0601
|
|
arc: C6 V02S0001
|
|
arc: CE0 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 F0
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D6 H02W0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 H02W0501
|
|
arc: M2 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0601 F6
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0301 F1
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
word: SLICEB.K1.INIT 0110101000000000
|
|
word: SLICEA.K1.INIT 0101010000000100
|
|
word: SLICEA.K0.INIT 0010101010000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C33:PLC2
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: C0 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: CE0 N1_V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 N1_V02S0001
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEB.K0.INIT 1110111101111111
|
|
word: SLICEB.K1.INIT 1111101111111111
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C34:PLC2
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: W1_H02W0101 H01E0101
|
|
|
|
.tile R35C35:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: H00L0000 H02W0201
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A1 H00L0000
|
|
arc: A6 H00R0000
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B6 E1_H02W0101
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C6 V00B0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D6 H02W0201
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0100 Q5
|
|
arc: W3_H06W0003 F0
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 1111111111111100
|
|
word: SLICEA.K1.INIT 1010101010101000
|
|
word: SLICED.K0.INIT 0000000011110010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET SET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R35C36:PLC2
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0100 H02W0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H02E0701
|
|
arc: A7 N1_V02S0101
|
|
arc: B0 V01N0001
|
|
arc: B4 V01S0000
|
|
arc: C1 F4
|
|
arc: C4 V00T0100
|
|
arc: C7 F4
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D4 V00B0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F4
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0401 F4
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEC.K0.INIT 0000000000110000
|
|
word: SLICED.K1.INIT 1010111110101111
|
|
word: SLICEA.K1.INIT 0101000001010000
|
|
word: SLICEA.K0.INIT 0110011010101010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C37:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: A0 H01E0001
|
|
arc: C0 V02N0401
|
|
arc: C3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D3 H01E0101
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1010000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R35C38:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: V00B0100 V02S0301
|
|
arc: C0 H02E0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E1_H02E0401 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M3 H01W0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00T0000 Q0
|
|
arc: W3_H06W0003 Q3
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R35C39:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: V00T0000 H02E0201
|
|
arc: B0 H02E0301
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C3:PLC2
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: B1 N1_V02S0301
|
|
arc: C0 V02S0401
|
|
arc: C1 V02S0401
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0601 Q6
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEA.K0.INIT 0000101010101010
|
|
word: SLICEA.K1.INIT 1100111011101110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C40:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: LSR0 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C41:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R35C43:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0100 V02N0701
|
|
arc: V00B0000 H02W0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00T0100 Q3
|
|
arc: W1_H02W0601 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C44:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
|
|
.tile R35C45:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R35C46:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R35C47:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R35C49:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R35C4:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 V02S0501
|
|
arc: A0 V02S0501
|
|
arc: B0 N1_V02S0101
|
|
arc: C0 H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 V00T0100
|
|
arc: E1_H02E0201 F0
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEA.K0.INIT 0101000100010001
|
|
word: SLICEA.K1.INIT 0000000011111111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R35C50:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R35C51:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R35C52:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R35C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R35C55:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R35C56:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R35C57:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R35C58:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R35C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R35C5:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 H02W0201
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A7 Q7
|
|
arc: B2 F3
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 S1_V02N0601
|
|
arc: C2 H00L0000
|
|
arc: C3 N1_V02S0401
|
|
arc: C6 N1_V02S0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 V01S0100
|
|
arc: D6 H00R0100
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 Q7
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0701 Q7
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICED.K0.INIT 1100111100000000
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICED.K1.INIT 1100110011011101
|
|
word: SLICEB.K0.INIT 0000000000000011
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R35C61:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R35C62:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R35C63:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R35C64:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R35C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R35C67:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R35C68:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R35C69:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R35C6:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: A0 H01E0001
|
|
arc: A3 H02E0501
|
|
arc: C3 S1_V02N0601
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D3 H02E0001
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M5 W1_H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: S1_V02S0301 F3
|
|
word: SLICEB.K1.INIT 1111000011110101
|
|
word: SLICEA.K0.INIT 0101010100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C70:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R35C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R35C73:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R35C74:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R35C75:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R35C76:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R35C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R35C79:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R35C7:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 W1_H02E0501
|
|
arc: C0 N1_V02S0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 1111000011111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C80:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R35C81:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R35C82:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R35C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R35C85:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
|
|
.tile R35C86:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R35C87:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
|
|
.tile R35C88:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: D3 W1_H02E0001
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 W1_H02E0001
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 F5
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
word: SLICEC.K1.INIT 0000000011111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R35C8:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q6
|
|
arc: LSR0 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C9:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C10:PLC2
|
|
arc: N1_V02N0601 H06E0303
|
|
|
|
.tile R36C11:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
|
|
.tile R36C13:PLC2
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
|
|
.tile R36C14:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R36C20:PLC2
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N3_V06N0103 Q2
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C21:PLC2
|
|
arc: N1_V02N0101 H06W0103
|
|
|
|
.tile R36C22:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: A0 V02S0501
|
|
arc: C0 N1_V01S0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
word: SLICEA.K0.INIT 1010101010101111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R36C23:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: W1_H02W0401 V06S0203
|
|
|
|
.tile R36C24:PLC2
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: W3_H06W0103 N3_V06S0103
|
|
|
|
.tile R36C25:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
|
|
.tile R36C28:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
|
|
.tile R36C32:PLC2
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R36C33:PLC2
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
|
|
.tile R36C35:PLC2
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
|
|
.tile R36C36:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: V00B0100 V02S0101
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C37:PLC2
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H01E0001
|
|
|
|
.tile R36C38:PLC2
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
|
|
.tile R36C43:PLC2
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
|
|
.tile R36C4:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 V06S0303
|
|
|
|
.tile R36C5:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
|
|
.tile R36C6:PLC2
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: A0 V02S0501
|
|
arc: B0 V00T0000
|
|
arc: C0 W1_H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 1111101011110010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C7:PLC2
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
|
|
.tile R36C8:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
|
|
.tile R37C17:PLC2
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R37C18:PLC2
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
|
|
.tile R37C19:PLC2
|
|
arc: N1_V02N0301 H02W0301
|
|
|
|
.tile R37C20:PLC2
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
|
|
.tile R37C22:PLC2
|
|
arc: N1_V02N0301 H02W0301
|
|
|
|
.tile R37C23:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
|
|
.tile R37C24:PLC2
|
|
arc: N1_V02N0001 H02E0001
|
|
|
|
.tile R37C25:PLC2
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R37C26:PLC2
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
|
|
.tile R37C29:PLC2
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
|
|
.tile R37C2:PLC2
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
|
|
.tile R37C35:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R37C36:PLC2
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
|
|
.tile R37C41:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R37C47:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R37C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R37C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R37C5:PLC2
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R37C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R37C6:PLC2
|
|
arc: N1_V02N0601 H02E0601
|
|
|
|
.tile R37C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R37C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R37C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R37C9:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
|
|
.tile R38C38:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
|
|
.tile R38C43:PLC2
|
|
arc: N1_V02N0701 H06W0203
|
|
|
|
.tile R38C46:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R38C47:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
|
|
.tile R38C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R38C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R38C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R38C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R38C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R38C7:PLC2
|
|
arc: W3_H06W0003 V06S0003
|
|
|
|
.tile R38C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R3C14:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
|
|
.tile R3C15:PLC2
|
|
arc: N1_V02N0201 H02E0201
|
|
|
|
.tile R3C35:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
|
|
.tile R3C36:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
|
.tile R3C41:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R3C42:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R3C43:PLC2
|
|
arc: N1_V02N0401 H01E0001
|
|
|
|
.tile R3C44:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R3C47:PLC2
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
|
|
.tile R41C19:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R42C6:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R47C19:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R48C6:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R4C15:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R53C19:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R54C6:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R59C19:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R5C41:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R5C47:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R60C6:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R65C19:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R66C6:PLC2
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R68C18:PLC2
|
|
arc: S1_V02S0501 H02W0501
|
|
|
|
.tile R68C19:PLC2
|
|
arc: W1_H02W0501 V06S0303
|
|
|
|
.tile R68C6:PLC2
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile R6C15:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R7C11:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R7C13:PLC2
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
|
|
.tile R7C14:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R7C17:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C20:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C22:PLC2
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
|
|
.tile R7C23:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
|
|
.tile R7C25:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R7C26:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C27:PLC2
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
|
|
.tile R7C28:PLC2
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R7C2:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R7C30:PLC2
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 V01N0001
|
|
|
|
.tile R7C32:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C33:PLC2
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
|
|
.tile R7C35:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R7C36:PLC2
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C38:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C41:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C44:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R7C47:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R7C5:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R7C8:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R8C10:PLC2
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R8C11:PLC2
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
|
|
.tile R8C12:PLC2
|
|
arc: S1_V02S0601 H06W0303
|
|
|
|
.tile R8C14:PLC2
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R8C15:PLC2
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R8C26:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
|
|
.tile R8C27:PLC2
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: CE0 H02E0101
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M0 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0203 Q7
|
|
arc: V00B0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R8C28:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0501 V06N0303
|
|
|
|
.tile R8C29:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: B0 V02N0301
|
|
arc: B1 Q1
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 F0
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 0000111000000100
|
|
word: SLICEA.K1.INIT 1111111011110100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R8C30:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 H02W0501
|
|
arc: A1 H02W0501
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: C0 S1_V02N0401
|
|
arc: C1 H00L0100
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 S1_V02N0201
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR1 H02E0501
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 0100010101000000
|
|
word: SLICEA.K1.INIT 1110111011111010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R8C31:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: W1_H02W0501 V01N0101
|
|
|
|
.tile R8C32:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
|
|
.tile R8C33:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0000
|
|
arc: M5 V01S0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q5
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R8C34:PLC2
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile R8C38:PLC2
|
|
arc: S1_V02S0601 V01N0001
|
|
|
|
.tile R8C48:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R8C7:PLC2
|
|
arc: S1_V02S0601 H06W0303
|
|
|
|
.tile R8C8:PLC2
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
|
|
.tile R8C9:PLC2
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R9C10:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 H00R0100
|
|
arc: CE0 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 H02W0601
|
|
arc: M1 H00L0000
|
|
arc: M5 H00L0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R9C11:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02S0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A2 H02W0701
|
|
arc: A3 F5
|
|
arc: A5 Q5
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 V00B0000
|
|
arc: B1 Q1
|
|
arc: B2 S1_V02N0101
|
|
arc: B5 E1_H02W0101
|
|
arc: B7 F3
|
|
arc: C0 H00L0100
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 N1_V01N0001
|
|
arc: C5 W1_H02E0401
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 H01E0101
|
|
arc: D3 F2
|
|
arc: D5 E1_H02W0001
|
|
arc: D7 W1_H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M3 H02W0201
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F0
|
|
arc: S3_V06S0203 F7
|
|
arc: V00B0000 Q6
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
word: SLICEA.K1.INIT 1111111111001100
|
|
word: SLICEC.K1.INIT 0000101100001111
|
|
word: SLICEB.K0.INIT 1101000000000000
|
|
word: SLICEB.K1.INIT 0000000001011111
|
|
word: SLICED.K1.INIT 1111101000110011
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R9C12:PLC2
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 F5
|
|
arc: A3 H00L0100
|
|
arc: A5 Q5
|
|
arc: B0 F3
|
|
arc: B3 H02W0101
|
|
arc: B5 H02W0101
|
|
arc: C0 S1_V02N0401
|
|
arc: C3 N1_V01N0001
|
|
arc: C5 V00T0000
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D3 H02W0001
|
|
arc: D5 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 F0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M5 H00L0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
word: SLICEB.K1.INIT 0000000000011101
|
|
word: SLICEC.K1.INIT 0000000010111111
|
|
word: SLICEA.K0.INIT 0010001000000010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R9C13:PLC2
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C14:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R9C22:PLC2
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 H02W0601
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: CE0 H02W0101
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M1 V01S0100
|
|
arc: M3 H00L0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0401 Q6
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C23:PLC2
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q7
|
|
arc: H00R0000 Q4
|
|
arc: LSR1 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C24:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: A2 H02E0501
|
|
arc: A3 V00T0000
|
|
arc: B2 H02W0101
|
|
arc: B3 H00R0100
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 S1_V02N0401
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q6
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 F2
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H01W0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0100 Q3
|
|
word: SLICEB.K0.INIT 0010001000110000
|
|
word: SLICEB.K1.INIT 1111110011111010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C25:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: H00R0000 H02W0601
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: CE0 H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02E0601
|
|
arc: M4 V00T0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0601 Q4
|
|
arc: V00T0000 Q0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C26:PLC2
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: CE1 V02N0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q6
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C27:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0701
|
|
arc: B0 H00R0100
|
|
arc: B1 V02S0101
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 S1_V02N0301
|
|
arc: C0 H02W0401
|
|
arc: C1 V02N0401
|
|
arc: C2 H02W0401
|
|
arc: C3 H02W0401
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 V02S0001
|
|
arc: D3 V02N0201
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0000 F2
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00T0000 F0
|
|
word: SLICEA.K0.INIT 0000111000000010
|
|
word: SLICEA.K1.INIT 1111111011001110
|
|
word: SLICEB.K0.INIT 0000110000001010
|
|
word: SLICEB.K1.INIT 1111110011111010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R9C28:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 V02N0701
|
|
arc: A3 V00T0000
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B4 V02N0501
|
|
arc: B7 E1_H02W0301
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0301 Q3
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F4
|
|
arc: LSR1 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0301 Q3
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C29:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 H02W0601
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 S1_V02N0301
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 H00R0000
|
|
arc: B4 H02E0301
|
|
arc: B7 V00B0000
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F5
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 F0
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M5 H02W0001
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0601 F4
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F1
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C30:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 E1_H02W0501
|
|
arc: A2 V02S0501
|
|
arc: A4 N1_V02S0301
|
|
arc: A7 S1_V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 S1_V02N0701
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: S3_V06S0203 F4
|
|
arc: V01S0000 F1
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C31:PLC2
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A4 H02E0501
|
|
arc: A5 N1_V01N0101
|
|
arc: B0 V00T0000
|
|
arc: B4 H00L0000
|
|
arc: B5 H00L0000
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V00B0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02S0201
|
|
arc: CE2 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H01W0000
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q5
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
arc: M4 H02E0401
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00B0100 Q5
|
|
arc: V00T0100 Q1
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000110100001000
|
|
word: SLICEC.K1.INIT 1110111011111010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R9C32:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: A0 H00R0000
|
|
arc: A1 H02E0701
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: C0 H02E0401
|
|
arc: C1 V02N0401
|
|
arc: C2 H02E0401
|
|
arc: C3 V02N0401
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D2 V00B0100
|
|
arc: D3 E1_H02W0001
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 V00T0000
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0100
|
|
arc: M4 E1_H01E0101
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0501 Q7
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEA.K0.INIT 0000110100001000
|
|
word: SLICEA.K1.INIT 1110111111101010
|
|
word: SLICEB.K0.INIT 0000101000001100
|
|
word: SLICEB.K1.INIT 1111111110101100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C33:PLC2
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: CE0 H02E0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H00R0000
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0601 Q6
|
|
arc: W1_H02W0701 Q7
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C34:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: H00R0100 H02E0701
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q3
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M3 H00R0100
|
|
arc: M4 W1_H02E0401
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0401 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C35:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0203 Q7
|
|
arc: S1_V02S0601 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C36:PLC2
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 H02E0601
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N3_V06N0003 Q3
|
|
arc: S1_V02S0001 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C37:PLC2
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile R9C38:PLC2
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: H00R0000 Q6
|
|
arc: LSR1 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C41:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R9C44:PLC2
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R9C47:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R9C5:PLC2
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
|
|
.tile R9C6:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
|
|
.tile R9C7:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: B1 Q1
|
|
arc: C0 H00R0100
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
word: SLICEA.K0.INIT 1111111111110000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R9C8:PLC2
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0701
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: V00T0100 H02W0101
|
|
arc: A3 V00T0000
|
|
arc: B3 Q3
|
|
arc: C3 H00L0100
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 H02E0001
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 W1_H02E0301
|
|
arc: M0 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 Q7
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K1.INIT 0000000000110101
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R9C9:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A0 H00R0000
|
|
arc: C0 H00L0000
|
|
arc: C1 E1_H02W0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 V01S0100
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: S3_V06S0003 F0
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
word: SLICEA.K1.INIT 1111111100001111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile TAP_R11C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R11C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R12C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R12C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R13C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R13C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R14C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R14C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R15C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R15C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R16C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R16C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R17C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R17C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R18C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R18C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R19C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R19C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C31:TAP_DRIVE
|
|
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.tile_group MIB_R22C13:MIB_DSP0 MIB_R22C13:MIB2_DSP0 MIB_R22C14:MIB_DSP1 MIB_R22C14:MIB2_DSP1 MIB_R22C15:MIB_DSP2 MIB_R22C15:MIB2_DSP2 MIB_R22C16:MIB_DSP3 MIB_R22C16:MIB2_DSP3 MIB_R22C17:MIB_DSP4 MIB_R22C17:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C8:MIB_DSP4 MIB_R22C8:MIB2_DSP4 MIB_R22C9:MIB_DSP5 MIB_R22C9:MIB2_DSP5 MIB_R22C10:MIB_DSP6 MIB_R22C10:MIB2_DSP6 MIB_R22C11:MIB_DSP7 MIB_R22C11:MIB2_DSP7 MIB_R22C12:MIB_DSP8 MIB_R22C12:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R34C22:MIB_EBR0 MIB_R34C23:MIB_EBR1
|
|
word: EBR0.WID 110000000
|
|
word: EBR0.CSDECODE_A 111
|
|
word: EBR0.CSDECODE_B 111
|
|
enum: EBR0.MODE DP16KD
|
|
enum: EBR0.DP16KD.DATA_WIDTH_A 4
|
|
enum: EBR0.DP16KD.DATA_WIDTH_B 4
|
|
enum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE
|
|
enum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE
|
|
enum: EBR0.REGMODE_A NOREG
|
|
enum: EBR0.REGMODE_B NOREG
|
|
enum: EBR0.RESETMODE ASYNC
|
|
enum: EBR0.ASYNC_RESET_RELEASE ASYNC
|
|
enum: EBR0.GSR DISABLED
|
|
enum: EBR0.CLKAMUX CLKA
|
|
enum: EBR0.CLKBMUX CLKB
|
|
enum: EBR0.RSTAMUX INV
|
|
enum: EBR0.RSTBMUX INV
|
|
enum: EBR0.WEAMUX WEA
|
|
enum: EBR0.WEBMUX INV
|
|
enum: EBR0.CEAMUX CEA
|
|
enum: EBR0.CEBMUX CEB
|
|
enum: EBR0.OCEAMUX OCEA
|
|
enum: EBR0.OCEBMUX OCEB
|
|
|
|
.tile_group MIB_R34C24:MIB_EBR2 MIB_R34C25:MIB_EBR3 MIB_R34C26:MIB_EBR4
|
|
word: EBR1.WID 001000000
|
|
word: EBR1.CSDECODE_A 111
|
|
word: EBR1.CSDECODE_B 111
|
|
enum: EBR1.MODE DP16KD
|
|
enum: EBR1.DP16KD.DATA_WIDTH_A 4
|
|
enum: EBR1.DP16KD.DATA_WIDTH_B 4
|
|
enum: EBR1.DP16KD.WRITEMODE_A READBEFOREWRITE
|
|
enum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE
|
|
enum: EBR1.REGMODE_A NOREG
|
|
enum: EBR1.REGMODE_B NOREG
|
|
enum: EBR1.RESETMODE ASYNC
|
|
enum: EBR1.ASYNC_RESET_RELEASE ASYNC
|
|
enum: EBR1.GSR DISABLED
|
|
enum: EBR1.CLKAMUX CLKA
|
|
enum: EBR1.CLKBMUX CLKB
|
|
enum: EBR1.RSTAMUX INV
|
|
enum: EBR1.RSTBMUX INV
|
|
enum: EBR1.WEAMUX WEA
|
|
enum: EBR1.WEBMUX INV
|
|
enum: EBR1.CEAMUX CEA
|
|
enum: EBR1.CEBMUX CEB
|
|
enum: EBR1.OCEAMUX OCEA
|
|
enum: EBR1.OCEBMUX OCEB
|
|
|
|
.tile_group MIB_R22C4:MIB_DSP0 MIB_R22C4:MIB2_DSP0 MIB_R22C5:MIB_DSP1 MIB_R22C5:MIB2_DSP1 MIB_R22C6:MIB_DSP2 MIB_R22C6:MIB2_DSP2 MIB_R22C7:MIB_DSP3 MIB_R22C7:MIB2_DSP3 MIB_R22C8:MIB_DSP4 MIB_R22C8:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C8:MIB_DSP4 MIB_R22C8:MIB2_DSP4 MIB_R22C9:MIB_DSP5 MIB_R22C9:MIB2_DSP5 MIB_R22C10:MIB_DSP6 MIB_R22C10:MIB2_DSP6 MIB_R22C11:MIB_DSP7 MIB_R22C11:MIB2_DSP7 MIB_R22C12:MIB_DSP8 MIB_R22C12:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|