micheleandClaude Sonnet 5
97a21be240
Adds FPGA-exclusive access to the onboard W25Q128JV SPI NOR flash for weights/bias/network persistence, layered as spi_flash_master (raw SPI, USRMCLK-driven) -> flash_copy_engine (flash<->PSRAM streaming, erase- before-write, Page Program loop) -> flash_slot_manager (16-slot catalog with CRC32), exposed via 8 new SPI opcodes (0x40-0x47). Fixes two pre-existing bugs found during bring-up: a psram_controller.v request lost during power-up, and a one-cycle-pulse race in the PSRAM arbiter request handshake. Full simulation + real Yosys/nextpnr-ecp5 synthesis verification (0 errors, Fmax 66.68MHz) in WORKLOG.md and docs/FPGA-Neural-Flash-Subsystem-Verification.md. Also updates docs/pinout to reflect the 56-signal real .lpf (3 new flash pins) and documents the WRITE_RAM/READ_RAM host backpressure risk found while testing this subsystem. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
239 lines
7.6 KiB
Verilog
239 lines
7.6 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// MEM_ARBITER
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//
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// Arbitrates a single shared byte-level memory master port (feeding
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// a shared int8_memory_access -> memory_interface -> psram_controller
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// chain) between three byte-level requesters:
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//
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// Port A: spi_engine.v (WRITE_RAM / READ_RAM opcodes)
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// Port B: neuron_memory.v (its own X/W/bias reads during a run)
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// Port C: layer_sequencer.v (Phase 5: descriptor reads + output
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// buffer writes between layers)
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// Port D: flash_copy_engine.v (flash-subsystem F2: flash<->PSRAM
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// block DMA, LOWEST priority -- see
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// below)
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//
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// Fixed priority B > C > A > D when more than one requests on the
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// same idle cycle (an in-progress inference is treated as more
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// time-critical than the sequencer's own bookkeeping, which in turn
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// is treated as more time-critical than a newly-arriving manual SPI
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// RAM access, which in turn is treated as more time-critical than
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// the flash copy engine -- flash operations are ms-scale and never
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// meant to compete with inference for memory bandwidth, per the
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// flash-subsystem phase-plan's explicit "priorita bassa" requirement:
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// a flash load/save simply waits its turn, one byte-transaction at a
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// time, behind anything else that wants the shared PSRAM port).
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// In normal operation B and C are temporally disjoint anyway --
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// neuron_memory only requests while running, and layer_sequencer
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// only requests in the gaps between layers -- so priority among
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// A/B/C mostly matters for the edge case of a manual
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// WRITE_RAM/READ_RAM arriving while a Phase 5 run is in progress.
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// Port D is expected to be active only during flash load/save,
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// which this design assumes does not overlap real-time inference
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// (the same "not the hot path" assumption the flash phase-plan
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// states explicitly) -- if it ever did overlap, its lowest-priority
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// placement here means it simply gets stretched out, never starves
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// or corrupts A/B/C.
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// Once a port is granted, the arbiter holds ownership until that
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// single transaction's m_ready pulse, then releases -- all four
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// masters already issue `req` as a clean one-cycle pulse (matching
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// int8_memory_access's own contract), so a simple grant-and-forward
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// design is sufficient; no request queuing/pipelining is needed.
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// ================================================================
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module mem_arbiter #(
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parameter ADDR_WIDTH = 23
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)(
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input wire clk,
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input wire rst,
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// ------------------------------------------------------------
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// Port A - spi_engine
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// ------------------------------------------------------------
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input wire a_req,
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input wire a_wr,
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input wire [ADDR_WIDTH-1:0] a_addr,
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input wire signed [7:0] a_wdata,
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output reg signed [7:0] a_rdata,
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output reg a_ready,
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// ------------------------------------------------------------
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// Port B - neuron_memory
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// ------------------------------------------------------------
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input wire b_req,
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input wire b_wr,
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input wire [ADDR_WIDTH-1:0] b_addr,
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input wire signed [7:0] b_wdata,
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output reg signed [7:0] b_rdata,
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output reg b_ready,
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// ------------------------------------------------------------
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// Port C - layer_sequencer
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// ------------------------------------------------------------
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input wire c_req,
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input wire c_wr,
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input wire [ADDR_WIDTH-1:0] c_addr,
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input wire signed [7:0] c_wdata,
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output reg signed [7:0] c_rdata,
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output reg c_ready,
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// ------------------------------------------------------------
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// Port D - flash_copy_engine (F2, lowest priority)
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// ------------------------------------------------------------
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input wire d_req,
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input wire d_wr,
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input wire [ADDR_WIDTH-1:0] d_addr,
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input wire signed [7:0] d_wdata,
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output reg signed [7:0] d_rdata,
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output reg d_ready,
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// ------------------------------------------------------------
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// Shared master port
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// ------------------------------------------------------------
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output reg m_req,
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output reg m_wr,
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output reg [ADDR_WIDTH-1:0] m_addr,
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output reg signed [7:0] m_wdata,
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input wire signed [7:0] m_rdata,
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input wire m_ready
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);
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localparam SEL_NONE = 3'd0;
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localparam SEL_A = 3'd1;
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localparam SEL_B = 3'd2;
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localparam SEL_C = 3'd3;
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localparam SEL_D = 3'd4;
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reg [2:0] owner;
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always @(posedge clk) begin
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if (rst) begin
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owner <= SEL_NONE;
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m_req <= 1'b0;
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m_wr <= 1'b0;
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m_addr <= {ADDR_WIDTH{1'b0}};
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m_wdata <= 8'sd0;
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a_rdata <= 8'sd0;
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a_ready <= 1'b0;
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b_rdata <= 8'sd0;
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b_ready <= 1'b0;
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c_rdata <= 8'sd0;
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c_ready <= 1'b0;
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d_rdata <= 8'sd0;
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d_ready <= 1'b0;
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end else begin
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m_req <= 1'b0;
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a_ready <= 1'b0;
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b_ready <= 1'b0;
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c_ready <= 1'b0;
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d_ready <= 1'b0;
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case (owner)
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SEL_NONE: begin
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if (b_req) begin
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owner <= SEL_B;
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m_req <= 1'b1;
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m_wr <= b_wr;
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m_addr <= b_addr;
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m_wdata <= b_wdata;
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end else if (c_req) begin
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owner <= SEL_C;
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m_req <= 1'b1;
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m_wr <= c_wr;
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m_addr <= c_addr;
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m_wdata <= c_wdata;
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end else if (a_req) begin
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owner <= SEL_A;
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m_req <= 1'b1;
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m_wr <= a_wr;
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m_addr <= a_addr;
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m_wdata <= a_wdata;
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end else if (d_req) begin
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owner <= SEL_D;
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m_req <= 1'b1;
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m_wr <= d_wr;
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m_addr <= d_addr;
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m_wdata <= d_wdata;
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end
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end
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SEL_A: begin
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if (m_ready) begin
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a_rdata <= m_rdata;
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a_ready <= 1'b1;
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owner <= SEL_NONE;
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end
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end
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SEL_B: begin
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if (m_ready) begin
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b_rdata <= m_rdata;
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b_ready <= 1'b1;
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owner <= SEL_NONE;
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end
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end
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SEL_C: begin
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if (m_ready) begin
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c_rdata <= m_rdata;
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c_ready <= 1'b1;
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owner <= SEL_NONE;
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end
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end
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SEL_D: begin
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if (m_ready) begin
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d_rdata <= m_rdata;
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d_ready <= 1'b1;
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owner <= SEL_NONE;
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end
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end
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default: begin
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owner <= SEL_NONE;
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end
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endcase
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end
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end
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endmodule
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