micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R10C77:CIB_EBR
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arc: N3_V06N0103 S1_V02N0201
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.tile CIB_R10C78:CIB_EBR
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arc: V01S0000 S3_V06N0103
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.tile CIB_R10C86:CIB_EBR
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arc: S1_V02S0701 V01N0101
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.tile CIB_R10C87:CIB_EBR
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arc: S1_V02S0501 S3_V06N0303
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arc: S1_V02S0601 S3_V06N0303
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arc: V01S0100 S3_V06N0303
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.tile CIB_R11C1:CIB_LR
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arc: E3_H06E0303 JQ5
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.tile CIB_R11C89:CIB_LR
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arc: H00L0000 W1_H02E0001
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arc: JA0 H00L0000
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enum: CIB.JB0MUX 0
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.tile CIB_R16C89:CIB_LR
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arc: E1_H01E0001 W3_H06E0003
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arc: JA3 E1_H01E0001
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enum: CIB.JB3MUX 0
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.tile CIB_R17C89:CIB_LR
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arc: H00L0100 W1_H02E0101
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arc: JA3 H00L0100
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enum: CIB.JB3MUX 0
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.tile CIB_R1C30:CIB
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arc: E1_H02E0701 V06N0203
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.tile CIB_R1C31:CIB
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C39:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C43:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C45:CIB
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arc: E3_H06E0003 W3_H06E0003
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.tile CIB_R1C48:CIB
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arc: JD7 H02W0001
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.tile CIB_R1C49:CIB
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arc: W1_H02W0001 W3_H06E0003
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.tile CIB_R1C51:CIB
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arc: E3_H06E0103 W3_H06E0003
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.tile CIB_R1C57:CIB
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arc: E3_H06E0103 W3_H06E0103
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.tile CIB_R1C63:CIB
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arc: E3_H06E0203 W3_H06E0103
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.tile CIB_R1C69:CIB
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arc: E3_H06E0203 W3_H06E0203
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.tile CIB_R1C71:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C72:CIB
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arc: E3_H06E0003 V06N0003
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arc: S3_V06S0203 H06E0203
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.tile CIB_R1C75:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C77:CIB
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arc: E1_H02E0701 V06N0203
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.tile CIB_R1C78:CIB
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arc: E1_H01E0001 W3_H06E0003
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C79:CIB
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arc: JA0 H01E0001
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enum: CIB.JB0MUX 0
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.tile CIB_R22C25:CIB_DSP
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arc: E1_H02E0201 V02N0201
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arc: N1_V02N0201 E1_H01W0000
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.tile CIB_R22C26:CIB_DSP
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arc: E1_H01E0101 JQ4
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arc: E3_H06E0103 N1_V01S0100
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arc: E3_H06E0203 N1_V01S0000
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arc: H00R0000 V02S0601
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arc: H00R0100 V02N0701
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arc: H01W0000 JQ6
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arc: JB4 E1_H02W0301
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arc: JB5 H00R0000
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arc: JB6 V02N0501
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arc: JB7 V02S0501
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arc: JCE2 H00R0100
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arc: JCE3 H00R0100
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arc: JD4 E1_H02W0201
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arc: JD5 V02N0601
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arc: JD6 V02S0401
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arc: JD7 H02E0201
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arc: N1_V01N0001 JQ7
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arc: N1_V02N0001 E1_H01W0000
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arc: N1_V02N0101 H02W0101
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arc: N1_V02N0201 H02W0201
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arc: N1_V02N0301 E1_H01W0100
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arc: N1_V02N0401 JF6
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arc: N1_V02N0601 JF4
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arc: N1_V02N0701 JQ5
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arc: S1_V02S0301 H02W0301
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arc: S1_V02S0701 JF7
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arc: V01S0000 JF5
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.tile CIB_R22C27:CIB_DSP
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arc: E1_H01E0001 JF7
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arc: E1_H01E0101 JF2
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arc: E1_H02E0201 V02S0201
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arc: E1_H02E0701 V02S0701
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arc: H00R0000 V02S0601
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arc: H00R0100 V02S0501
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arc: H01W0000 JQ3
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arc: H01W0100 JF6
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arc: JB0 V02S0101
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arc: JB1 V02N0301
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arc: JB2 H00R0100
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arc: JB3 H02W0101
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arc: JB4 V02S0501
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arc: JB5 V02N0701
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arc: JB6 V02S0501
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arc: JB7 V02N0701
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arc: JD0 V02S0001
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arc: JD1 V00B0100
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arc: JD2 H00R0000
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arc: JD3 V00T0100
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arc: JD4 V02N0401
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arc: JD5 H00R0100
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arc: JD6 V02N0401
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arc: JD7 H00R0100
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arc: N1_V01N0001 JF4
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arc: N1_V01N0101 JF5
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arc: N1_V02N0001 JQ0
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arc: N1_V02N0101 E1_H01W0100
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arc: N1_V02N0201 JQ2
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arc: N1_V02N0301 JQ1
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arc: N1_V02N0401 JQ4
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arc: N1_V02N0501 H01E0101
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arc: N1_V02N0601 JQ6
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arc: N1_V02N0701 JQ7
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arc: V00B0100 E1_H02W0701
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arc: V00T0100 V02S0701
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arc: V01S0000 JQ5
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arc: V01S0100 S3_V06N0303
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arc: W1_H02W0101 JF1
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arc: W1_H02W0201 JF0
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arc: W1_H02W0301 JF3
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JA2MUX 0
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enum: CIB.JC3MUX 0
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enum: CIB.JA0MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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.tile CIB_R22C28:CIB_DSP
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arc: E1_H01E0001 JF1
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arc: E1_H01E0101 E3_H06W0203
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arc: E1_H02E0001 V02S0001
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arc: E1_H02E0201 V02N0201
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arc: E1_H02E0701 E3_H06W0203
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arc: H00R0000 V02S0601
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arc: H00R0100 V02N0701
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arc: H01W0100 JQ0
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arc: JB0 V00T0000
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arc: JB1 V02N0101
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arc: JB2 H00R0000
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arc: JB3 V02N0101
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arc: JB4 H00R0000
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arc: JB5 V02N0701
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arc: JB6 V00B0100
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arc: JB7 V02S0501
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arc: JD0 V02N0201
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arc: JD1 H00R0000
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arc: JD2 V02N0201
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arc: JD3 H00R0000
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arc: JD4 H00R0100
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arc: JD5 V02S0601
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arc: JD6 V02N0401
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arc: JD7 H02E0201
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arc: JLSR0 V00T0100
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arc: JLSR1 V00T0100
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arc: N1_V01N0001 JQ3
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arc: N1_V01N0101 JF0
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arc: N1_V02N0001 JQ2
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arc: N1_V02N0101 JF3
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arc: N1_V02N0201 JF2
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arc: N1_V02N0301 JQ1
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arc: N1_V02N0501 H01E0101
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arc: N1_V02N0601 H01E0001
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arc: V00B0100 H02E0701
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arc: V00T0000 V02S0601
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arc: V00T0100 E1_H02W0101
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arc: W1_H02W0101 V02N0101
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arc: W1_H02W0201 V02S0201
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arc: W1_H02W0301 V02N0301
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JC6MUX 0
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.tile CIB_R22C29:CIB_DSP
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arc: E1_H02E0401 V02S0401
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arc: H00R0100 H02E0701
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arc: JB0 V02N0101
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arc: JB1 V02N0301
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arc: JB2 H02W0301
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arc: JB3 E1_H02W0301
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arc: JB4 H01E0101
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arc: JB5 V02S0701
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arc: JB6 H01E0101
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arc: JB7 V02S0701
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arc: JD0 H02E0201
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arc: JD1 V02S0001
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arc: JD2 V00B0100
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arc: JD3 H02E0001
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arc: JD4 V02N0601
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arc: JD5 V00B0000
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arc: JD6 V02S0401
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arc: JD7 H00R0100
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arc: JLSR1 V00T0000
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arc: N1_V02N0201 H01E0001
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arc: V00B0000 V02N0001
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arc: V00B0100 E1_H02W0501
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arc: V00T0000 S1_V02N0601
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arc: W1_H02W0701 V02S0701
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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.tile CIB_R22C30:CIB_DSP
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arc: E1_H02E0101 S1_V02N0101
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arc: E1_H02E0201 V02S0201
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arc: E1_H02E0301 V02S0301
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arc: H00L0000 V02S0001
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arc: H00R0000 H02E0401
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arc: JB0 V00B0000
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arc: JB1 V02S0101
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arc: JB2 E1_H02W0301
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arc: JB3 H00R0000
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arc: JB4 H00L0000
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arc: JB5 V02S0701
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arc: JB6 V00B0000
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arc: JB7 V02S0701
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arc: JCE3 S1_V02N0601
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arc: JD0 H00R0000
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arc: JD1 V02S0001
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arc: JD2 H00R0000
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arc: JD3 V02S0001
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arc: JD4 V02S0401
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arc: JD5 V00B0000
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arc: JD6 V02S0401
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arc: JD7 V00B0000
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arc: JLSR0 V00B0100
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arc: JLSR1 V00B0100
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arc: N1_V02N0201 E1_H01W0000
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arc: N1_V02N0401 H02W0401
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arc: N1_V02N0501 E1_H02W0501
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arc: N1_V02N0701 E1_H01W0100
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arc: V00B0000 V02S0001
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arc: V00B0100 S1_V02N0101
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arc: W1_H02W0101 S1_V02N0101
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arc: W1_H02W0301 V02N0301
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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.tile CIB_R22C31:CIB_DSP
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arc: E1_H01E0001 JF1
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arc: E1_H01E0101 JQ0
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arc: E1_H02E0101 N1_V01S0100
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arc: E1_H02E0201 V02N0201
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arc: E1_H02E0401 JQ6
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arc: E1_H02E0501 JQ7
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arc: E1_H02E0701 JQ5
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arc: H00R0000 E1_H02W0401
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arc: H00R0100 V02N0501
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arc: H01W0000 JQ2
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arc: H01W0100 JQ1
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arc: JB0 V02N0101
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arc: JB1 H02W0101
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arc: JB2 H00R0100
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arc: JB3 H02E0301
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arc: JB4 V02N0701
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arc: JB5 V02S0501
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arc: JB6 E1_H02W0301
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arc: JB7 S1_V02N0501
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arc: JCE0 S1_V02N0201
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arc: JD0 V02S0001
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arc: JD1 H00R0000
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arc: JD2 V02S0201
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arc: JD3 V00B0100
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arc: JD4 H02E0201
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arc: JD5 V00B0000
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arc: JD6 V02S0601
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arc: JD7 V02S0401
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arc: JLSR0 V00T0000
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arc: JLSR1 V00T0100
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arc: N1_V01N0001 JF5
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arc: N1_V01N0101 JQ3
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arc: N1_V02N0001 JF2
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arc: N1_V02N0101 JF3
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arc: N1_V02N0201 JF0
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arc: N1_V02N0301 E1_H01W0100
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arc: N1_V02N0401 JF6
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arc: N1_V02N0501 JF7
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arc: N1_V02N0601 JQ4
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arc: N1_V02N0701 H02W0701
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arc: S1_V02S0201 E1_H01W0000
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arc: V00B0000 V02N0001
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arc: V00B0100 E1_H02W0501
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arc: V00T0000 S1_V02N0601
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arc: V00T0100 H02E0101
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arc: W1_H02W0301 V02N0301
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arc: W1_H02W0401 JF4
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arc: W1_H02W0501 V02N0501
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JA2MUX 0
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enum: CIB.JC3MUX 0
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enum: CIB.JA0MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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.tile CIB_R22C32:CIB_DSP
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arc: E1_H01E0001 JF1
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arc: E1_H01E0101 JQ7
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arc: E1_H02E0001 JQ0
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arc: E1_H02E0101 V02N0101
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arc: E1_H02E0201 V02N0201
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arc: E1_H02E0301 V02S0301
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arc: E1_H02E0601 JQ4
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arc: E3_H06E0103 W3_H06E0103
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arc: E3_H06E0303 W3_H06E0203
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arc: H01W0000 JF0
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arc: H01W0100 JF4
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arc: JB0 V00B0000
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arc: JB1 E1_H02W0101
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arc: JB2 H02W0301
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arc: JB3 E1_H02W0101
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arc: JB4 H02W0301
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arc: JB5 E1_H02W0101
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arc: JB6 V00B0000
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arc: JB7 E1_H02W0101
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arc: JD0 H02E0201
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arc: JD1 V02S0001
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arc: JD2 H02E0201
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arc: JD3 V02S0001
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arc: JD4 H02E0201
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arc: JD5 V00B0000
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arc: JD6 H02E0201
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arc: JD7 V00B0000
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arc: JLSR1 V00T0000
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arc: N1_V01N0001 JQ2
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arc: N1_V01N0101 JQ3
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arc: N1_V02N0001 H01E0001
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arc: N1_V02N0101 JQ1
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arc: N1_V02N0201 JF2
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arc: N1_V02N0301 JF3
|
|
arc: N1_V02N0401 JF6
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N1_V02N0601 JQ6
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0501 JF5
|
|
arc: W1_H02W0701 JF7
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C33:CIB_DSP
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02S0501
|
|
arc: JB0 V02S0301
|
|
arc: JB1 H02W0101
|
|
arc: JB2 H00R0000
|
|
arc: JB3 E1_H02W0301
|
|
arc: JB4 V00B0100
|
|
arc: JB5 V02S0701
|
|
arc: JB6 V00B0000
|
|
arc: JB7 H02E0301
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V02S0001
|
|
arc: JD2 V02S0201
|
|
arc: JD3 V02N0201
|
|
arc: JD4 V02S0601
|
|
arc: JD5 V02N0401
|
|
arc: JD6 H00R0100
|
|
arc: JD7 H02E0201
|
|
arc: JLSR0 E1_H02W0501
|
|
arc: JLSR1 H02W0301
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 V02N0501
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C34:CIB_DSP
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: JB0 H02E0101
|
|
arc: JB1 H02E0301
|
|
arc: JB2 H02E0101
|
|
arc: JB3 H02E0301
|
|
arc: JB4 H02E0101
|
|
arc: JB5 H01E0101
|
|
arc: JB6 H02E0101
|
|
arc: JB7 H01E0101
|
|
arc: JD0 V02N0201
|
|
arc: JD1 E1_H02W0001
|
|
arc: JD2 H02E0001
|
|
arc: JD3 V02S0201
|
|
arc: JD4 V02S0401
|
|
arc: JD5 V00B0000
|
|
arc: JD6 V02S0401
|
|
arc: JD7 V00B0000
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C35:CIB_DSP
|
|
arc: E1_H01E0001 JF7
|
|
arc: E1_H01E0101 JQ5
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H01W0000 JQ4
|
|
arc: JB0 W1_H02E0101
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 W1_H02E0101
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 H02E0101
|
|
arc: JB5 H02E0301
|
|
arc: JB6 V00B0100
|
|
arc: JB7 S1_V02N0501
|
|
arc: JCE0 S1_V02N0201
|
|
arc: JCE1 S1_V02N0201
|
|
arc: JCE2 H00L0000
|
|
arc: JCE3 H00L0000
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 V02S0201
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V02S0201
|
|
arc: JD4 E1_H02W0201
|
|
arc: JD5 V00B0000
|
|
arc: JD6 N1_V02S0401
|
|
arc: JD7 V02N0601
|
|
arc: N1_V01N0001 JQ7
|
|
arc: N1_V01N0101 JQ6
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 JF6
|
|
arc: N1_V02N0701 JF5
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
|
|
.tile CIB_R22C36:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: E1_H01E0101 JF7
|
|
arc: E1_H02E0001 JQ0
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0000 JF4
|
|
arc: H01W0100 JF6
|
|
arc: JB0 H00R0100
|
|
arc: JB1 H02W0301
|
|
arc: JB2 V01N0001
|
|
arc: JB3 V02N0101
|
|
arc: JB4 V02N0501
|
|
arc: JB5 V00B0100
|
|
arc: JB6 V02N0501
|
|
arc: JB7 V00B0100
|
|
arc: JD0 E1_H02W0201
|
|
arc: JD1 W1_H02E0001
|
|
arc: JD2 V02N0201
|
|
arc: JD3 V02N0001
|
|
arc: JD4 H00L0100
|
|
arc: JD5 V01N0001
|
|
arc: JD6 H00L0100
|
|
arc: JD7 V01N0001
|
|
arc: N1_V01N0001 JQ1
|
|
arc: N1_V01N0101 JF2
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 JQ3
|
|
arc: N1_V02N0201 JF0
|
|
arc: N1_V02N0301 JF3
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N1_V02N0601 JQ6
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 JQ2
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 JF1
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 JF5
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C37:CIB_DSP
|
|
arc: E1_H01E0001 JF3
|
|
arc: E1_H01E0101 JF1
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H01W0000 JQ0
|
|
arc: JB0 H02E0301
|
|
arc: JB1 H02E0101
|
|
arc: JB2 H02E0301
|
|
arc: JB3 H02E0101
|
|
arc: JB4 H02E0301
|
|
arc: JB5 H02E0101
|
|
arc: JB6 V00B0000
|
|
arc: JB7 N1_V02S0701
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 H02E0201
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 H02E0201
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 H02E0201
|
|
arc: JD6 H02W0001
|
|
arc: JD7 H00L0100
|
|
arc: JLSR0 V00T0100
|
|
arc: JLSR1 V00T0000
|
|
arc: N1_V01N0001 JF2
|
|
arc: N1_V01N0101 JQ2
|
|
arc: N1_V02N0101 JQ3
|
|
arc: N1_V02N0201 JF0
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 V02N0601
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C38:CIB_DSP
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: JB0 V00B0000
|
|
arc: JB1 H00R0100
|
|
arc: JB2 E1_H02W0301
|
|
arc: JB3 V02N0301
|
|
arc: JB4 H02E0101
|
|
arc: JB5 V02N0501
|
|
arc: JB6 H02E0101
|
|
arc: JB7 V02N0501
|
|
arc: JD0 V00T0100
|
|
arc: JD1 V00B0100
|
|
arc: JD2 V02N0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 H00L0100
|
|
arc: JD5 W1_H02E0201
|
|
arc: JD6 V02N0601
|
|
arc: JD7 H02E0201
|
|
arc: JLSR1 H02W0301
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C39:CIB_DSP
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: JB0 W1_H02E0101
|
|
arc: JB1 V02N0101
|
|
arc: JB2 W1_H02E0101
|
|
arc: JB3 V02N0101
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 V00B0100
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 V00B0000
|
|
arc: JCE3 V02N0601
|
|
arc: JD0 V02N0201
|
|
arc: JD1 W1_H02E0201
|
|
arc: JD2 V02N0201
|
|
arc: JD3 W1_H02E0201
|
|
arc: JD4 V00B0000
|
|
arc: JD5 W1_H02E0201
|
|
arc: JD6 V00B0000
|
|
arc: JD7 W1_H02E0201
|
|
arc: JLSR0 V00T0100
|
|
arc: JLSR1 V00T0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C40:CIB_DSP
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R22C41:CIB_DSP
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
|
|
.tile CIB_R22C42:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: E1_H01E0101 JQ3
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 JQ2
|
|
arc: E1_H02E0401 JQ6
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 H02W0301
|
|
arc: H01W0000 JQ1
|
|
arc: H01W0100 JQ5
|
|
arc: JB0 E1_H02W0301
|
|
arc: JB1 E1_H02W0101
|
|
arc: JB2 V02S0301
|
|
arc: JB3 H02E0301
|
|
arc: JB4 V02N0501
|
|
arc: JB5 H02W0101
|
|
arc: JB6 S1_V02N0501
|
|
arc: JB7 W1_H02E0101
|
|
arc: JCE0 H00L0100
|
|
arc: JD0 H02E0201
|
|
arc: JD1 V02N0001
|
|
arc: JD2 V00T0100
|
|
arc: JD3 V02N0201
|
|
arc: JD4 E1_H02W0201
|
|
arc: JD5 S1_V02N0401
|
|
arc: JD6 E1_H02W0001
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V01N0001 JQ0
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 JF3
|
|
arc: N1_V02N0201 JF2
|
|
arc: N1_V02N0301 JF1
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JF7
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0401 JF6
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C43:CIB_DSP
|
|
arc: E1_H01E0001 JF0
|
|
arc: E1_H01E0101 JF2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 JF4
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0000 JF3
|
|
arc: H01W0100 JF7
|
|
arc: JB0 H00R0100
|
|
arc: JB1 V02N0101
|
|
arc: JB2 H00R0100
|
|
arc: JB3 V02N0101
|
|
arc: JB4 V02N0501
|
|
arc: JB5 H00L0000
|
|
arc: JB6 V02N0501
|
|
arc: JB7 V00B0000
|
|
arc: JD0 E1_H02W0201
|
|
arc: JD1 H00R0000
|
|
arc: JD2 V02N0201
|
|
arc: JD3 H00R0000
|
|
arc: JD4 E1_H02W0201
|
|
arc: JD5 V02N0601
|
|
arc: JD6 E1_H02W0201
|
|
arc: JD7 V02N0601
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V01N0001 JF1
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N1_V02N0601 JQ6
|
|
arc: N1_V02N0701 JQ7
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0000 JQ3
|
|
arc: W1_H02W0001 JQ2
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 JF6
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C44:CIB_DSP
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: JB0 H00R0100
|
|
arc: JB1 V00T0000
|
|
arc: JB2 E1_H02W0301
|
|
arc: JB3 H02W0301
|
|
arc: JB4 E1_H02W0101
|
|
arc: JB5 H02W0101
|
|
arc: JB6 S1_V02N0701
|
|
arc: JB7 V00B0100
|
|
arc: JD0 H00R0000
|
|
arc: JD1 E1_H02W0201
|
|
arc: JD2 V02S0201
|
|
arc: JD3 H02E0201
|
|
arc: JD4 H00L0100
|
|
arc: JD5 H02W0001
|
|
arc: JD6 E1_H01W0100
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 V00T0100
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C45:CIB_DSP
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: JB0 H02E0101
|
|
arc: JB1 V02N0301
|
|
arc: JB2 H02E0101
|
|
arc: JB3 V02N0301
|
|
arc: JB4 H02E0101
|
|
arc: JB5 V00B0100
|
|
arc: JB6 H02E0101
|
|
arc: JB7 V00B0100
|
|
arc: JD0 E1_H02W0201
|
|
arc: JD1 V02N0201
|
|
arc: JD2 H02W0001
|
|
arc: JD3 H02E0201
|
|
arc: JD4 H02W0001
|
|
arc: JD5 H02E0201
|
|
arc: JD6 H02W0001
|
|
arc: JD7 H02E0201
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W3_H06W0003 N1_V01S0000
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C46:CIB_DSP
|
|
arc: E1_H01E0101 JQ6
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H01W0000 JQ5
|
|
arc: JB0 E1_H02W0101
|
|
arc: JB1 V00B0000
|
|
arc: JB2 E1_H02W0101
|
|
arc: JB3 H00L0000
|
|
arc: JB4 W1_H02E0301
|
|
arc: JB5 H00R0000
|
|
arc: JB6 E1_H02W0101
|
|
arc: JB7 V00B0000
|
|
arc: JCE0 H00L0100
|
|
arc: JCE1 H00L0100
|
|
arc: JCE2 H00L0100
|
|
arc: JCE3 H00L0100
|
|
arc: JD0 V02N0001
|
|
arc: JD1 V00T0100
|
|
arc: JD2 V02N0001
|
|
arc: JD3 V00T0100
|
|
arc: JD4 E1_H01W0100
|
|
arc: JD5 W1_H02E0001
|
|
arc: JD6 H02W0201
|
|
arc: JD7 H02E0201
|
|
arc: N1_V01N0001 JQ7
|
|
arc: N1_V01N0101 JQ4
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 JF6
|
|
arc: N1_V02N0701 JF5
|
|
arc: S1_V02S0701 JF7
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile CIB_R22C47:CIB_DSP
|
|
arc: E1_H01E0001 JF4
|
|
arc: E1_H01E0101 JF0
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0601 JQ4
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0000 JF1
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: JB0 V02N0301
|
|
arc: JB1 H00R0100
|
|
arc: JB2 E1_H02W0101
|
|
arc: JB3 H02W0301
|
|
arc: JB4 E1_H02W0101
|
|
arc: JB5 H02W0301
|
|
arc: JB6 E1_H02W0101
|
|
arc: JB7 H02W0301
|
|
arc: JD0 H00R0000
|
|
arc: JD1 E1_H02W0201
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V02N0001
|
|
arc: JD4 H02W0001
|
|
arc: JD5 E1_H02W0001
|
|
arc: JD6 H02W0001
|
|
arc: JD7 E1_H02W0001
|
|
arc: N1_V01N0001 JF5
|
|
arc: N1_V01N0101 JQ3
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 JQ0
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0401 JF6
|
|
arc: N1_V02N0501 JQ7
|
|
arc: N1_V02N0601 JQ6
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V01S0000 JQ5
|
|
arc: W1_H02W0001 JF2
|
|
arc: W1_H02W0101 JF3
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 JF7
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C48:CIB_DSP
|
|
arc: E1_H01E0001 JF2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0100 JQ2
|
|
arc: JB0 V00T0000
|
|
arc: JB1 V02N0301
|
|
arc: JB2 H02W0101
|
|
arc: JB3 V02N0301
|
|
arc: JB4 H02W0101
|
|
arc: JB5 V00B0100
|
|
arc: JB6 H02W0301
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 V02N0001
|
|
arc: JD1 E1_H02W0001
|
|
arc: JD2 V02N0001
|
|
arc: JD3 E1_H02W0001
|
|
arc: JD4 V00B0000
|
|
arc: JD5 E1_H02W0001
|
|
arc: JD6 H00R0100
|
|
arc: JD7 V02N0401
|
|
arc: JLSR0 V00T0100
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0001 JF3
|
|
arc: N1_V01N0101 JQ1
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0101 JQ3
|
|
arc: N1_V02N0201 JF0
|
|
arc: N1_V02N0301 JF1
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C49:CIB_DSP
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H02E0301
|
|
arc: JB3 E1_H02W0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 H02W0101
|
|
arc: JB6 V00B0000
|
|
arc: JB7 H02W0101
|
|
arc: JD0 S1_V02N0201
|
|
arc: JD1 H02E0201
|
|
arc: JD2 H02W0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 E1_H02W0201
|
|
arc: JD5 V02S0601
|
|
arc: JD6 H00L0100
|
|
arc: JD7 V00B0000
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C50:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: JB0 V01N0001
|
|
arc: JB1 V02N0101
|
|
arc: JB2 V01N0001
|
|
arc: JB3 V02N0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 V00B0100
|
|
arc: JB6 V00T0000
|
|
arc: JB7 V00B0100
|
|
arc: JCE3 H02W0101
|
|
arc: JD0 V00B0100
|
|
arc: JD1 S1_V02N0001
|
|
arc: JD2 V00B0100
|
|
arc: JD3 S1_V02N0001
|
|
arc: JD4 H00L0100
|
|
arc: JD5 V01N0001
|
|
arc: JD6 H00L0100
|
|
arc: JD7 V01N0001
|
|
arc: JLSR0 V00B0000
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W3_H06W0003 V01N0001
|
|
arc: W3_H06W0103 V01N0101
|
|
arc: W3_H06W0303 V01N0101
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C51:CIB_DSP
|
|
arc: E1_H01E0001 JQ2
|
|
arc: E1_H01E0101 JQ3
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 H02E0601
|
|
arc: H01W0000 JQ6
|
|
arc: H01W0100 JF2
|
|
arc: JB0 V02N0101
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 W1_H02E0301
|
|
arc: JB3 H02W0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 S1_V02N0501
|
|
arc: JB6 V00T0000
|
|
arc: JB7 V00B0000
|
|
arc: JCE0 E1_H02W0101
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 H02E0001
|
|
arc: JD2 V00B0100
|
|
arc: JD3 V00T0100
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 E1_H02W0001
|
|
arc: JD6 E1_H01W0100
|
|
arc: JD7 H02W0201
|
|
arc: JLSR0 H02E0501
|
|
arc: JLSR1 H02E0501
|
|
arc: N1_V01N0001 JQ7
|
|
arc: N1_V01N0101 JQ1
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 JQ0
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JF5
|
|
arc: N1_V02N0701 JQ5
|
|
arc: S1_V02S0001 JF0
|
|
arc: S1_V02S0101 JF3
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 JF1
|
|
arc: S1_V02S0401 JF6
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 JF4
|
|
arc: S1_V02S0701 JF7
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C52:CIB_DSP
|
|
arc: E1_H01E0001 JF2
|
|
arc: E1_H01E0101 JQ4
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 V02N0601
|
|
arc: H01W0000 JF0
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 V00T0000
|
|
arc: JB1 E1_H01W0100
|
|
arc: JB2 H00R0000
|
|
arc: JB3 E1_H01W0100
|
|
arc: JB4 H00R0000
|
|
arc: JB5 V00B0100
|
|
arc: JB6 V00T0000
|
|
arc: JB7 V00B0100
|
|
arc: JD0 V02N0001
|
|
arc: JD1 H00R0000
|
|
arc: JD2 V02N0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 E1_H01W0100
|
|
arc: JD5 V02N0601
|
|
arc: JD6 E1_H01W0100
|
|
arc: JD7 V02N0601
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0001 JQ7
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0101 JQ3
|
|
arc: N1_V02N0201 JQ0
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0401 JQ6
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0301 JF1
|
|
arc: S1_V02S0401 JF6
|
|
arc: S1_V02S0501 JF7
|
|
arc: S1_V02S0601 JF4
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02W0101
|
|
arc: V01S0000 JF3
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 JF5
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C53:CIB_DSP
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 H00R0100
|
|
arc: JB1 H01W0100
|
|
arc: JB2 E1_H01W0100
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 V02N0501
|
|
arc: JB5 H00R0000
|
|
arc: JB6 E1_H02W0101
|
|
arc: JB7 H02W0101
|
|
arc: JD0 S1_V02N0001
|
|
arc: JD1 V00T0100
|
|
arc: JD2 N1_V02S0201
|
|
arc: JD3 V02N0001
|
|
arc: JD4 H00L0100
|
|
arc: JD5 H02E0201
|
|
arc: JD6 S1_V02N0601
|
|
arc: JD7 V02N0401
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W3_H06W0003 V01N0001
|
|
arc: W3_H06W0103 V01N0101
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C54:CIB_DSP
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 V00B0100
|
|
arc: JD1 H00R0000
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V00T0100
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 H00R0100
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 H00R0100
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0103 V01N0101
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C55:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: E1_H01E0101 JQ4
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H01W0000 JQ5
|
|
arc: JB0 V02N0101
|
|
arc: JB1 S1_V02N0301
|
|
arc: JB2 V02N0101
|
|
arc: JB3 S1_V02N0301
|
|
arc: JB4 H02E0101
|
|
arc: JB5 V00B0100
|
|
arc: JB6 V02N0701
|
|
arc: JB7 E1_H02W0101
|
|
arc: JCE0 H00L0000
|
|
arc: JCE1 H00L0000
|
|
arc: JCE2 H00L0000
|
|
arc: JCE3 H00L0000
|
|
arc: JD0 S1_V02N0201
|
|
arc: JD1 V02N0201
|
|
arc: JD2 S1_V02N0201
|
|
arc: JD3 V02N0201
|
|
arc: JD4 V02N0401
|
|
arc: JD5 H02E0201
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 V02N0601
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 JF6
|
|
arc: N1_V02N0501 JF7
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 JF5
|
|
arc: S1_V02S0401 JQ6
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W3_H06W0003 V01N0001
|
|
|
|
.tile CIB_R22C56:CIB_DSP
|
|
arc: E1_H01E0001 JF7
|
|
arc: E1_H01E0101 JF1
|
|
arc: E1_H02E0001 JQ2
|
|
arc: E1_H02E0401 JQ6
|
|
arc: E1_H02E0501 JQ7
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 JF4
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0000 JQ3
|
|
arc: H01W0100 JF2
|
|
arc: JB0 V02S0101
|
|
arc: JB1 H00R0100
|
|
arc: JB2 H02E0101
|
|
arc: JB3 V02N0101
|
|
arc: JB4 H02E0101
|
|
arc: JB5 V02N0501
|
|
arc: JB6 H02E0101
|
|
arc: JB7 V00T0000
|
|
arc: JD0 E1_H02W0001
|
|
arc: JD1 V02N0001
|
|
arc: JD2 V02N0201
|
|
arc: JD3 H00R0000
|
|
arc: JD4 H02E0001
|
|
arc: JD5 V02N0401
|
|
arc: JD6 H02E0001
|
|
arc: JD7 V02N0401
|
|
arc: N1_V01N0001 JF5
|
|
arc: N1_V01N0101 JQ0
|
|
arc: N1_V02N0301 JF3
|
|
arc: N1_V02N0601 JF6
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 JQ1
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 JQ4
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 JQ5
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 JF0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C57:CIB_DSP
|
|
arc: E1_H01E0001 JF2
|
|
arc: E1_H01E0101 JF1
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H01W0000 JQ1
|
|
arc: H01W0100 JQ2
|
|
arc: JB0 V00B0000
|
|
arc: JB1 V00T0000
|
|
arc: JB2 H00L0000
|
|
arc: JB3 H00R0000
|
|
arc: JB4 H00L0000
|
|
arc: JB5 H00R0000
|
|
arc: JB6 V02N0701
|
|
arc: JB7 H02W0101
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V02N0201
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V02N0201
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 V00B0000
|
|
arc: JD6 S1_V02N0601
|
|
arc: JD7 V02N0601
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V02N0101 JF3
|
|
arc: N1_V02N0201 JF0
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 JQ0
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V01S0000 JQ3
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C58:CIB_DSP
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: JB0 S1_V02N0101
|
|
arc: JB1 S1_V02N0301
|
|
arc: JB2 E1_H02W0101
|
|
arc: JB3 H02W0101
|
|
arc: JB4 S1_V02N0501
|
|
arc: JB5 V02N0701
|
|
arc: JB6 S1_V02N0501
|
|
arc: JB7 V02N0701
|
|
arc: JD0 V00T0100
|
|
arc: JD1 V02N0001
|
|
arc: JD2 V02N0201
|
|
arc: JD3 H00R0000
|
|
arc: JD4 V02N0601
|
|
arc: JD5 H00R0100
|
|
arc: JD6 H02W0201
|
|
arc: JD7 H02W0001
|
|
arc: JLSR1 V00B0000
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C59:CIB_DSP
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00R0100 V02N0701
|
|
arc: JB0 V00B0000
|
|
arc: JB1 H00R0100
|
|
arc: JB2 V02N0101
|
|
arc: JB3 H00R0100
|
|
arc: JB4 V02N0501
|
|
arc: JB5 V02N0701
|
|
arc: JB6 V00B0000
|
|
arc: JB7 V02N0701
|
|
arc: JCE3 V02N0601
|
|
arc: JD0 V00B0100
|
|
arc: JD1 V02N0201
|
|
arc: JD2 V00B0100
|
|
arc: JD3 V02N0201
|
|
arc: JD4 H00R0100
|
|
arc: JD5 V02N0401
|
|
arc: JD6 H00R0100
|
|
arc: JD7 V02N0401
|
|
arc: JLSR0 V00T0000
|
|
arc: JLSR1 V00T0000
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0601 V02N0601
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C60:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: E1_H01E0101 JF0
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 JQ3
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 JQ5
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: H01W0100 JQ0
|
|
arc: JB0 W1_H02E0301
|
|
arc: JB1 E1_H01W0100
|
|
arc: JB2 V02N0301
|
|
arc: JB3 S1_V02N0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 S1_V02N0501
|
|
arc: JB6 V00T0000
|
|
arc: JB7 H02E0301
|
|
arc: JCE0 H00R0100
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V00T0100
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 S1_V02N0201
|
|
arc: JD4 S1_V02N0401
|
|
arc: JD5 H01W0000
|
|
arc: JD6 S1_V02N0601
|
|
arc: JD7 V02N0401
|
|
arc: JLSR0 V00B0000
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V01N0001 JQ1
|
|
arc: N1_V01N0101 JQ4
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 JF3
|
|
arc: N1_V02N0201 JF2
|
|
arc: N1_V02N0301 JF1
|
|
arc: N1_V02N0401 JF6
|
|
arc: N1_V02N0501 JF7
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 JF5
|
|
arc: S1_V02S0401 JQ6
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 JQ2
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C61:CIB_DSP
|
|
arc: E1_H01E0001 JF1
|
|
arc: E1_H01E0101 JF2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 JQ4
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 JF7
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 V00B0100
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 V00B0100
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 V00B0100
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V00B0100
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 H00R0100
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 H00R0100
|
|
arc: JLSR1 H02W0501
|
|
arc: N1_V01N0001 JF3
|
|
arc: N1_V01N0101 JQ0
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 JQ7
|
|
arc: N1_V02N0601 JF6
|
|
arc: N1_V02N0701 JQ5
|
|
arc: S1_V02S0401 JF4
|
|
arc: S1_V02S0501 JF5
|
|
arc: V00B0100 H02E0501
|
|
arc: V01S0000 JQ3
|
|
arc: W1_H02W0601 JQ6
|
|
arc: W1_H02W0701 V02N0701
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C62:CIB_DSP
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: JB0 H00R0100
|
|
arc: JB1 H02E0301
|
|
arc: JB2 V02S0301
|
|
arc: JB3 V02S0101
|
|
arc: JB4 H02W0301
|
|
arc: JB5 H02W0101
|
|
arc: JB6 V02N0501
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 S1_V02N0001
|
|
arc: JD1 V00B0100
|
|
arc: JD2 H00R0000
|
|
arc: JD3 V02N0001
|
|
arc: JD4 V02N0601
|
|
arc: JD5 W1_H02E0001
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 V00T0000
|
|
arc: JLSR1 V00T0000
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0501 V06N0303
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C63:CIB_DSP
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 H02W0601
|
|
arc: JB0 W1_H02E0101
|
|
arc: JB1 S1_V02N0301
|
|
arc: JB2 W1_H02E0101
|
|
arc: JB3 S1_V02N0301
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 S1_V02N0701
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 S1_V02N0701
|
|
arc: JD0 V02N0201
|
|
arc: JD1 H00R0000
|
|
arc: JD2 S1_V02N0001
|
|
arc: JD3 H02E0201
|
|
arc: JD4 S1_V02N0401
|
|
arc: JD5 H02E0201
|
|
arc: JD6 S1_V02N0401
|
|
arc: JD7 H02E0201
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C64:CIB_DSP
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 JQ7
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 JQ4
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H01W0000 JF6
|
|
arc: H01W0100 JF7
|
|
arc: JB0 V02N0101
|
|
arc: JB1 S1_V02N0301
|
|
arc: JB2 V02N0101
|
|
arc: JB3 S1_V02N0301
|
|
arc: JB4 V00B0100
|
|
arc: JB5 H02W0301
|
|
arc: JB6 V00T0000
|
|
arc: JB7 V02N0701
|
|
arc: JCE0 H00R0000
|
|
arc: JCE1 H00R0000
|
|
arc: JCE2 H00R0000
|
|
arc: JCE3 H00R0000
|
|
arc: JD0 S1_V02N0001
|
|
arc: JD1 V02N0201
|
|
arc: JD2 S1_V02N0001
|
|
arc: JD3 V02N0201
|
|
arc: JD4 H02E0001
|
|
arc: JD5 H00L0100
|
|
arc: JD6 V00B0000
|
|
arc: JD7 W1_H02E0001
|
|
arc: N1_V01N0001 JQ6
|
|
arc: N1_V01N0101 JQ5
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0601 JF4
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: W1_H02W0701 JF5
|
|
|
|
.tile CIB_R22C65:CIB_DSP
|
|
arc: E1_H01E0001 JF3
|
|
arc: E1_H01E0101 JQ1
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 JQ2
|
|
arc: E3_H06E0203 JQ4
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 JF2
|
|
arc: H01W0100 JF7
|
|
arc: JB0 V02S0101
|
|
arc: JB1 V00T0000
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 V00B0100
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 V00B0100
|
|
arc: JB7 W1_H02E0101
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 H02E0001
|
|
arc: JD2 H02W0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 V00B0000
|
|
arc: JD5 H00R0100
|
|
arc: JD6 V00B0000
|
|
arc: JD7 H00R0100
|
|
arc: N1_V01N0001 JF6
|
|
arc: N1_V01N0101 JQ3
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0101 JF1
|
|
arc: N1_V02N0201 JF0
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0501 JQ7
|
|
arc: N1_V02N0601 JQ6
|
|
arc: N1_V02N0701 JQ5
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 JF5
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C66:CIB_DSP
|
|
arc: E1_H01E0001 JF3
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 JQ3
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: JB0 V00B0000
|
|
arc: JB1 V02N0101
|
|
arc: JB2 H00R0100
|
|
arc: JB3 V02N0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 V00B0100
|
|
arc: JB6 S1_V02N0701
|
|
arc: JB7 H02W0301
|
|
arc: JD0 V00B0100
|
|
arc: JD1 H00R0000
|
|
arc: JD2 V00B0100
|
|
arc: JD3 H00R0000
|
|
arc: JD4 H00L0100
|
|
arc: JD5 H00R0100
|
|
arc: JD6 V02N0401
|
|
arc: JD7 V02N0601
|
|
arc: JLSR0 V00T0100
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0001 JQ0
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0101 JF1
|
|
arc: N1_V02N0201 JF2
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0001 JF0
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 JQ1
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C67:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 V02N0601
|
|
arc: JB0 V02N0301
|
|
arc: JB1 V02N0101
|
|
arc: JB2 H00R0000
|
|
arc: JB3 H02W0101
|
|
arc: JB4 W1_H02E0301
|
|
arc: JB5 V02N0501
|
|
arc: JB6 W1_H02E0301
|
|
arc: JB7 V02N0501
|
|
arc: JD0 V02N0001
|
|
arc: JD1 H02E0201
|
|
arc: JD2 V02N0201
|
|
arc: JD3 S1_V02N0201
|
|
arc: JD4 H02W0201
|
|
arc: JD5 V02N0401
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 H00L0100
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00B0000 H02W0601
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C68:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: JB0 H00R0100
|
|
arc: JB1 V00T0000
|
|
arc: JB2 H00R0100
|
|
arc: JB3 H00R0000
|
|
arc: JB4 V02N0501
|
|
arc: JB5 V02N0701
|
|
arc: JB6 V02N0501
|
|
arc: JB7 V02N0701
|
|
arc: JCE3 V02N0601
|
|
arc: JD0 V00T0100
|
|
arc: JD1 V00B0100
|
|
arc: JD2 H00R0000
|
|
arc: JD3 V00B0100
|
|
arc: JD4 V02N0401
|
|
arc: JD5 H00R0100
|
|
arc: JD6 V02N0401
|
|
arc: JD7 H00R0100
|
|
arc: JLSR0 H02W0501
|
|
arc: JLSR1 H02W0501
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0601 V02N0601
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C69:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: H01W0000 JQ6
|
|
arc: H01W0100 JQ2
|
|
arc: JB0 S1_V02N0301
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 H02E0301
|
|
arc: JB3 V02S0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 H02W0101
|
|
arc: JB6 V00B0100
|
|
arc: JB7 H02E0101
|
|
arc: JCE0 H00L0100
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V02N0201
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V02N0001
|
|
arc: JD4 H00R0100
|
|
arc: JD5 V00B0000
|
|
arc: JD6 V02N0401
|
|
arc: JD7 V02S0401
|
|
arc: JLSR0 V00T0100
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0001 JQ3
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 JF2
|
|
arc: N1_V02N0301 JF3
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 JF6
|
|
arc: N1_V02N0701 JQ5
|
|
arc: N3_V06N0103 JQ1
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 JF1
|
|
arc: S1_V02S0401 JQ4
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: S1_V02S0701 JF7
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 V02N0501
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C70:CIB_DSP
|
|
arc: E1_H01E0001 JF7
|
|
arc: E1_H01E0101 JF0
|
|
arc: E1_H02E0001 JQ0
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 JQ6
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: H01W0000 JF3
|
|
arc: H01W0100 JF4
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 V00B0100
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 V00B0100
|
|
arc: JB7 W1_H02E0101
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 V00B0100
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V00B0100
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 H00R0100
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 H00R0100
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V01N0001 JF5
|
|
arc: N1_V01N0101 JF1
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 JQ3
|
|
arc: N1_V02N0401 JF6
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 JQ4
|
|
arc: N1_V02N0701 JQ7
|
|
arc: S1_V02S0501 JQ5
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 JF2
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C71:CIB_DSP
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: JB0 V00T0000
|
|
arc: JB1 H02W0101
|
|
arc: JB2 H00L0000
|
|
arc: JB3 V02N0101
|
|
arc: JB4 V02S0701
|
|
arc: JB5 V02N0701
|
|
arc: JB6 H02E0301
|
|
arc: JB7 V00B0000
|
|
arc: JD0 H02W0201
|
|
arc: JD1 H00R0000
|
|
arc: JD2 V02S0201
|
|
arc: JD3 V02S0001
|
|
arc: JD4 H00R0100
|
|
arc: JD5 W1_H02E0201
|
|
arc: JD6 H02W0201
|
|
arc: JD7 S1_V02N0601
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0601 V02N0601
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C72:CIB_DSP
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: JB0 H02W0101
|
|
arc: JB1 V00B0000
|
|
arc: JB2 H02W0101
|
|
arc: JB3 H00R0000
|
|
arc: JB4 H02W0101
|
|
arc: JB5 H00R0000
|
|
arc: JB6 H02W0101
|
|
arc: JB7 V00B0000
|
|
arc: JD0 H02E0001
|
|
arc: JD1 V02N0201
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 V00T0100
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 V02N0401
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 V02N0401
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0303 E1_H02W0601
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C73:CIB_DSP
|
|
arc: E1_H01E0001 JF7
|
|
arc: E1_H01E0101 JF4
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: H01W0000 JQ7
|
|
arc: JB0 V02N0101
|
|
arc: JB1 V02N0301
|
|
arc: JB2 V02N0101
|
|
arc: JB3 V02N0301
|
|
arc: JB4 H02W0301
|
|
arc: JB5 H01E0101
|
|
arc: JB6 V00B0100
|
|
arc: JB7 V00B0000
|
|
arc: JCE0 H00R0000
|
|
arc: JCE1 H00R0000
|
|
arc: JCE2 H00R0000
|
|
arc: JCE3 H00R0000
|
|
arc: JD0 H02E0201
|
|
arc: JD1 V02N0201
|
|
arc: JD2 H02E0201
|
|
arc: JD3 V02N0201
|
|
arc: JD4 S1_V02N0601
|
|
arc: JD5 H00R0100
|
|
arc: JD6 S1_V02N0401
|
|
arc: JD7 H00L0100
|
|
arc: N1_V01N0001 JF5
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 JF6
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 JQ6
|
|
arc: S1_V02S0501 JQ5
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V01S0000 JQ4
|
|
arc: W1_H02W0101 V02N0101
|
|
|
|
.tile CIB_R22C74:CIB_DSP
|
|
arc: E1_H01E0001 JF3
|
|
arc: E1_H01E0101 JF6
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 JQ1
|
|
arc: E1_H02E0201 JF2
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0000 JQ3
|
|
arc: JB0 H00R0100
|
|
arc: JB1 H02W0101
|
|
arc: JB2 H00L0000
|
|
arc: JB3 H02E0101
|
|
arc: JB4 H00L0000
|
|
arc: JB5 H02E0301
|
|
arc: JB6 V00B0000
|
|
arc: JB7 H02E0101
|
|
arc: JD0 V02N0201
|
|
arc: JD1 H02E0001
|
|
arc: JD2 H00R0000
|
|
arc: JD3 V02N0001
|
|
arc: JD4 H00L0100
|
|
arc: JD5 H02E0201
|
|
arc: JD6 H00L0100
|
|
arc: JD7 H02E0201
|
|
arc: N1_V01N0001 JF5
|
|
arc: N1_V01N0101 JQ6
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 JF1
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 JF7
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 JQ2
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 JQ4
|
|
arc: S1_V02S0701 JQ5
|
|
arc: V00B0000 H02E0601
|
|
arc: V01S0000 JQ7
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C75:CIB_DSP
|
|
arc: E1_H01E0001 JF3
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: H01W0000 JQ1
|
|
arc: H01W0100 JQ0
|
|
arc: JB0 V00B0000
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00R0000
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 V00B0100
|
|
arc: JB6 V02N0701
|
|
arc: JB7 H02E0301
|
|
arc: JD0 V00B0100
|
|
arc: JD1 W1_H02E0201
|
|
arc: JD2 V00B0100
|
|
arc: JD3 W1_H02E0201
|
|
arc: JD4 H00R0100
|
|
arc: JD5 W1_H02E0201
|
|
arc: JD6 E1_H02W0201
|
|
arc: JD7 V02N0601
|
|
arc: JLSR0 V00T0000
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 JF2
|
|
arc: N1_V02N0101 JF1
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0001 JQ2
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 JF0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C76:CIB_DSP
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: JB0 V02N0301
|
|
arc: JB1 V00T0000
|
|
arc: JB2 H02E0101
|
|
arc: JB3 S1_V02N0301
|
|
arc: JB4 V02N0701
|
|
arc: JB5 S1_V02N0501
|
|
arc: JB6 V02N0701
|
|
arc: JB7 S1_V02N0501
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 H00R0000
|
|
arc: JD2 V02N0001
|
|
arc: JD3 V00B0100
|
|
arc: JD4 E1_H02W0201
|
|
arc: JD5 V00B0000
|
|
arc: JD6 H02E0201
|
|
arc: JD7 H00R0100
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C77:CIB_DSP
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: JB0 V02N0101
|
|
arc: JB1 V02N0301
|
|
arc: JB2 V02N0101
|
|
arc: JB3 V02N0301
|
|
arc: JB4 V02N0501
|
|
arc: JB5 H00L0000
|
|
arc: JB6 V02N0501
|
|
arc: JB7 V00B0100
|
|
arc: JCE3 H02W0101
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V02N0001
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 V02N0001
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 V00B0000
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 V00T0000
|
|
arc: JLSR1 V00T0000
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C78:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: E1_H01E0101 JF6
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 JQ1
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0000 JF7
|
|
arc: H01W0100 JF1
|
|
arc: JB0 E1_H01W0100
|
|
arc: JB1 H02W0301
|
|
arc: JB2 H00L0000
|
|
arc: JB3 V02N0101
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 H02W0101
|
|
arc: JB6 V00B0000
|
|
arc: JB7 H02E0301
|
|
arc: JCE0 E1_H02W0101
|
|
arc: JD0 V00B0100
|
|
arc: JD1 H00R0000
|
|
arc: JD2 H02E0001
|
|
arc: JD3 V00T0100
|
|
arc: JD4 H02E0201
|
|
arc: JD5 H00R0100
|
|
arc: JD6 V02N0401
|
|
arc: JD7 H00L0100
|
|
arc: JLSR0 V00T0000
|
|
arc: JLSR1 V00T0000
|
|
arc: N1_V01N0001 JQ5
|
|
arc: N1_V01N0101 JQ0
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0101 JQ3
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 JQ6
|
|
arc: N1_V02N0601 JQ4
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 JF0
|
|
arc: S1_V02S0101 JF3
|
|
arc: S1_V02S0201 JF2
|
|
arc: S1_V02S0601 JF4
|
|
arc: S1_V02S0701 JF5
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W3_H06W0203 V01N0001
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C79:CIB_DSP
|
|
arc: E1_H01E0001 JF3
|
|
arc: E1_H01E0101 JF6
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 JF7
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: H01W0000 JQ3
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 V00B0100
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 V00B0100
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 E1_H02W0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 E1_H02W0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 E1_H02W0201
|
|
arc: JD5 H00R0100
|
|
arc: JD6 E1_H02W0201
|
|
arc: JD7 H00R0100
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V01N0001 JQ2
|
|
arc: N1_V01N0101 JF2
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ0
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JQ7
|
|
arc: N1_V02N0701 JQ5
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0101 JF1
|
|
arc: S1_V02S0201 JF0
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0401 JQ6
|
|
arc: S1_V02S0501 JF5
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V01S0000 JF4
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0301 V02N0301
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C80:CIB_DSP
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 S1_V02N0301
|
|
arc: JB1 E1_H01W0100
|
|
arc: JB2 H00R0100
|
|
arc: JB3 E1_H02W0301
|
|
arc: JB4 H02E0301
|
|
arc: JB5 V02N0501
|
|
arc: JB6 H02W0101
|
|
arc: JB7 V02N0701
|
|
arc: JD0 H02W0201
|
|
arc: JD1 H02E0001
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 H00R0000
|
|
arc: JD4 V02N0601
|
|
arc: JD5 V02S0401
|
|
arc: JD6 V00B0000
|
|
arc: JD7 V02N0401
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C81:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0100 H02W0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 V02N0701
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 V02N0701
|
|
arc: JB7 W1_H02E0101
|
|
arc: JD0 V02N0001
|
|
arc: JD1 V02N0201
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 H00R0100
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 H00R0100
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: V00B0100 H02W0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C82:CIB_DSP
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: H01W0000 JQ4
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 H01W0100
|
|
arc: JB1 H02E0101
|
|
arc: JB2 H01W0100
|
|
arc: JB3 H00R0000
|
|
arc: JB4 E1_H02W0101
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 V02N0701
|
|
arc: JB7 W1_H02E0301
|
|
arc: JCE0 H00L0100
|
|
arc: JCE1 H00L0000
|
|
arc: JCE2 H00L0100
|
|
arc: JCE3 H00L0100
|
|
arc: JD0 H02E0201
|
|
arc: JD1 V00T0100
|
|
arc: JD2 H02E0201
|
|
arc: JD3 V00T0100
|
|
arc: JD4 V02N0601
|
|
arc: JD5 H00R0100
|
|
arc: JD6 H02W0201
|
|
arc: JD7 V00B0000
|
|
arc: N1_V01N0001 JQ5
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 JQ6
|
|
arc: N1_V02N0501 JF7
|
|
arc: N1_V02N0601 JF6
|
|
arc: N1_V02N0701 JF5
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 JF4
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 JQ7
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile CIB_R22C83:CIB_DSP
|
|
arc: E1_H01E0001 JF6
|
|
arc: E1_H01E0101 JF3
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0000 JF1
|
|
arc: H01W0100 JF7
|
|
arc: JB0 S1_V02N0101
|
|
arc: JB1 H00R0100
|
|
arc: JB2 H02E0301
|
|
arc: JB3 V02S0101
|
|
arc: JB4 H02E0301
|
|
arc: JB5 V02S0701
|
|
arc: JB6 H02E0301
|
|
arc: JB7 V02S0701
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 V02S0401
|
|
arc: JD5 H02E0201
|
|
arc: JD6 V02S0401
|
|
arc: JD7 H02E0201
|
|
arc: N1_V01N0001 JF5
|
|
arc: N1_V01N0101 JQ6
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 JF2
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 JQ7
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0301 JQ3
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 JF0
|
|
arc: W1_H02W0201 V02N0201
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C84:CIB_DSP
|
|
arc: E1_H01E0001 JQ2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H01W0100 JQ0
|
|
arc: JB0 V00B0000
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00R0000
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 H02E0101
|
|
arc: JB7 V02N0501
|
|
arc: JD0 V02S0201
|
|
arc: JD1 W1_H02E0201
|
|
arc: JD2 V02S0201
|
|
arc: JD3 W1_H02E0201
|
|
arc: JD4 V02S0601
|
|
arc: JD5 W1_H02E0201
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 V02N0601
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: N1_V01N0001 JQ1
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 JF3
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V01S0000 JQ3
|
|
arc: W1_H02W0001 JF2
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 JF1
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C85:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: JB0 H02E0301
|
|
arc: JB1 H02W0101
|
|
arc: JB2 V02N0101
|
|
arc: JB3 E1_H01W0100
|
|
arc: JB4 H00L0000
|
|
arc: JB5 V02N0501
|
|
arc: JB6 V00T0000
|
|
arc: JB7 V02N0501
|
|
arc: JD0 V02N0001
|
|
arc: JD1 H02W0001
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 H02E0201
|
|
arc: JD4 H01W0000
|
|
arc: JD5 H02E0001
|
|
arc: JD6 V02N0601
|
|
arc: JD7 W1_H02E0001
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 W1_H02E0001
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C86:CIB_DSP
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 H02E0101
|
|
arc: JB1 E1_H01W0100
|
|
arc: JB2 H02E0101
|
|
arc: JB3 E1_H01W0100
|
|
arc: JB4 H02E0101
|
|
arc: JB5 H02W0301
|
|
arc: JB6 H02E0101
|
|
arc: JB7 H02W0301
|
|
arc: JCE3 S1_V02N0601
|
|
arc: JD0 H02W0001
|
|
arc: JD1 H02E0001
|
|
arc: JD2 H02W0001
|
|
arc: JD3 H02E0001
|
|
arc: JD4 E1_H01W0100
|
|
arc: JD5 H02E0001
|
|
arc: JD6 E1_H01W0100
|
|
arc: JD7 H02E0001
|
|
arc: JLSR0 H02W0501
|
|
arc: JLSR1 V00T0100
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C87:CIB_DSP
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 H01E0101
|
|
|
|
.tile CIB_R25C89:CIB_LR
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R28C89:CIB_LR
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile CIB_R29C89:CIB_LR
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: JA3 H00L0100
|
|
arc: W1_H02W0501 JF5
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R30C89:CIB_LR
|
|
arc: W1_H02W0501 H01E0101
|
|
|
|
.tile CIB_R31C89:CIB_LR
|
|
arc: W1_H02W0501 JF5
|
|
|
|
.tile CIB_R34C27:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R34C33:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R34C35:CIB_EBR
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R34C36:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R34C37:CIB_EBR
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile CIB_R34C39:CIB_EBR
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile CIB_R34C42:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R34C46:CIB_EBR
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile CIB_R34C47:CIB_EBR
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R34C48:CIB_EBR
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile CIB_R34C49:CIB_EBR
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
|
|
.tile CIB_R34C51:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R34C54:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R34C57:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R34C60:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R34C63:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R34C66:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R34C69:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R34C72:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R34C74:CIB_EBR
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile CIB_R34C75:CIB_EBR
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R34C78:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile CIB_R34C81:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R34C84:CIB_EBR
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R34C87:CIB_EBR
|
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arc: N1_V02N0301 S3_V06N0003
|
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arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R46C27:CIB_DSP
|
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arc: N3_V06N0303 S3_V06N0203
|
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.tile CIB_R46C33:CIB_DSP
|
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arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C34:CIB_DSP
|
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arc: S1_V02S0601 E1_H01W0000
|
|
|
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.tile CIB_R46C35:CIB_DSP
|
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arc: E1_H01E0001 JQ4
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H01W0000 JQ7
|
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arc: N1_V01N0001 JQ5
|
|
arc: N1_V02N0601 JQ6
|
|
|
|
.tile CIB_R46C36:CIB_DSP
|
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arc: E1_H02E0101 N1_V02S0101
|
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arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 JQ3
|
|
arc: N1_V02N0401 JQ6
|
|
arc: N1_V02N0501 JQ7
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 JQ5
|
|
arc: S1_V02S0601 JQ4
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R46C37:CIB_DSP
|
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arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H01W0000 JQ1
|
|
arc: H01W0100 JQ3
|
|
arc: JB6 V00B0000
|
|
arc: JB7 V02S0701
|
|
arc: JD6 V02S0601
|
|
arc: JD7 S1_V02N0601
|
|
arc: N1_V01N0001 JQ2
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0001 JQ0
|
|
arc: V00B0000 V02N0001
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R46C38:CIB_DSP
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: JB0 V02N0301
|
|
arc: JB1 H02E0301
|
|
arc: JB2 H00R0100
|
|
arc: JB3 H02E0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 V00B0000
|
|
arc: JB7 W1_H02E0101
|
|
arc: JD0 V02S0001
|
|
arc: JD1 V02N0201
|
|
arc: JD2 H02E0001
|
|
arc: JD3 E1_H02W0001
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 V02S0601
|
|
arc: JD6 N1_V02S0401
|
|
arc: JD7 V00B0000
|
|
arc: JLSR1 V00B0100
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 H02E0701
|
|
|
|
.tile CIB_R46C39:CIB_DSP
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 V02N0501
|
|
arc: JB0 V02N0101
|
|
arc: JB1 N1_V02S0301
|
|
arc: JB2 V02N0101
|
|
arc: JB3 N1_V02S0301
|
|
arc: JB4 V02N0501
|
|
arc: JB5 N1_V02S0701
|
|
arc: JB6 V02N0501
|
|
arc: JB7 N1_V02S0701
|
|
arc: JCE3 H00R0000
|
|
arc: JD0 N1_V02S0001
|
|
arc: JD1 V01S0100
|
|
arc: JD2 N1_V02S0001
|
|
arc: JD3 V01S0100
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 H00R0100
|
|
arc: JD6 N1_V02S0401
|
|
arc: JD7 H00R0100
|
|
arc: JLSR0 V00B0000
|
|
arc: JLSR1 V00B0000
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R46C40:CIB_DSP
|
|
arc: W1_H02W0001 V02N0001
|
|
|
|
.tile CIB_R46C42:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R46C45:CIB_DSP
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile CIB_R46C46:CIB_DSP
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 JQ7
|
|
arc: H01W0000 JQ5
|
|
arc: JB4 H02W0101
|
|
arc: JB5 V02S0701
|
|
arc: JB6 V02N0501
|
|
arc: JB7 H02W0301
|
|
arc: JCE2 V02S0601
|
|
arc: JCE3 V02S0601
|
|
arc: JD4 V02S0401
|
|
arc: JD5 V00B0000
|
|
arc: JD6 N1_V02S0401
|
|
arc: JD7 V02N0401
|
|
arc: N1_V01N0001 JQ6
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0601 JF6
|
|
arc: N1_V02N0701 JF7
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 JQ4
|
|
arc: V00B0000 V02N0201
|
|
|
|
.tile CIB_R46C47:CIB_DSP
|
|
arc: E1_H01E0001 JF1
|
|
arc: E1_H01E0101 JF6
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 JF0
|
|
arc: H01W0100 JF7
|
|
arc: JB0 V02S0301
|
|
arc: JB1 V00T0000
|
|
arc: JB2 H00R0100
|
|
arc: JB3 H02E0101
|
|
arc: JB4 V00B0100
|
|
arc: JB5 H02E0101
|
|
arc: JB6 V00B0100
|
|
arc: JB7 H02E0101
|
|
arc: JD0 H02E0001
|
|
arc: JD1 H02E0201
|
|
arc: JD2 N1_V02S0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 H00R0100
|
|
arc: JD6 N1_V02S0601
|
|
arc: JD7 H00R0100
|
|
arc: N1_V01N0001 JF3
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 JQ3
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 JQ7
|
|
arc: N1_V02N0601 JQ6
|
|
arc: N1_V02N0701 JQ5
|
|
arc: S1_V02S0001 JF2
|
|
arc: S1_V02S0401 JF4
|
|
arc: S1_V02S0601 JQ4
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R46C48:CIB_DSP
|
|
arc: E1_H01E0101 JF0
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: JB0 V00T0000
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H00R0000
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 H02W0101
|
|
arc: JD0 V02S0001
|
|
arc: JD1 H00R0000
|
|
arc: JD2 V02S0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 V02S0601
|
|
arc: JD5 N1_V02S0601
|
|
arc: JD6 N1_V02S0401
|
|
arc: JD7 S1_V02N0401
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V01N0001 JF1
|
|
arc: N1_V01N0101 JF3
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0101 JQ3
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0001 JQ0
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0201 JF2
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R46C49:CIB_DSP
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: JB0 V02N0101
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 V02N0301
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 H02W0101
|
|
arc: JB5 N1_V02S0701
|
|
arc: JB6 H02W0101
|
|
arc: JB7 V00T0000
|
|
arc: JD0 N1_V01S0000
|
|
arc: JD1 V02S0001
|
|
arc: JD2 N1_V02S0201
|
|
arc: JD3 H02E0201
|
|
arc: JD4 H02E0001
|
|
arc: JD5 V00B0000
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 H02W0201
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R46C50:CIB_DSP
|
|
arc: H00R0000 V02S0601
|
|
arc: JB0 V02S0301
|
|
arc: JB1 N1_V02S0101
|
|
arc: JB2 V02S0101
|
|
arc: JB3 N1_V02S0101
|
|
arc: JB4 H00R0000
|
|
arc: JB5 N1_V02S0701
|
|
arc: JB6 V00B0100
|
|
arc: JB7 N1_V02S0701
|
|
arc: JCE3 H02E0101
|
|
arc: JD0 N1_V02S0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 N1_V02S0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 V02S0601
|
|
arc: JD6 N1_V02S0401
|
|
arc: JD7 V02S0601
|
|
arc: JLSR0 W1_H02E0301
|
|
arc: JLSR1 W1_H02E0301
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R46C51:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C54:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R46C57:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C60:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C63:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R46C66:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R46C69:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R46C71:CIB_DSP
|
|
arc: E1_H02E0201 V01N0001
|
|
|
|
.tile CIB_R46C72:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile CIB_R46C73:CIB_DSP
|
|
arc: E1_H01E0001 JQ5
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0701 JQ7
|
|
arc: H00R0100 V02S0701
|
|
arc: H01W0000 JQ6
|
|
arc: JB4 E1_H02W0301
|
|
arc: JB5 N1_V02S0701
|
|
arc: JB6 V02N0701
|
|
arc: JB7 V00T0000
|
|
arc: JCE2 H00R0100
|
|
arc: JCE3 H00R0100
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 V02S0401
|
|
arc: JD6 H02W0001
|
|
arc: JD7 W1_H02E0201
|
|
arc: N1_V01N0001 JQ4
|
|
arc: N1_V02N0401 JF6
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 JF7
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00T0000 V02S0601
|
|
arc: V01S0000 JF5
|
|
|
|
.tile CIB_R46C74:CIB_DSP
|
|
arc: E1_H01E0001 JF1
|
|
arc: E1_H01E0101 JF2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H01W0000 JF7
|
|
arc: H01W0100 JF3
|
|
arc: JB0 V02N0101
|
|
arc: JB1 N1_V02S0301
|
|
arc: JB2 H02E0101
|
|
arc: JB3 H02E0301
|
|
arc: JB4 V02S0501
|
|
arc: JB5 H02E0301
|
|
arc: JB6 V02S0501
|
|
arc: JB7 H02E0301
|
|
arc: JD0 N1_V02S0201
|
|
arc: JD1 S1_V02N0201
|
|
arc: JD2 V02S0201
|
|
arc: JD3 V02N0201
|
|
arc: JD4 H02E0001
|
|
arc: JD5 H02E0201
|
|
arc: JD6 H02E0001
|
|
arc: JD7 H02E0201
|
|
arc: N1_V01N0001 JF4
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JQ5
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 JQ7
|
|
arc: S1_V02S0001 JF0
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0201 JQ0
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 JQ6
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0401 JF6
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R46C75:CIB_DSP
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0000 JQ1
|
|
arc: H01W0100 JQ3
|
|
arc: JB0 V00T0000
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 H00R0100
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 V02S0501
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 V00B0100
|
|
arc: JB7 N1_V01S0000
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 W1_H02E0201
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 W1_H02E0201
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 W1_H02E0201
|
|
arc: JD6 N1_V02S0601
|
|
arc: JD7 V02N0401
|
|
arc: JLSR0 V00B0000
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V01N0001 JF0
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0101 JF3
|
|
arc: N1_V02N0201 JF2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0201 JQ2
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 JF1
|
|
arc: W1_H02W0301 V02N0301
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R46C76:CIB_DSP
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: JB0 V02N0101
|
|
arc: JB1 H00R0100
|
|
arc: JB2 H02W0101
|
|
arc: JB3 N1_V02S0301
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 W1_H02E0301
|
|
arc: JD0 H02W0001
|
|
arc: JD1 V02S0001
|
|
arc: JD2 N1_V02S0201
|
|
arc: JD3 H02E0201
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 V00B0000
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 W1_H02E0001
|
|
arc: JLSR1 H02W0501
|
|
arc: V00B0000 H02E0601
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R46C77:CIB_DSP
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: JB0 S1_V02N0301
|
|
arc: JB1 N1_V02S0301
|
|
arc: JB2 S1_V02N0301
|
|
arc: JB3 N1_V02S0301
|
|
arc: JB4 S1_V02N0501
|
|
arc: JB5 V02S0701
|
|
arc: JB6 S1_V02N0501
|
|
arc: JB7 V02S0701
|
|
arc: JCE3 H00R0100
|
|
arc: JD0 S1_V02N0201
|
|
arc: JD1 S1_V02N0001
|
|
arc: JD2 S1_V02N0201
|
|
arc: JD3 S1_V02N0001
|
|
arc: JD4 V02S0401
|
|
arc: JD5 S1_V02N0601
|
|
arc: JD6 V02S0401
|
|
arc: JD7 S1_V02N0601
|
|
arc: JLSR0 H02W0301
|
|
arc: JLSR1 H02W0301
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R46C78:CIB_DSP
|
|
arc: E1_H01E0001 JF1
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02W0501
|
|
arc: JB0 V00B0000
|
|
arc: JB1 H02E0101
|
|
arc: JB2 V02N0101
|
|
arc: JB3 N1_V02S0301
|
|
arc: JB4 V02N0501
|
|
arc: JB5 N1_V02S0501
|
|
arc: JB6 V02S0501
|
|
arc: JB7 N1_V02S0701
|
|
arc: JCE0 H00R0100
|
|
arc: JD0 H00R0000
|
|
arc: JD1 H02W0001
|
|
arc: JD2 N1_V02S0201
|
|
arc: JD3 H02W0201
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 H02E0001
|
|
arc: JD6 N1_V02S0401
|
|
arc: JD7 S1_V02N0601
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V01N0001 JF5
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 JF2
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 JF6
|
|
arc: N1_V02N0701 JF7
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 JF0
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 JF3
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V02S0301
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R46C79:CIB_DSP
|
|
arc: E1_H01E0001 JF7
|
|
arc: H00L0000 V02N0201
|
|
arc: H01W0000 JF3
|
|
arc: H01W0100 JF1
|
|
arc: JB0 V00B0000
|
|
arc: JB1 H02E0301
|
|
arc: JB2 H00L0000
|
|
arc: JB3 H02E0301
|
|
arc: JB4 H00L0000
|
|
arc: JB5 H02E0301
|
|
arc: JB6 V00B0000
|
|
arc: JB7 H02E0301
|
|
arc: JD0 H02E0201
|
|
arc: JD1 V02N0201
|
|
arc: JD2 H02E0201
|
|
arc: JD3 V02N0201
|
|
arc: JD4 H02E0201
|
|
arc: JD5 V00B0000
|
|
arc: JD6 H02E0201
|
|
arc: JD7 V00B0000
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 JF2
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0201 JF0
|
|
arc: S1_V02S0601 JF6
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: W1_H02W0501 V06S0303
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R46C80:CIB_DSP
|
|
arc: JB0 V00T0000
|
|
arc: JB1 W1_H02E0301
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V02S0201
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: V00T0000 V02S0401
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R46C81:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R46C84:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R46C87:CIB_DSP
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R58C27:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C33:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C36:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C42:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R58C45:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R58C48:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R58C51:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C54:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C57:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C60:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C63:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C66:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C69:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C72:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R58C75:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R58C78:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C81:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C84:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile CIB_R58C87:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R5C1:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R5C89:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C15:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C18:CIB
|
|
arc: JA0 N1_V02S0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C21:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C27:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C33:CIB
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C36:CIB
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile CIB_R70C39:CIB
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile CIB_R70C3:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C42:VCIB_DCU0
|
|
arc: N3_V06N0303 H06E0303
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C43:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C45:VCIB_DCUC
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
arc: N3_V06N0003 H06E0003
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C54:CIB
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile CIB_R70C57:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C60:CIB
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile CIB_R70C63:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C66:CIB
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
arc: N3_V06N0103 H06E0103
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
arc: N3_V06N0103 H06E0103
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C81:CIB
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C84:CIB
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile MIB_R0C31:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C39:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C71:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C75:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C78:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C79:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C50:EBR_SPINE_UR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C77:EBR_SPINE_UR1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R11C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R11C90:PICR0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R12C0:PICL1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R12C90:PICR1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C90:PICR1_DQS0
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C90:PICR0_DQS2
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R18C90:PICR1_DQS3
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C31:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C39:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C71:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C75:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C78:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C79:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R22C31:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R22C42:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R22C51:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R22C60:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R22C69:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R22C78:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R23C90:PICR0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R25C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R46C78:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R58C30:EBR_SPINE_LL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C50:EBR_SPINE_LR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R58C77:EBR_SPINE_LR1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R71C15:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile R11C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R11C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R11C25:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R11C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R11C37:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R11C40:PLC2
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R11C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R11C46:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R11C49:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R11C52:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R11C55:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: S3_V06S0203 H06W0203
|
|
|
|
.tile R11C58:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R11C61:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R11C64:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R11C67:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R11C70:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R11C71:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
|
|
.tile R11C72:PLC2
|
|
arc: B0 H02E0101
|
|
arc: C0 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C73:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile R11C75:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
|
|
.tile R11C76:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: A0 H02E0501
|
|
arc: C0 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C77:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: A0 H00L0000
|
|
arc: A1 V01N0101
|
|
arc: B0 H00R0100
|
|
arc: B1 V00T0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: CE1 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V00B0100
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0100 Q7
|
|
arc: LSR1 V00T0100
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0201 F0
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 1001011001101001
|
|
word: SLICEA.K1.INIT 0110100110010110
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C78:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0100 V02N0301
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: A1 H00L0100
|
|
arc: A2 F5
|
|
arc: A3 F5
|
|
arc: A4 V02N0301
|
|
arc: A5 V00B0000
|
|
arc: A7 F5
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 H02W0101
|
|
arc: B3 H02W0301
|
|
arc: B4 H02W0101
|
|
arc: B5 H00L0000
|
|
arc: B7 H02W0101
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V02N0001
|
|
arc: C7 V02N0201
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 F0
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H02E0001 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00B0000 F4
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0101 F1
|
|
word: SLICEC.K1.INIT 0101010101000000
|
|
word: SLICEA.K0.INIT 0011111100111111
|
|
word: SLICEC.K0.INIT 0000000000001000
|
|
word: SLICED.K1.INIT 0000001010000000
|
|
word: SLICEA.K1.INIT 0000000010000000
|
|
word: SLICEB.K0.INIT 0000000000001010
|
|
word: SLICEB.K1.INIT 0000100000001010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C79:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A2 V01N0101
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 H01W0100
|
|
arc: B2 H01W0100
|
|
arc: B3 V02N0301
|
|
arc: C7 E1_H01E0101
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V02N0001
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V00T0100 F3
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEB.K1.INIT 0000000000110011
|
|
word: SLICED.K1.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 0011001100000000
|
|
word: SLICEB.K0.INIT 1110111001000100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R11C80:PLC2
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: A2 H00L0100
|
|
arc: A7 Q7
|
|
arc: B2 V02N0301
|
|
arc: B7 V00B0000
|
|
arc: C2 H00L0000
|
|
arc: C7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H00R0000
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q4
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0100
|
|
arc: M4 E1_H01E0101
|
|
arc: M5 H00R0000
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C81:PLC2
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
|
|
.tile R11C82:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
|
|
.tile R11C83:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
|
|
.tile R11C84:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 V02N0201
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02E0201
|
|
arc: E1_H02E0101 Q1
|
|
arc: F4 F4_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00B0000 F4
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C85:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: H00L0100 H02E0101
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: A2 V00T0000
|
|
arc: A4 V00T0000
|
|
arc: B2 V01N0001
|
|
arc: C0 F4
|
|
arc: C4 V02N0001
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D2 V02N0001
|
|
arc: D4 V01N0001
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 H02E0501
|
|
arc: M1 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q2
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEB.K0.INIT 1100110010101010
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0000010100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R11C86:PLC2
|
|
arc: H00L0100 H02E0101
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: V00T0000 H02E0201
|
|
arc: A0 V02N0501
|
|
arc: A5 V00B0000
|
|
arc: A6 F5
|
|
arc: B0 H00R0100
|
|
arc: B5 H00L0000
|
|
arc: C0 H02E0401
|
|
arc: C5 V02N0201
|
|
arc: C6 E1_H01E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D5 H02E0201
|
|
arc: D6 V02N0401
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q4
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M2 N1_V01N0001
|
|
arc: M3 H01W0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 F6
|
|
arc: S3_V06S0103 Q1
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 Q7
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 1010000000000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R11C87:PLC2
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: B2 V01N0001
|
|
arc: B4 V02N0501
|
|
arc: C2 W1_H02E0601
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V01N0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02N0001
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V00B0000 F4
|
|
arc: V00T0000 Q2
|
|
word: SLICEC.K0.INIT 1001011001101001
|
|
word: SLICEC.K1.INIT 1010010101011010
|
|
word: SLICEB.K0.INIT 0011110011000011
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C30:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R12C51:PLC2
|
|
arc: S3_V06S0303 H06W0303
|
|
|
|
.tile R12C54:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R12C55:PLC2
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile R12C60:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R12C61:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R12C66:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R12C67:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R12C72:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: B1 S1_V02N0301
|
|
arc: C1 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: F1 F1_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R12C73:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R12C75:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
|
|
.tile R12C76:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0701
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0101 Q1
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C77:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0201
|
|
arc: A0 H00L0000
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D2 V02S0001
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: S1_V02S0201 F2
|
|
word: SLICEA.K0.INIT 1010101010100101
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C78:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: A4 E1_H01W0000
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 E1_H01W0000
|
|
arc: B4 H02W0101
|
|
arc: B6 H02W0101
|
|
arc: B7 V00T0000
|
|
arc: C4 S1_V02N0201
|
|
arc: C7 W1_H02E0401
|
|
arc: D4 H02W0201
|
|
arc: D6 H02W0201
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F6
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0401 F4
|
|
arc: S3_V06S0203 F4
|
|
arc: V01S0000 F7
|
|
word: SLICED.K1.INIT 0000001000100010
|
|
word: SLICED.K0.INIT 0000000000100010
|
|
word: SLICEC.K0.INIT 1111000111110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R12C79:PLC2
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A0 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: B0 V00T0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 N1_V01S0100
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 V01S0100
|
|
arc: D3 V01S0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 F0
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q3
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 0000001000000000
|
|
word: SLICEB.K0.INIT 0000010101010101
|
|
word: SLICEB.K1.INIT 1111010100001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C80:PLC2
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C81:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: W1_H02W0001 V06N0003
|
|
|
|
.tile R12C83:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
|
|
.tile R12C84:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0100 V02N0301
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: LSR0 V00B0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0501 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C85:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: V00B0000 V02S0201
|
|
arc: A2 V00B0000
|
|
arc: B0 V00T0000
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 H02E0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 Q2
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0001 Q0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 0000001100110011
|
|
word: SLICEB.K0.INIT 1010111101010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C86:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: A0 H01E0001
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: B0 V00T0000
|
|
arc: B2 H00R0000
|
|
arc: B3 H00R0000
|
|
arc: B5 H01E0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 H01E0001
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 V00B0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D2 F0
|
|
arc: D3 F0
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0001
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F2
|
|
arc: LSR1 H02W0501
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 V01S0100
|
|
arc: M2 V00T0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0401 F4
|
|
arc: S1_V02S0601 F6
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEB.K0.INIT 0000000000110000
|
|
word: SLICEB.K1.INIT 0000000010110000
|
|
word: SLICED.K0.INIT 1100000011000000
|
|
word: SLICEA.K0.INIT 1000101010101010
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000101
|
|
word: SLICEC.K1.INIT 0100000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R12C87:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: A1 V02N0701
|
|
arc: A3 V02N0501
|
|
arc: A7 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B3 V01N0001
|
|
arc: B7 V02N0701
|
|
arc: C1 V02N0401
|
|
arc: C3 V02N0601
|
|
arc: C5 V01N0101
|
|
arc: C7 V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D5 V02N0601
|
|
arc: D7 V02N0401
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0501 Q7
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0601 F6
|
|
arc: V00B0100 F5
|
|
arc: V00T0100 F1
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 0000000000001111
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C71:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
|
|
.tile R13C72:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R13C75:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C76:PLC2
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: A2 V00B0000
|
|
arc: A3 V01N0101
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 H00R0000
|
|
arc: A7 H00L0000
|
|
arc: B0 H02E0301
|
|
arc: B2 V02S0301
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V00B0100
|
|
arc: B7 S1_V02N0701
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C77:PLC2
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: A0 H00L0100
|
|
arc: A1 V01N0101
|
|
arc: A2 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0100
|
|
arc: A6 H00R0000
|
|
arc: A7 V00T0100
|
|
arc: B0 V00B0000
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 H00L0000
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 V02N0701
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0100 Q7
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C78:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: A0 H02E0501
|
|
arc: A1 H02E0501
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: A4 H02E0501
|
|
arc: A5 H02E0701
|
|
arc: A6 H02E0701
|
|
arc: A7 H02E0701
|
|
arc: B0 V00B0000
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 H00L0000
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 H00R0000
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 S1_V02N0701
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R13C79:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 H02W0501
|
|
arc: A3 V02N0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0100
|
|
arc: A6 H00R0000
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 H02W0101
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: B4 H02W0101
|
|
arc: B5 H02W0101
|
|
arc: B6 H02W0101
|
|
arc: B7 S1_V02N0701
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q6
|
|
arc: V01S0100 Q7
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C80:PLC2
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 H00L0000
|
|
arc: A1 V02N0501
|
|
arc: A4 F5
|
|
arc: A5 H02E0501
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B4 V00B0100
|
|
arc: B5 H00R0000
|
|
arc: B6 H01E0101
|
|
arc: B7 H01E0101
|
|
arc: C4 H02W0601
|
|
arc: C5 H01E0001
|
|
arc: C6 W1_H02E0401
|
|
arc: C7 W1_H02E0401
|
|
arc: CE0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02E0201
|
|
arc: D5 H01W0000
|
|
arc: D6 H00L0100
|
|
arc: D7 H00R0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0601 F6
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R13C81:PLC2
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: A0 W1_H02E0501
|
|
arc: A4 V00T0100
|
|
arc: B0 W1_H02E0301
|
|
arc: B4 W1_H02E0301
|
|
arc: C0 W1_H02E0401
|
|
arc: C4 W1_H02E0401
|
|
arc: D0 W1_H02E0001
|
|
arc: D4 W1_H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0601 F4
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R13C83:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
|
|
.tile R13C84:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: A2 V00B0000
|
|
arc: A3 V02N0701
|
|
arc: A4 V02N0301
|
|
arc: A5 H02W0501
|
|
arc: A6 H00R0000
|
|
arc: A7 V02N0101
|
|
arc: B0 V02S0301
|
|
arc: B2 H00R0100
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 V02N0501
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 S1_V02N0701
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C85:PLC2
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 V02N0701
|
|
arc: A1 V01N0101
|
|
arc: A2 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0100
|
|
arc: A6 H00R0000
|
|
arc: A7 V00T0100
|
|
arc: B0 V00B0000
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 H00L0000
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 H02W0301
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 H02W0301
|
|
arc: B7 S1_V02N0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0601 Q6
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C86:PLC2
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0301
|
|
arc: A6 H02E0701
|
|
arc: A7 V02N0301
|
|
arc: B0 V00B0000
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B4 V02N0501
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02N0701
|
|
arc: B7 H02W0101
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q4
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C87:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V02N0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0100
|
|
arc: A6 H00R0000
|
|
arc: A7 H02W0501
|
|
arc: B0 H02W0301
|
|
arc: B1 H02W0301
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: B4 H02W0301
|
|
arc: B5 H02W0301
|
|
arc: B6 H02W0301
|
|
arc: B7 H02W0301
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0000 Q1
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R13C88:PLC2
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 H02E0701
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 V02N0701
|
|
arc: A1 H00L0100
|
|
arc: A4 H02E0701
|
|
arc: A7 H00L0000
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0301
|
|
arc: B4 H00L0000
|
|
arc: C4 H02E0601
|
|
arc: C7 H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02E0201
|
|
arc: D7 H00R0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 F4
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0701 F7
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1010000000000000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R14C72:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
|
|
.tile R14C73:PLC2
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 H02E0301
|
|
|
|
.tile R14C74:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
|
|
.tile R14C75:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R14C76:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: B5 N1_V01S0000
|
|
arc: C5 E1_H01E0101
|
|
arc: CE1 H00R0000
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 H00R0100
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0701 F5
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: LSR0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: V01S0000 Q6
|
|
word: SLICEC.K1.INIT 0000000000001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R14C77:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02S0701
|
|
arc: A2 V02S0501
|
|
arc: A5 V02S0101
|
|
arc: A6 N1_V02S0101
|
|
arc: B2 V02S0301
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 V02S0501
|
|
arc: C2 V02S0601
|
|
arc: C5 V02S0201
|
|
arc: C6 V02S0201
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V00T0100
|
|
arc: D5 V02S0401
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0103 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0301 Q1
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R14C78:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: A0 V02S0701
|
|
arc: A1 H00R0000
|
|
arc: A3 V02S0501
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 V00T0000
|
|
arc: B1 V02S0101
|
|
arc: B3 H02E0301
|
|
arc: B7 H02E0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 H00L0100
|
|
arc: C7 E1_H01E0101
|
|
arc: D0 V02S0201
|
|
arc: D1 V02S0201
|
|
arc: D3 V02S0001
|
|
arc: D7 F0
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M6 H02E0401
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0001000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R14C79:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 V01N0101
|
|
|
|
.tile R14C80:PLC2
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: A1 H02E0701
|
|
arc: A5 N1_V01S0100
|
|
arc: B0 V02S0101
|
|
arc: B1 V02S0101
|
|
arc: B5 H02E0301
|
|
arc: C0 H02E0601
|
|
arc: C1 F4
|
|
arc: C3 F4
|
|
arc: C5 H02E0401
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0201
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 V02S0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 H00R0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 H02W0401
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00T0100 F1
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 1111001100110011
|
|
word: SLICEA.K1.INIT 0000101100000011
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R14C81:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
|
|
.tile R14C82:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
|
|
.tile R14C83:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
|
|
.tile R14C84:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: CE1 H00R0000
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0501 Q5
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0100
|
|
arc: M6 H02W0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C85:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: A3 S1_V02N0501
|
|
arc: B3 V02S0301
|
|
arc: C3 H00L0000
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 N1_V02S0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0003 Q0
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0301 F3
|
|
arc: V01S0100 F3
|
|
word: SLICEB.K1.INIT 1010101110101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R14C86:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: A0 H00L0000
|
|
arc: A1 H02E0701
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 V02S0301
|
|
arc: A6 V02S0301
|
|
arc: A7 W1_H02E0501
|
|
arc: B1 H02E0101
|
|
arc: B2 H01W0100
|
|
arc: B3 H00R0000
|
|
arc: B4 V02N0501
|
|
arc: B5 H02E0101
|
|
arc: B6 V00B0100
|
|
arc: B7 V02S0701
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 V02S0401
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C4 V02S0001
|
|
arc: C5 H02E0401
|
|
arc: C6 H02E0401
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00L0100
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 V02S0201
|
|
arc: D2 H02E0001
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 F2
|
|
arc: D5 H00R0100
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 F5
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0601 F4
|
|
arc: V00B0000 Q4
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 0000000100000001
|
|
word: SLICED.K1.INIT 0000000001000000
|
|
word: SLICEA.K0.INIT 1111111111110101
|
|
word: SLICEB.K0.INIT 0000001000000000
|
|
word: SLICEB.K1.INIT 0000100001000000
|
|
word: SLICEC.K0.INIT 0000000011101010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R14C87:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A1 V02S0701
|
|
arc: A2 H02E0501
|
|
arc: A3 H01E0001
|
|
arc: A4 H02E0501
|
|
arc: A5 V02S0101
|
|
arc: A7 V02S0101
|
|
arc: B1 V00T0000
|
|
arc: B2 H02E0301
|
|
arc: B3 H00R0100
|
|
arc: B4 H02E0301
|
|
arc: B5 H00R0000
|
|
arc: B7 H02E0101
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0601
|
|
arc: C3 F4
|
|
arc: C4 H02E0601
|
|
arc: C5 W1_H02E0601
|
|
arc: C7 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H01E0101
|
|
arc: D2 H02E0201
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0201
|
|
arc: D5 F2
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: S1_V02S0101 Q1
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 0000000100000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R14C88:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 V02S0701
|
|
arc: A1 V02S0701
|
|
arc: B0 V02S0101
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: F0 F5A_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: M0 H01E0001
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: V00T0000 F0
|
|
word: SLICEA.K0.INIT 1011001100110011
|
|
word: SLICEA.K1.INIT 1010000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C42:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
|
.tile R15C43:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
|
|
.tile R15C47:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R15C48:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R15C49:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R15C53:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R15C54:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R15C55:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R15C56:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R15C59:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R15C60:PLC2
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R15C61:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R15C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R15C65:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R15C66:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R15C67:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R15C68:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R15C70:PLC2
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
|
|
.tile R15C71:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R15C72:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
|
|
.tile R15C73:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02N0101
|
|
arc: A0 E1_H02W0501
|
|
arc: B0 V02S0301
|
|
arc: C0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00T0000 Q2
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C74:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R15C75:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
|
|
.tile R15C76:PLC2
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: A0 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A3 H00L0100
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 N1_V01N0101
|
|
arc: A7 V02N0101
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 V02N0301
|
|
arc: B4 H02E0301
|
|
arc: B5 V02N0501
|
|
arc: B6 V02N0701
|
|
arc: B7 V01S0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q7
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q7
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C77:PLC2
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02W0701
|
|
arc: A0 V02N0701
|
|
arc: A1 H00L0100
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 V00B0000
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 Q5
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 V00T0000
|
|
arc: B1 V02N0101
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 Q3
|
|
arc: B4 V01S0000
|
|
arc: B5 V02N0501
|
|
arc: B6 H02E0301
|
|
arc: B7 V02S0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C78:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00R0000 V02N0401
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 H00L0100
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 V00B0000
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 Q5
|
|
arc: A6 H02E0501
|
|
arc: A7 H00R0000
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 H02W0101
|
|
arc: B3 Q3
|
|
arc: B4 V02N0701
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02N0501
|
|
arc: B7 V00B0100
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q7
|
|
arc: V00B0100 Q7
|
|
arc: V01S0100 Q0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C79:PLC2
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 V01N0101
|
|
arc: A1 V02N0701
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 H00L0100
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00L0000
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 V02N0301
|
|
arc: B3 V01N0001
|
|
arc: B4 V01S0000
|
|
arc: B5 H00R0000
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 H02E0101
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C80:PLC2
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: A0 H00L0000
|
|
arc: A1 V01N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 Q1
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C81:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: V00B0000 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N3_V06N0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C83:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: N1_V02N0601 H06W0303
|
|
|
|
.tile R15C84:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 H00L0100
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 V02N0301
|
|
arc: A7 H02E0701
|
|
arc: B0 H02E0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 H02E0101
|
|
arc: B4 H00R0000
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V00B0100
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 Q7
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C85:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V02N0701
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 V00T0000
|
|
arc: A5 Q5
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 Q7
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 H02E0301
|
|
arc: B2 H00R0000
|
|
arc: B3 V02N0301
|
|
arc: B4 V01S0000
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V00B0000
|
|
arc: B7 S1_V02N0501
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q5
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C86:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 V00B0000
|
|
arc: A3 V02N0501
|
|
arc: A4 V02N0301
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 H00L0000
|
|
arc: B0 H01W0100
|
|
arc: B1 H02E0301
|
|
arc: B2 V02S0101
|
|
arc: B3 Q3
|
|
arc: B4 V02N0701
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 V00B0100
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: V00B0100 Q7
|
|
arc: V01S0100 Q4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C87:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00L0000 H02E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 V06N0303
|
|
arc: A0 V01N0101
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 Q5
|
|
arc: A6 H00L0000
|
|
arc: A7 Q7
|
|
arc: B0 H01W0100
|
|
arc: B1 V01N0001
|
|
arc: B2 V02N0101
|
|
arc: B3 V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0501
|
|
arc: B6 V02N0701
|
|
arc: B7 V00T0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R15C88:PLC2
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: A0 H00L0000
|
|
arc: A1 V01N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 Q1
|
|
arc: CE0 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C49:PLC2
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R16C52:PLC2
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
|
|
.tile R16C53:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
|
.tile R16C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R16C58:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R16C59:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R16C61:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R16C64:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R16C65:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R16C67:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R16C69:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
|
|
.tile R16C70:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 V02N0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: A0 H02W0701
|
|
arc: A2 H02E0701
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 H02E0501
|
|
arc: A5 V00T0000
|
|
arc: A6 H00L0000
|
|
arc: A7 V02N0101
|
|
arc: B2 V02N0301
|
|
arc: B3 H02E0101
|
|
arc: B4 V02N0501
|
|
arc: B5 H00R0000
|
|
arc: B6 V02N0701
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: V01S0000 Q2
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C71:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A0 H00R0000
|
|
arc: A1 H02W0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V00B0000
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 H02E0701
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 H02W0701
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 V02N0501
|
|
arc: B5 H00L0000
|
|
arc: B6 V02N0701
|
|
arc: B7 S1_V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C72:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V00B0000
|
|
arc: A4 V00B0000
|
|
arc: A5 V00B0000
|
|
arc: B0 H02E0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: B3 H00R0000
|
|
arc: B4 H00R0000
|
|
arc: B5 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q2
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0100 Q0
|
|
word: SLICED.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C73:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile R16C74:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
|
|
.tile R16C75:PLC2
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
|
|
.tile R16C76:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
|
|
.tile R16C77:PLC2
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R16C78:PLC2
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: V00T0000 H02W0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00T0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: V01S0100 Q3
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C79:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M3 H02W0201
|
|
arc: M4 E1_H01E0101
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C80:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00B0000
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C81:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R16C82:PLC2
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
|
|
.tile R16C83:PLC2
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
|
|
.tile R16C84:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
|
|
.tile R16C85:PLC2
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
|
|
.tile R16C86:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: V00B0000 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0100 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C87:PLC2
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: V00B0000 H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 H02E0601
|
|
arc: M1 H02E0001
|
|
arc: M2 H02E0601
|
|
arc: M4 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0100 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R16C88:PLC2
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M5 W1_H02E0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C40:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R17C42:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
|
|
.tile R17C43:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V02N0501
|
|
|
|
.tile R17C44:PLC2
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
|
|
.tile R17C45:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R17C46:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R17C47:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
|
|
.tile R17C48:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
|
|
.tile R17C49:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R17C50:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
|
|
.tile R17C51:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R17C53:PLC2
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
|
.tile R17C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R17C56:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R17C57:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R17C58:PLC2
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
|
|
.tile R17C59:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
|
|
.tile R17C60:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
|
.tile R17C61:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R17C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R17C63:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R17C64:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R17C65:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R17C66:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R17C67:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R17C68:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R17C69:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 H02W0301
|
|
arc: A0 V02S0701
|
|
arc: A2 V01N0101
|
|
arc: A3 V02N0701
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 V00T0100
|
|
arc: A7 V02N0301
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 V02N0101
|
|
arc: B4 H00R0000
|
|
arc: B5 H00L0000
|
|
arc: B6 V00T0000
|
|
arc: B7 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C70:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: A0 V01N0101
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0101
|
|
arc: A6 H02E0501
|
|
arc: A7 H02E0701
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 V01N0001
|
|
arc: B2 H00L0000
|
|
arc: B3 V02N0301
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 H02W0301
|
|
arc: B6 V00B0000
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q3
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C71:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 V01N0101
|
|
arc: A1 H02E0501
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 V01N0001
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C72:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R17C73:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R17C74:PLC2
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0701 H02E0701
|
|
|
|
.tile R17C75:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
|
|
.tile R17C76:PLC2
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
|
|
.tile R17C77:PLC2
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
|
|
.tile R17C78:PLC2
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
|
|
.tile R17C79:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R17C81:PLC2
|
|
arc: N1_V02N0401 V01N0001
|
|
|
|
.tile R17C82:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R17C83:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02E0301
|
|
arc: A2 V00B0000
|
|
arc: A3 V01N0101
|
|
arc: A4 H02E0701
|
|
arc: A5 H02E0501
|
|
arc: A6 V00T0100
|
|
arc: A7 H00L0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 S1_V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0701 Q7
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C84:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0401
|
|
arc: A0 V01N0101
|
|
arc: A1 S1_V02N0501
|
|
arc: A2 V00B0000
|
|
arc: A3 V00T0000
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 H02W0701
|
|
arc: A6 H00L0000
|
|
arc: A7 H02E0501
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 H02E0101
|
|
arc: B3 V01N0001
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0501
|
|
arc: B6 H02E0301
|
|
arc: B7 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0301 Q1
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C85:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 V01N0101
|
|
arc: A1 S1_V02N0501
|
|
arc: A2 V00B0000
|
|
arc: A3 H00L0100
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 S1_V02N0101
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 H02E0301
|
|
arc: B3 V01N0001
|
|
arc: B4 H02W0301
|
|
arc: B5 H02W0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0301 Q1
|
|
word: SLICED.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R17C86:PLC2
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 V02N0301
|
|
|
|
.tile R17C87:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R18C27:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
|
|
.tile R18C29:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R18C30:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R18C35:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R18C36:PLC2
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
|
|
.tile R18C41:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R18C42:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
|
|
.tile R18C43:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R18C44:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R18C45:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
|
|
.tile R18C46:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile R18C47:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R18C48:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R18C49:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
|
|
.tile R18C50:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
|
|
.tile R18C51:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R18C52:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R18C53:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R18C54:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R18C55:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R18C56:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R18C57:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R18C58:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R18C59:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R18C60:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R18C61:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
|
|
.tile R18C62:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R18C63:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R18C64:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H02E0501
|
|
|
|
.tile R18C65:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R18C66:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R18C67:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
|
|
.tile R18C68:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
|
|
.tile R18C69:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: V00B0000 V02N0201
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V00B0000
|
|
arc: A4 H02E0501
|
|
arc: A5 V02N0301
|
|
arc: A6 V02S0101
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 H02E0301
|
|
arc: B2 V02S0301
|
|
arc: B3 H00L0000
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 V02N0701
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0000 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C70:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: A0 V02S0701
|
|
arc: A1 V02N0701
|
|
arc: A2 H02E0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 H02E0501
|
|
arc: A5 V02N0301
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 H02E0101
|
|
arc: B1 V02N0101
|
|
arc: B2 H00R0000
|
|
arc: B3 V02S0301
|
|
arc: B4 H00L0000
|
|
arc: B5 V00B0100
|
|
arc: B6 H02E0301
|
|
arc: B7 V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0000 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C71:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00R0000 H02E0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00B0000 H02E0401
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: B0 V02N0101
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0201 Q2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C72:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0001
|
|
arc: A2 V00T0000
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 V02S0101
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 V02S0301
|
|
arc: B0 V00B0000
|
|
arc: B2 H00R0000
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 H02W0301
|
|
arc: B5 W1_H02E0301
|
|
arc: B6 V02S0501
|
|
arc: B7 V02S0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C73:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: A0 V02S0701
|
|
arc: A1 H01E0001
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 H02W0701
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 H02E0701
|
|
arc: B0 H02E0101
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 H02W0101
|
|
arc: B3 H02E0301
|
|
arc: B4 H02W0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C74:PLC2
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 V02S0301
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H02E0701
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: B0 H02W0101
|
|
arc: B1 V00T0000
|
|
arc: B2 V02S0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C75:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: B0 V02N0101
|
|
arc: C0 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C76:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 V02S0001
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02N0701
|
|
arc: A0 H00L0000
|
|
arc: A2 V00B0000
|
|
arc: A3 V01N0101
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 H02E0501
|
|
arc: A7 V00T0100
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C77:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: A0 V01N0101
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V00T0100
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 H02E0701
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 V01N0001
|
|
arc: B3 H00R0000
|
|
arc: B4 H00L0000
|
|
arc: B5 H02E0301
|
|
arc: B6 V00B0000
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q7
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C78:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00L0000 V02N0201
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 H00L0000
|
|
arc: A1 V01N0101
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q3
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C79:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R18C80:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
|
|
.tile R18C81:PLC2
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M3 H01W0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V00T0100 Q3
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C82:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile R18C83:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0000
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 H02E0701
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 H02W0301
|
|
arc: B2 H00L0000
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 H02W0101
|
|
arc: B7 S1_V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
arc: V01S0000 Q7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C84:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: A0 H00L0000
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 V00B0000
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 V00T0000
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 H02E0701
|
|
arc: A7 H02W0701
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 H02W0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 S1_V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0601 Q4
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C85:PLC2
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V02N0301
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: V01S0100 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C86:PLC2
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R18C87:PLC2
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
|
|
.tile R19C27:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
|
|
.tile R19C29:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
|
|
.tile R19C32:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
|
|
.tile R19C33:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C34:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R19C35:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R19C36:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
|
|
.tile R19C37:PLC2
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R19C38:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R19C39:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
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arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C40:PLC2
|
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arc: E3_H06E0003 W3_H06E0303
|
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arc: E3_H06E0103 W3_H06E0003
|
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arc: E3_H06E0203 W3_H06E0103
|
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arc: E3_H06E0303 W3_H06E0203
|
|
|
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.tile R19C41:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
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arc: E3_H06E0203 W3_H06E0203
|
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arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C42:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: V00B0100 V02N0301
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
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.tile R19C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R19C44:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
|
|
.tile R19C45:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R19C46:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
|
|
.tile R19C47:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R19C48:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
|
|
.tile R19C49:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
|
|
.tile R19C50:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
|
|
.tile R19C51:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R19C52:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
|
|
.tile R19C53:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C54:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C55:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile R19C56:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
|
|
.tile R19C57:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R19C58:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R19C59:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R19C60:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C61:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C62:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R19C63:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0101 V01N0101
|
|
|
|
.tile R19C64:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
|
|
.tile R19C65:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R19C66:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0601 H01E0001
|
|
|
|
.tile R19C67:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C68:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
|
|
.tile R19C69:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
|
|
.tile R19C70:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: A2 V01N0101
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 V00B0000
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 H00R0000
|
|
arc: B0 V02S0301
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 E1_H02W0101
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0601 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C71:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A0 V01N0101
|
|
arc: A1 H00R0000
|
|
arc: A2 V00B0000
|
|
arc: A3 H00L0100
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 H02W0701
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 V02N0101
|
|
arc: B2 H00L0000
|
|
arc: B3 V01N0001
|
|
arc: B4 H02W0301
|
|
arc: B5 H02E0101
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
arc: V01S0000 Q7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C72:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0303 H01E0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: B0 V01N0001
|
|
arc: B1 V02N0101
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 E1_H02W0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0301 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C73:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 V02N0401
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 V00T0000
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 H02E0501
|
|
arc: B0 V02S0301
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V00B0100
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C74:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: A0 H00R0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V02N0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0100
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H00L0000
|
|
arc: B3 V02N0301
|
|
arc: B4 V00B0100
|
|
arc: B5 V02N0501
|
|
arc: B6 V02S0501
|
|
arc: B7 N1_V02S0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C75:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 H00R0000
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: B0 V00B0000
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 H00L0000
|
|
arc: B3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C76:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A2 H02W0701
|
|
arc: A3 V00T0000
|
|
arc: A4 V00T0100
|
|
arc: A5 N1_V02S0301
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 V00B0000
|
|
arc: B2 V02N0301
|
|
arc: B3 H02E0301
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 V02S0701
|
|
arc: B7 N1_V02S0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C77:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 V02S0501
|
|
arc: A1 H00R0000
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 V00B0000
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 W1_H02E0501
|
|
arc: A7 N1_V02S0101
|
|
arc: B0 V02N0301
|
|
arc: B1 V00T0000
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 V02S0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C78:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A0 H00L0000
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 H00L0100
|
|
arc: B0 H02E0301
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 N1_V02S0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C79:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R19C80:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0701 H01E0101
|
|
|
|
.tile R19C81:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: A0 V02S0701
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V00T0000
|
|
arc: A5 H02W0701
|
|
arc: A6 H02W0501
|
|
arc: A7 E1_H02W0701
|
|
arc: B2 V02N0301
|
|
arc: B3 H02W0301
|
|
arc: B4 H02E0101
|
|
arc: B5 H00R0000
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0301 Q3
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C82:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0000
|
|
arc: A2 V00B0000
|
|
arc: A3 V00T0000
|
|
arc: A4 H02E0501
|
|
arc: A5 V00T0100
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 V02N0101
|
|
arc: B1 V02S0101
|
|
arc: B2 H02W0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 H00R0000
|
|
arc: B6 V02N0501
|
|
arc: B7 V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C83:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 H00L0100
|
|
arc: A2 H00L0100
|
|
arc: B0 H02E0301
|
|
arc: B1 V00B0000
|
|
arc: B2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C84:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
|
|
.tile R19C85:PLC2
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R19C86:PLC2
|
|
arc: N1_V02N0301 H06E0003
|
|
|
|
.tile R20C25:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
|
|
.tile R20C26:PLC2
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: M1 H00L0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C27:PLC2
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C28:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R20C29:PLC2
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
|
|
.tile R20C30:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 V02N0701
|
|
|
|
.tile R20C31:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 H02W0301
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C32:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A2 H00L0100
|
|
arc: A3 H01E0001
|
|
arc: A4 V02N0101
|
|
arc: A5 V00T0100
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 H00R0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 V02N0301
|
|
arc: B3 H00L0000
|
|
arc: B4 H01E0101
|
|
arc: B5 H02E0301
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0701
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0701 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C33:PLC2
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: A0 V01N0101
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 V02N0501
|
|
arc: A4 H02E0501
|
|
arc: A5 V00T0000
|
|
arc: A6 V00T0100
|
|
arc: A7 H00R0000
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V01N0001
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B4 H00L0000
|
|
arc: B5 H02E0101
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0401 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C34:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: V01S0000 Q2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C35:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 H02W0301
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C36:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
|
|
.tile R20C37:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
|
|
.tile R20C38:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R20C39:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R20C40:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R20C41:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C42:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 H02E0601
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C43:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0301 Q3
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0100
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 H02W0401
|
|
arc: M5 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q5
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0701 Q7
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C44:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
|
|
.tile R20C45:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
|
|
.tile R20C46:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0601 Q6
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C47:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q5
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q6
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C48:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
|
|
.tile R20C49:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
|
|
.tile R20C50:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C51:PLC2
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
|
|
.tile R20C52:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
|
|
.tile R20C53:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
|
|
.tile R20C54:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R20C55:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0201 Q2
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C56:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0201 H01E0001
|
|
|
|
.tile R20C57:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
|
|
.tile R20C58:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C59:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S1_V02S0101 H02W0101
|
|
|
|
.tile R20C60:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0201 S3_V06N0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H02E0101 Q3
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q5
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C61:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0101 Q3
|
|
arc: M3 H00R0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C62:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
|
|
.tile R20C63:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: A2 V00T0000
|
|
arc: A3 H02E0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V00B0000
|
|
arc: A6 V02N0301
|
|
arc: A7 H00L0000
|
|
arc: B0 N1_V02S0301
|
|
arc: B2 V02N0101
|
|
arc: B3 V01N0001
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 H00R0000
|
|
arc: B6 V02N0501
|
|
arc: B7 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 Q4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0701 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C64:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02S0501
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: A0 V01N0101
|
|
arc: A1 H00L0000
|
|
arc: A2 V00B0000
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 V02N0301
|
|
arc: A5 V00T0000
|
|
arc: A6 S1_V02N0301
|
|
arc: A7 V02N0101
|
|
arc: B0 H00R0100
|
|
arc: B1 N1_V02S0301
|
|
arc: B2 H00R0000
|
|
arc: B3 V01N0001
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 V02N0701
|
|
arc: B6 V00B0100
|
|
arc: B7 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0101 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C65:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: A0 V02N0701
|
|
arc: A1 V01N0101
|
|
arc: A2 V00T0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V00T0000
|
|
arc: B2 V01N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C66:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: W1_H02W0101 V02N0101
|
|
|
|
.tile R20C67:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R20C68:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
|
|
.tile R20C69:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C70:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: A2 H01E0001
|
|
arc: A3 V00T0000
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 V02N0301
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 H02W0701
|
|
arc: B0 N1_V02S0301
|
|
arc: B2 H00R0000
|
|
arc: B3 V02N0101
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 W1_H02E0101
|
|
arc: B6 H01E0101
|
|
arc: B7 V02N0501
|
|
arc: CE0 N1_V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C71:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 H00R0000
|
|
arc: A1 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V00B0000
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 H02E0701
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 H02E0301
|
|
arc: B1 H00R0100
|
|
arc: B2 H00L0000
|
|
arc: B3 H02E0101
|
|
arc: B4 V00B0100
|
|
arc: B5 V02N0701
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C72:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: V00B0000 V02N0201
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 E1_H01E0001
|
|
arc: B0 V02N0301
|
|
arc: B1 V00B0000
|
|
arc: B2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C73:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0100
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N3_V06N0003 Q3
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q1
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C74:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: M0 V00T0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C75:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A2 V02N0701
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 V02S0301
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 V00T0100
|
|
arc: A7 H02E0501
|
|
arc: B0 V00T0000
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 H00R0000
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 V02S0501
|
|
arc: B6 V02N0501
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C76:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: A0 V02N0701
|
|
arc: A1 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V02S0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 H02E0501
|
|
arc: A6 H00R0000
|
|
arc: A7 V02N0101
|
|
arc: B0 V00B0000
|
|
arc: B1 H02E0101
|
|
arc: B2 H02W0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 H02W0301
|
|
arc: B6 V00B0100
|
|
arc: B7 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C77:PLC2
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H00L0100
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: B0 H02W0301
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 E1_H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0100 Q5
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C78:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R20C79:PLC2
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0303 Q6
|
|
arc: M1 H02E0001
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C80:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R20C81:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
|
|
.tile R20C82:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q1
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0601 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C83:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 V06N0103
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: A0 N1_V02S0701
|
|
arc: A2 H02E0701
|
|
arc: A3 V02N0501
|
|
arc: A4 V00B0000
|
|
arc: A5 V00T0000
|
|
arc: A6 V02N0301
|
|
arc: A7 V02N0101
|
|
arc: B2 H02E0101
|
|
arc: B3 V01N0001
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 H00L0000
|
|
arc: B6 V02S0501
|
|
arc: B7 W1_H02E0301
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0001 Q0
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C84:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 V02N0701
|
|
arc: A1 H00L0000
|
|
arc: A2 H01E0001
|
|
arc: A3 H02W0701
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 V00T0000
|
|
arc: A6 H02W0501
|
|
arc: A7 V02N0301
|
|
arc: B0 H02E0301
|
|
arc: B1 V02N0101
|
|
arc: B2 H02W0301
|
|
arc: B3 H00R0000
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V00B0000
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0501 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0303 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C85:PLC2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: B0 V00T0000
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C86:PLC2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R20C87:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R21C26:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0100 H02W0101
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H02W0001
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q4
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C27:PLC2
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 V00T0000
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C28:PLC2
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
|
|
.tile R21C29:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R21C30:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R21C31:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02N0501
|
|
arc: CE0 H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: V01S0100 Q0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C32:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q1
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C33:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0100 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C34:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q1
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0000 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C35:PLC2
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 E3_H06W0203
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 Q1
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C36:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H00R0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0101 Q1
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: M0 V00T0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 E1_H02W0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q4
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C37:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 H02E0601
|
|
arc: M1 H00L0100
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 H02E0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C38:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R21C39:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C40:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R21C41:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: V00T0000 H02E0201
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0100 Q5
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q5
|
|
arc: W3_H06W0203 Q7
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C42:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q0
|
|
arc: M0 V00B0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q5
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0203 Q7
|
|
arc: V01S0100 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C44:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R21C45:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: H01W0000 Q4
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q3
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C46:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 N1_V02S0601
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00L0000
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q7
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C47:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0000
|
|
arc: M2 H02E0601
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q5
|
|
arc: V01S0000 Q7
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C48:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C49:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q5
|
|
arc: M2 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C50:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C51:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C52:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: W3_H06W0003 E1_H02W0001
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0501 Q5
|
|
arc: E3_H06E0003 Q3
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C53:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0001 Q2
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C54:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 V02N0601
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0301 Q1
|
|
arc: M1 W1_H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C55:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: C5 H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 V02S0401
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0303 F5
|
|
arc: F5 F5_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEC.K1.INIT 0000111100000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R21C56:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R21C57:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W1_H02W0201 V02N0201
|
|
|
|
.tile R21C58:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0000 H02E0201
|
|
arc: V00B0000 H02E0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C59:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R21C60:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0601 Q4
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 H02W0601
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N3_V06N0103 Q2
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0303 Q6
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C61:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 H02E0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 W1_H02E0101
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0601 Q6
|
|
arc: H01W0000 Q5
|
|
arc: M0 W1_H02E0601
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C62:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M5 H00R0000
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: V01S0100 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C63:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0001 Q2
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C64:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0101 Q1
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0601 Q4
|
|
arc: N1_V02N0701 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C65:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H02W0001
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: V01S0000 Q7
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C66:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 V02N0601
|
|
|
|
.tile R21C67:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
|
|
.tile R21C68:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: V00T0100 V02N0701
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C69:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02W0301
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0701 Q7
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M2 H02W0601
|
|
arc: M3 H02E0201
|
|
arc: M4 H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q5
|
|
arc: V01S0100 Q2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C70:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: CE0 V02S0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q5
|
|
arc: M0 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0000
|
|
arc: M5 H02E0001
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C71:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00T0100
|
|
arc: M1 H02E0001
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q5
|
|
arc: V01S0100 Q3
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C72:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 V00B0000
|
|
arc: A3 H02W0501
|
|
arc: A4 V02N0101
|
|
arc: A5 H02E0701
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 H02W0701
|
|
arc: B2 V02N0301
|
|
arc: B3 H02W0101
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0501
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 V00T0000
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0401 Q4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0701 Q5
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C73:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 V00B0000
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0000
|
|
arc: A5 H02E0501
|
|
arc: A6 H02W0701
|
|
arc: A7 H00R0000
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 H02E0301
|
|
arc: B2 H02E0101
|
|
arc: B3 V02N0301
|
|
arc: B4 V01S0000
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 H02W0301
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0501 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q6
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R21C74:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0303 N1_V02S0601
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 V02N0501
|
|
arc: A1 E1_H02W0501
|
|
arc: A2 E1_H02W0501
|
|
arc: B0 V00T0000
|
|
arc: B1 H01W0100
|
|
arc: B2 H01W0100
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R21C75:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 Q0
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0000
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C76:PLC2
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 V02N0501
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 H00L0100
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 N1_V02S0301
|
|
arc: A7 H02W0701
|
|
arc: B2 H01W0100
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 H02W0101
|
|
arc: B5 H00L0000
|
|
arc: B6 H02E0301
|
|
arc: B7 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0203 Q7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C77:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 H00L0000
|
|
arc: A2 V00B0000
|
|
arc: A3 H02E0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 V02N0101
|
|
arc: A6 H00R0000
|
|
arc: A7 V00T0100
|
|
arc: B0 V00T0000
|
|
arc: B1 H02E0301
|
|
arc: B2 V02S0301
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 V02S0701
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0100
|
|
arc: B7 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C78:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H00R0000
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 V00B0000
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: V00B0000 Q6
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C79:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: CE0 H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 H02E0601
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H02E0201
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C80:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C81:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 W1_H02E0001
|
|
arc: F4 F4_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q7
|
|
arc: V00B0000 F4
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C82:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02N0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: H01W0000 Q1
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0701 Q7
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C83:PLC2
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q0
|
|
arc: H01W0000 Q4
|
|
arc: M0 H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H02E0201
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q6
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0301 Q1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C84:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0100 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C85:PLC2
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R23C25:PLC2
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
|
|
.tile R23C26:PLC2
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00B0100 V02S0301
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q4
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C27:PLC2
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: W1_H02W0601 V06N0303
|
|
|
|
.tile R23C28:PLC2
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
|
|
.tile R23C29:PLC2
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R23C30:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R23C31:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00B0000 V02S0201
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C32:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0701 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C33:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R23C34:PLC2
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C35:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R23C36:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 H02W0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q1
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: M1 H00R0000
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0501 Q7
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C37:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C38:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C39:PLC2
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R23C40:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C41:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R23C42:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H00R0100
|
|
arc: CE1 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0000
|
|
arc: M2 E1_H02W0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C43:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0000 Q0
|
|
arc: W3_H06W0003 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C44:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C45:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C46:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0100 Q6
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0303 Q6
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C47:PLC2
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0301 Q3
|
|
arc: H01W0000 Q3
|
|
arc: M0 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 Q0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C48:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C49:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q3
|
|
arc: M3 E1_H02W0201
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C50:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q1
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0301 Q1
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C51:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q0
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0000
|
|
arc: M5 H02W0001
|
|
arc: M6 E1_H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q4
|
|
arc: V01S0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C52:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 H02E0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: M1 E1_H02W0001
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0100 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C53:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H02W0201
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E3_H06E0303 Q5
|
|
arc: H01W0000 Q5
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q3
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C54:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q5
|
|
arc: M2 V00T0000
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q5
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C55:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00R0100
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q4
|
|
arc: M0 H01E0001
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q5
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C56:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0100
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q5
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0100 Q1
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C57:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00T0000 V02S0401
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q3
|
|
arc: H01W0100 Q1
|
|
arc: M1 V01S0100
|
|
arc: M3 H00L0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 Q1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C58:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE1 H02W0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0000 Q2
|
|
arc: M2 H02W0601
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: V01S0100 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C59:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q5
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q5
|
|
arc: LSR1 V00T0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C60:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0003 H01E0001
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0103 Q2
|
|
arc: M2 V00T0000
|
|
arc: M4 V00T0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C61:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C62:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0100 Q7
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C63:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: M1 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C64:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q3
|
|
arc: M1 E1_H02W0001
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C65:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0000 Q7
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C66:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0401 Q6
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C67:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C68:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0401 Q4
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q3
|
|
arc: LSR1 H02W0501
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C69:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W3_H06W0003 E1_H02W0301
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H00L0000
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E3_H06E0103 Q1
|
|
arc: H01W0000 Q3
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q1
|
|
arc: N3_V06N0203 Q4
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C70:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q4
|
|
arc: M1 H02E0001
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C71:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: B0 H02W0101
|
|
arc: D0 E1_H02W0201
|
|
arc: E1_H01E0101 F0
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: W1_H02W0001 F0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 0011001100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R23C72:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R23C73:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q1
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q7
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C74:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0401 Q6
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0000
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M6 H02E0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0100 Q3
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C75:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: H01W0100 Q5
|
|
arc: M0 V00B0000
|
|
arc: M1 H02E0001
|
|
arc: M5 H00R0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q5
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0301 Q1
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0100 Q7
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C76:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0100 V02S0101
|
|
arc: CE1 V02N0201
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: M2 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q5
|
|
arc: V01S0100 Q2
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C77:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02S0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: CE0 H02W0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H02E0701 Q7
|
|
arc: M1 W1_H02E0001
|
|
arc: M4 V00B0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q4
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q1
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C78:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: H01W0000 Q2
|
|
arc: M0 V00T0100
|
|
arc: M1 H02W0001
|
|
arc: M2 W1_H02E0601
|
|
arc: M3 H00R0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0501 Q5
|
|
arc: S3_V06S0003 Q3
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0201 Q2
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C79:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: B0 E1_H02W0101
|
|
arc: C0 S1_V02N0601
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0301 Q3
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C80:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: CE1 H00L0100
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0201 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C81:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
|
|
.tile R23C82:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H02E0101
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: H01W0000 Q0
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M3 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0401 Q6
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C83:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: H01W0100 Q3
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: M3 W1_H02E0201
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0501 Q5
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0303 Q6
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C84:PLC2
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
|
|
.tile R23C85:PLC2
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
|
|
.tile R23C86:PLC2
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
|
|
.tile R23C87:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R24C29:PLC2
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
|
|
.tile R24C30:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R24C31:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: W1_H02W0601 V01N0001
|
|
|
|
.tile R24C32:PLC2
|
|
arc: N1_V02N0601 H02E0601
|
|
|
|
.tile R24C34:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
|
|
.tile R24C35:PLC2
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0501 H02W0501
|
|
|
|
.tile R24C36:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R24C37:PLC2
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C38:PLC2
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
|
|
.tile R24C39:PLC2
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: S3_V06S0103 H06W0103
|
|
|
|
.tile R24C40:PLC2
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R24C42:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R24C43:PLC2
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
|
|
.tile R24C44:PLC2
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
|
|
.tile R24C45:PLC2
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R24C46:PLC2
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: S3_V06S0003 Q3
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C47:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
|
|
.tile R24C48:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C49:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
|
|
.tile R24C50:PLC2
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 N1_V01S0100
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R24C51:PLC2
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0701 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C52:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R24C53:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R24C54:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R24C55:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: W3_H06W0103 N1_V01S0100
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: LSR1 H02E0501
|
|
arc: M4 H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C56:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q3
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C57:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R24C58:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0100 V02N0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C59:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
|
|
.tile R24C60:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R24C61:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R24C62:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C63:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C64:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06E0003
|
|
|
|
.tile R24C65:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R24C66:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 F0
|
|
arc: N1_V01N0101 F0
|
|
arc: N3_V06N0003 F0
|
|
arc: V01S0000 F0
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R24C67:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
|
|
.tile R24C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C69:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C70:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0401 H02W0401
|
|
|
|
.tile R24C71:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
|
|
.tile R24C72:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
|
|
.tile R24C73:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: CE0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: M1 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: S3_V06S0103 Q1
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C74:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q7
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H02E0001
|
|
arc: M6 H02W0401
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0601 Q6
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
arc: W3_H06W0103 Q2
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C75:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 H02E0601
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H01W0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0401 Q4
|
|
arc: W3_H06W0003 Q3
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0203 Q4
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C76:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile R24C77:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R24C78:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 V02N0701
|
|
arc: A2 V00T0000
|
|
arc: A3 V02S0701
|
|
arc: A4 V00T0100
|
|
arc: A5 H02E0501
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 H00R0000
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 H01E0101
|
|
arc: B5 V01S0000
|
|
arc: B6 V02S0501
|
|
arc: B7 V00B0000
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: S1_V02S0201 Q2
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C79:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: A0 V02S0701
|
|
arc: A1 H02E0701
|
|
arc: A2 H02W0501
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0100
|
|
arc: A5 V00T0000
|
|
arc: A6 V02S0101
|
|
arc: A7 H00L0000
|
|
arc: B0 N1_V02S0301
|
|
arc: B1 V00B0000
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 H00R0000
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 W1_H02E0301
|
|
arc: B6 H02W0101
|
|
arc: B7 H02E0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0501 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C80:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H00L0000
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 H00L0100
|
|
arc: B0 H01W0100
|
|
arc: B1 N1_V02S0101
|
|
arc: B2 E1_H02W0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C81:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
|
|
.tile R24C82:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
|
|
.tile R24C83:PLC2
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R24C84:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
|
|
.tile R24C85:PLC2
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
|
|
.tile R24C86:PLC2
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
|
|
.tile R24C87:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
|
|
.tile R24C88:PLC2
|
|
arc: W1_H02W0601 H01E0001
|
|
|
|
.tile R25C25:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
|
|
.tile R25C26:PLC2
|
|
arc: N1_V02N0601 H01E0001
|
|
|
|
.tile R25C31:PLC2
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile R25C35:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
|
|
.tile R25C37:PLC2
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
|
|
.tile R25C39:PLC2
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
|
|
.tile R25C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
|
|
.tile R25C46:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R25C47:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
|
|
.tile R25C48:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: N1_V02N0101 H02W0101
|
|
|
|
.tile R25C49:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 V06N0103
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 V06N0103
|
|
|
|
.tile R25C50:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0401
|
|
arc: A2 V00B0000
|
|
arc: A3 V01N0101
|
|
arc: A4 V00T0000
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 V02S0301
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 V02S0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B4 V02N0701
|
|
arc: B5 H00R0000
|
|
arc: B6 H02E0101
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C51:PLC2
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: A0 H00L0000
|
|
arc: A1 H02E0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V01N0101
|
|
arc: A4 V00T0100
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 V02N0301
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 V02N0101
|
|
arc: B1 V01N0001
|
|
arc: B2 H02W0101
|
|
arc: B3 V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0401 Q6
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C52:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 V01N0101
|
|
arc: A1 V02N0501
|
|
arc: A2 V02S0701
|
|
arc: A3 V02S0701
|
|
arc: B0 V02S0301
|
|
arc: B1 V02N0301
|
|
arc: B2 V01N0001
|
|
arc: B3 V01N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q3
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C53:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R25C54:PLC2
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
|
|
.tile R25C55:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N1_V02N0601 H06W0303
|
|
|
|
.tile R25C56:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R25C57:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C58:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C59:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
|
|
.tile R25C60:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
|
|
.tile R25C61:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R25C63:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R25C64:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R25C65:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R25C66:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R25C67:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R25C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0301 H06E0003
|
|
|
|
.tile R25C69:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C70:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 V02S0401
|
|
arc: V00T0000 H02E0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: LSR0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C71:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile R25C72:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
|
|
.tile R25C73:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: A0 H02E0701
|
|
arc: A2 V02N0501
|
|
arc: A3 H02W0701
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 V02N0101
|
|
arc: A6 H00R0000
|
|
arc: A7 W1_H02E0501
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 V02N0301
|
|
arc: B4 H02W0301
|
|
arc: B5 H02W0101
|
|
arc: B6 V02N0701
|
|
arc: B7 S1_V02N0701
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0103 Q1
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M1 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C74:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 V02N0501
|
|
arc: A1 V01N0101
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 H02W0701
|
|
arc: A6 H02E0701
|
|
arc: A7 N1_V02S0301
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V02N0301
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 V02N0701
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C75:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
arc: A0 V02N0501
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 V00T0000
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0101
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 V02N0301
|
|
arc: B2 H02E0301
|
|
arc: B3 V02N0101
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 N1_V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0601 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 F4
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C76:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 E1_H02W0701
|
|
arc: A2 H00L0100
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 V00T0000
|
|
arc: A5 V00B0000
|
|
arc: A6 H00L0000
|
|
arc: A7 V02S0101
|
|
arc: B2 V02N0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 V02N0701
|
|
arc: B5 V02S0501
|
|
arc: B6 V01S0000
|
|
arc: B7 S1_V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: S1_V02S0101 Q1
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C77:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 H00L0000
|
|
arc: A2 V02N0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0100
|
|
arc: A6 H02E0701
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 H00R0100
|
|
arc: B1 H02E0301
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 H02W0101
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 H02E0101
|
|
arc: B6 N1_V02S0701
|
|
arc: B7 S1_V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0201 Q2
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: V01S0000 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C78:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0501
|
|
arc: B0 H02E0101
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C79:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02S0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 W1_H02E0701
|
|
arc: A2 V00T0000
|
|
arc: A3 H00L0100
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 V02S0301
|
|
arc: A6 H02E0501
|
|
arc: A7 H00R0000
|
|
arc: B2 V02S0101
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 N1_V02S0501
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C80:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: A0 V02S0701
|
|
arc: A1 H02E0501
|
|
arc: A2 V00B0000
|
|
arc: A3 H00L0100
|
|
arc: A4 V02S0101
|
|
arc: A5 H02W0501
|
|
arc: A6 H00R0000
|
|
arc: A7 H00L0000
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 N1_V02S0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C81:PLC2
|
|
arc: E1_H02E0601 V06N0303
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A0 H02E0501
|
|
arc: A1 H00R0000
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 N1_V02S0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q3
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C82:PLC2
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R25C83:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
|
|
.tile R25C84:PLC2
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
|
|
.tile R25C85:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R25C86:PLC2
|
|
arc: S1_V02S0101 V01N0101
|
|
|
|
.tile R25C87:PLC2
|
|
arc: S1_V02S0301 V01N0101
|
|
|
|
.tile R26C27:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R26C33:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R26C34:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R26C35:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R26C36:PLC2
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R26C37:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R26C40:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R26C42:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R26C45:PLC2
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
|
|
.tile R26C46:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
|
|
.tile R26C48:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
|
|
.tile R26C49:PLC2
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
|
|
.tile R26C50:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: A2 H02E0701
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 H02E0501
|
|
arc: A5 V02S0301
|
|
arc: A6 H02W0701
|
|
arc: A7 V02N0101
|
|
arc: B0 N1_V02S0101
|
|
arc: B2 H02W0301
|
|
arc: B3 H02E0301
|
|
arc: B4 H02W0101
|
|
arc: B5 V02N0701
|
|
arc: B6 V02N0501
|
|
arc: B7 S1_V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C51:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 H00L0100
|
|
arc: A1 H02W0501
|
|
arc: A2 V02N0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0101
|
|
arc: A6 V02S0301
|
|
arc: A7 H00R0000
|
|
arc: B0 V02N0301
|
|
arc: B1 V02S0101
|
|
arc: B2 H00L0000
|
|
arc: B3 H02W0101
|
|
arc: B4 V02S0501
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 V00B0000
|
|
arc: B7 H02W0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C52:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 S3_V06N0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 H02E0701
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: B0 V02N0101
|
|
arc: B1 N1_V02S0101
|
|
arc: B2 N1_V02S0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0301 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C53:PLC2
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R26C54:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile R26C55:PLC2
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
|
|
.tile R26C56:PLC2
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R26C57:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R26C58:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R26C60:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
|
|
.tile R26C61:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R26C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R26C63:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R26C64:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R26C66:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
|
|
.tile R26C67:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R26C68:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R26C69:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
|
|
.tile R26C70:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R26C72:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R26C73:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 H02E0701
|
|
arc: A2 V00B0000
|
|
arc: A3 H00L0100
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B2 H00L0000
|
|
arc: B3 V02S0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02S0501
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0701
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0501 Q7
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C74:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00L0100
|
|
arc: A2 H02W0501
|
|
arc: A3 V02S0501
|
|
arc: A4 V00T0000
|
|
arc: A5 Q5
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 Q7
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0101
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V01S0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C75:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H02W0701
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 V02S0701
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V00T0100
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0101
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: B4 V01S0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0501
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C76:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 H02E0701
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 Q5
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 Q7
|
|
arc: B0 H02W0101
|
|
arc: B1 V02S0101
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 H00L0000
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 V01S0000
|
|
arc: B7 V00B0000
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C77:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 H02W0101
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0301 Q1
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C78:PLC2
|
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arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q7
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: M2 H02E0601
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0701 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C79:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00R0000 V02S0601
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 H00R0000
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V00T0000
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 V02N0101
|
|
arc: A7 V02S0301
|
|
arc: B2 V02S0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 V02S0501
|
|
arc: B6 V02S0701
|
|
arc: B7 S1_V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C80:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: V00B0000 H02E0401
|
|
arc: A0 H00L0000
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V00B0000
|
|
arc: A6 H02W0501
|
|
arc: A7 H02W0701
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0301
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 V02S0701
|
|
arc: B5 H00R0000
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 S1_V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C81:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0100 V02S0301
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H00L0100
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 N1_V02S0701
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 V02S0101
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 W1_H02E0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q3
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C82:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V02N0301
|
|
arc: A5 V02N0101
|
|
arc: A6 H02E0501
|
|
arc: A7 H02W0501
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 H02E0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C83:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: A0 H00L0000
|
|
arc: A1 H00R0000
|
|
arc: A2 V02N0701
|
|
arc: A3 H00L0100
|
|
arc: A4 H02W0501
|
|
arc: A5 V02N0101
|
|
arc: A6 H02E0701
|
|
arc: A7 H02E0501
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0101
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C84:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: A0 H00L0100
|
|
arc: A1 H00R0000
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0701
|
|
arc: A4 H02E0701
|
|
arc: A5 H02E0701
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 V02N0501
|
|
arc: B5 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0401 F4
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICED.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C85:PLC2
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
|
|
.tile R26C86:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C87:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C88:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H00R0000
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0401 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C36:PLC2
|
|
arc: S1_V02S0001 H06W0003
|
|
|
|
.tile R27C39:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R27C45:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C47:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R27C49:PLC2
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
|
|
.tile R27C50:PLC2
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 H02E0701
|
|
|
|
.tile R27C51:PLC2
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R27C52:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
|
|
.tile R27C53:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
|
|
.tile R27C54:PLC2
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
|
|
.tile R27C57:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R27C58:PLC2
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C59:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R27C60:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
|
|
.tile R27C61:PLC2
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
|
|
.tile R27C63:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R27C64:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C65:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C66:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C67:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R27C69:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R27C70:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C71:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0003 H01E0001
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile R27C72:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
|
|
.tile R27C73:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 H02E0701
|
|
arc: A2 V00B0000
|
|
arc: A3 V02N0701
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V02N0301
|
|
arc: A6 V02N0101
|
|
arc: A7 S1_V02N0301
|
|
arc: B2 V01N0001
|
|
arc: B3 V02S0101
|
|
arc: B4 H00L0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0501
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C74:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02N0401
|
|
arc: A0 V01N0101
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 H00R0000
|
|
arc: A7 H00R0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V01N0001
|
|
arc: B2 H00L0000
|
|
arc: B3 V02S0101
|
|
arc: B4 H02E0301
|
|
arc: B5 H00R0000
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C75:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02S0501
|
|
arc: W3_H06W0103 V06S0103
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0701
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V02N0101
|
|
arc: A6 V02N0301
|
|
arc: A7 V00T0100
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 H00R0100
|
|
arc: B3 V02S0301
|
|
arc: B4 V02N0501
|
|
arc: B5 V02S0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0701
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C76:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02N0401
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V00T0000
|
|
arc: A4 N1_V02S0301
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 H00R0000
|
|
arc: A7 H00R0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B2 H00R0000
|
|
arc: B3 V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B5 H00R0000
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C77:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02E0201
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0501
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 H02E0701
|
|
arc: A6 H02E0701
|
|
arc: A7 V02N0301
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0301
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 W1_H02E0301
|
|
arc: B6 H02E0101
|
|
arc: B7 H02E0101
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 V00T0000
|
|
arc: C6 H02E0601
|
|
arc: C7 H02E0601
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 W1_H02E0201
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 H02E0201
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: M5 H00R0000
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q6
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C78:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A4 V02S0101
|
|
arc: A6 H02E0501
|
|
arc: A7 V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V00T0000
|
|
arc: C4 V02N0001
|
|
arc: C6 V02N0201
|
|
arc: C7 V02N0201
|
|
arc: D4 H02E0201
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F7
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F4
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R27C79:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: A2 W1_H02E0501
|
|
arc: B2 H02E0101
|
|
arc: C2 H02E0401
|
|
arc: D2 W1_H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H02E0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0000
|
|
arc: M6 E1_H02W0401
|
|
arc: S1_V02S0301 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R27C80:PLC2
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
|
|
.tile R27C81:PLC2
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
|
|
.tile R27C82:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
|
|
.tile R27C83:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0701 H06E0203
|
|
|
|
.tile R27C84:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: A0 N1_V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A3 H00L0100
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 H02W0501
|
|
arc: A7 Q7
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V00B0100
|
|
arc: B6 V00B0000
|
|
arc: B7 V02N0501
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q7
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C85:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 H02E0501
|
|
arc: A4 V02N0101
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 H02W0501
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 V02S0101
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: B5 V00B0100
|
|
arc: B6 V00B0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q5
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C86:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 Q5
|
|
arc: A6 N1_V02S0101
|
|
arc: A7 Q7
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 V02S0301
|
|
arc: B2 H01W0100
|
|
arc: B3 V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00B0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q7
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C87:PLC2
|
|
arc: H00R0100 H02W0501
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 H00L0000
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0701
|
|
arc: A3 V00T0000
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 Q5
|
|
arc: A6 V02N0301
|
|
arc: A7 N1_V02S0301
|
|
arc: B0 V02S0301
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C88:PLC2
|
|
arc: H00R0100 V02N0501
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: B0 V02S0101
|
|
arc: B1 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C27:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R28C33:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R28C35:PLC2
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R28C36:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00B0000 V02S0001
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q4
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C37:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
|
|
.tile R28C39:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R28C40:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C41:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R28C42:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R28C43:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C45:PLC2
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
|
|
.tile R28C46:PLC2
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: S3_V06S0003 Q3
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C47:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C48:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
|
|
.tile R28C49:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: B1 H02E0101
|
|
arc: D1 E1_H02W0201
|
|
arc: E3_H06E0103 F1
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 F1
|
|
arc: N3_V06N0103 F1
|
|
arc: S1_V02S0101 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: W1_H02W0101 F1
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K1.INIT 0011001100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R28C50:PLC2
|
|
arc: N1_V02N0701 H02E0701
|
|
|
|
.tile R28C51:PLC2
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
|
|
.tile R28C54:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R28C55:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R28C57:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C58:PLC2
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
|
|
.tile R28C60:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
|
|
.tile R28C61:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C63:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C64:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R28C66:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R28C67:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C69:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R28C70:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C71:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
|
|
.tile R28C72:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: S1_V02S0401 H06W0203
|
|
|
|
.tile R28C73:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 H02E0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q3
|
|
arc: V01S0100 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C74:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 H02W0301
|
|
arc: CE0 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0601 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0401 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C75:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: A0 H00L0000
|
|
arc: A1 F7
|
|
arc: A2 H00L0100
|
|
arc: A4 H02E0701
|
|
arc: A5 E1_H01W0000
|
|
arc: A7 F5
|
|
arc: B0 E1_H01W0100
|
|
arc: B2 V02N0101
|
|
arc: B4 V01S0000
|
|
arc: B7 V00B0100
|
|
arc: C0 E1_H01W0000
|
|
arc: C2 H02E0601
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V00T0000
|
|
arc: C7 F4
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V00T0100
|
|
arc: D4 H01W0000
|
|
arc: D5 H02W0001
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 Q1
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0303 F5
|
|
arc: V00B0100 Q7
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0301 Q1
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K1.INIT 1010101000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000000000010000
|
|
word: SLICEA.K0.INIT 0001000000000000
|
|
word: SLICEC.K1.INIT 0000000000000101
|
|
word: SLICED.K1.INIT 0010000000100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C76:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: A4 V02S0101
|
|
arc: A5 V02S0101
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B2 H01W0100
|
|
arc: B4 H02E0301
|
|
arc: C0 H00L0000
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C4 Q4
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V01S0100
|
|
arc: D2 Q2
|
|
arc: D4 H00R0100
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICEA.K0.INIT 0000001100001111
|
|
word: SLICEA.K1.INIT 1100001111110000
|
|
word: SLICEC.K1.INIT 0000000001010101
|
|
word: SLICEC.K0.INIT 0000000000001000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET SET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R28C77:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A7 N1_V01S0100
|
|
arc: B2 H00L0000
|
|
arc: B7 N1_V01S0000
|
|
arc: C2 W1_H02E0401
|
|
arc: C7 H01E0001
|
|
arc: D2 V02S0001
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R28C78:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00B0100 H02E0501
|
|
arc: A1 F7
|
|
arc: A3 F7
|
|
arc: A7 W1_H02E0701
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B7 V02S0701
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 N1_V01S0100
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D3 N1_V01S0000
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M4 E1_H01E0101
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K1.INIT 1000100000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010000000000000
|
|
word: SLICEB.K0.INIT 0011001100110011
|
|
word: SLICEB.K1.INIT 1011001100110011
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C79:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A1 V02S0701
|
|
arc: B1 W1_H02E0301
|
|
arc: C1 H02E0601
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R28C80:PLC2
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: W1_H02W0001 H01E0001
|
|
|
|
.tile R28C81:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R28C82:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
|
|
.tile R28C83:PLC2
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0100 H02E0101
|
|
arc: CE1 V02N0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0203 Q7
|
|
arc: LSR1 V00B0000
|
|
arc: M2 V00T0100
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C84:PLC2
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02W0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A2 V00B0000
|
|
arc: A3 V01N0101
|
|
arc: A4 V02N0101
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 H00R0000
|
|
arc: A7 V00T0100
|
|
arc: B0 H01W0100
|
|
arc: B2 V01N0001
|
|
arc: B3 V02S0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H00L0000
|
|
arc: B6 V02N0701
|
|
arc: B7 H01E0101
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C85:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 H00R0000
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 W1_H02E0701
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0101
|
|
arc: B2 H00L0000
|
|
arc: B3 V02S0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02S0701
|
|
arc: B6 V00T0000
|
|
arc: B7 N1_V02S0701
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q5
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C86:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: A3 H02W0701
|
|
arc: A4 H02W0701
|
|
arc: A5 H02W0701
|
|
arc: A6 H02W0701
|
|
arc: A7 H02W0701
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0301
|
|
arc: B2 H00L0000
|
|
arc: B3 V02S0101
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0701
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C87:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 S3_V06N0103
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0101
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C88:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: V00B0000 V02S0001
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0101
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0100 Q1
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C18:PLC2
|
|
arc: S3_V06S0203 H06W0203
|
|
|
|
.tile R29C21:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C27:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C33:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C37:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R29C38:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R29C39:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R29C40:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R29C45:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C46:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R29C47:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R29C48:PLC2
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R29C49:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R29C51:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R29C52:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C54:PLC2
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
|
|
.tile R29C57:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C58:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R29C63:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C64:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C69:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C70:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C71:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R29C72:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R29C73:PLC2
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R29C74:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q2
|
|
arc: LSR1 V00T0000
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C75:PLC2
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0000 H02W0001
|
|
arc: H00L0100 H02E0101
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 V02S0701
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 H02W0501
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 V00B0000
|
|
arc: B3 H00L0000
|
|
arc: B7 H02W0301
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C5 E1_H01E0101
|
|
arc: C7 V00T0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M4 H02E0401
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0101 Q1
|
|
arc: V00B0100 Q7
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEB.K0.INIT 0000000000001010
|
|
word: SLICEB.K1.INIT 0000100000001010
|
|
word: SLICED.K1.INIT 0000011100000000
|
|
word: SLICEC.K1.INIT 0101101010100101
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C76:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A2 H00L0100
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 N1_V01S0100
|
|
arc: B2 H02E0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 N1_V01S0000
|
|
arc: C2 N1_V01S0100
|
|
arc: C4 V00T0100
|
|
arc: C5 V00B0100
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0201
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H01W0100 F4
|
|
arc: LSR1 V00T0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00B0100 Q5
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEC.K0.INIT 1111000011110010
|
|
word: SLICEC.K1.INIT 0000111101001011
|
|
word: SLICEB.K0.INIT 0000000010000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C77:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: A3 F7
|
|
arc: A5 V00T0000
|
|
arc: A7 F5
|
|
arc: B0 H02E0301
|
|
arc: B3 H02E0101
|
|
arc: B5 H02E0301
|
|
arc: B7 V01S0000
|
|
arc: C0 H02E0601
|
|
arc: C3 H00L0000
|
|
arc: C5 V00T0100
|
|
arc: C7 V00B0100
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D3 H02E0001
|
|
arc: D5 H02E0201
|
|
arc: D7 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0501 F7
|
|
word: SLICED.K1.INIT 0101010101000000
|
|
word: SLICEB.K1.INIT 0000100000100000
|
|
word: SLICEA.K0.INIT 1111110011111111
|
|
word: SLICEC.K1.INIT 0000000000001000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C78:PLC2
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 H06E0303
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
|
|
.tile R29C79:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R29C81:PLC2
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C82:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R29C83:PLC2
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
|
|
.tile R29C84:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02S0401
|
|
arc: A4 V00B0000
|
|
arc: A6 N1_V01S0100
|
|
arc: B4 N1_V01S0000
|
|
arc: B6 V02S0501
|
|
arc: C1 H02W0401
|
|
arc: C4 E1_H01E0101
|
|
arc: C6 H02W0601
|
|
arc: CE0 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0201
|
|
arc: D4 V02S0601
|
|
arc: D6 V02S0601
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0601 F6
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H01W0000 F1
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 W1_H02E0001
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 H02W0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0701 Q7
|
|
arc: V00B0000 Q4
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000010000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET SET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R29C85:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N3_V06N0003 H06W0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A2 V02S0701
|
|
arc: A3 V02S0501
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 V00T0000
|
|
arc: A6 F5
|
|
arc: A7 V02S0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 H00R0000
|
|
arc: B6 F3
|
|
arc: B7 V02S0701
|
|
arc: C0 V02N0401
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 H02W0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V00T0000
|
|
arc: C5 V02S0001
|
|
arc: C6 H01E0001
|
|
arc: C7 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V02S0001
|
|
arc: D2 V02S0201
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V02S0401
|
|
arc: D5 N1_V02S0401
|
|
arc: D6 H00R0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0401 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F2
|
|
word: SLICEA.K0.INIT 1111110000000011
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000000000000010
|
|
word: SLICEA.K1.INIT 0000000000000011
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C86:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A1 V02S0501
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 E1_H01E0001
|
|
arc: A5 V00T0000
|
|
arc: A6 H00L0000
|
|
arc: B1 V02S0101
|
|
arc: B2 V01N0001
|
|
arc: B3 V01N0001
|
|
arc: B5 H01E0101
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 E1_H02W0301
|
|
arc: C1 H02W0601
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C5 W1_H02E0601
|
|
arc: C6 H01E0001
|
|
arc: C7 H01E0001
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0201
|
|
arc: D5 H02W0001
|
|
arc: D6 E1_H02W0201
|
|
arc: D7 F0
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H02E0401 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00R0100 Q5
|
|
arc: LSR1 H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M4 H02E0401
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00B0000
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 F4
|
|
arc: W1_H02W0201 F2
|
|
word: SLICED.K0.INIT 1011001100110011
|
|
word: SLICEB.K0.INIT 1001011001101001
|
|
word: SLICEB.K1.INIT 0110100110010110
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C87:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0401
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A1 V02S0701
|
|
arc: A2 V02S0501
|
|
arc: A4 E1_H02W0501
|
|
arc: A7 N1_V01S0100
|
|
arc: B1 V00B0000
|
|
arc: B2 H00L0000
|
|
arc: B4 V02N0701
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V02S0501
|
|
arc: B7 V02S0701
|
|
arc: C1 H00L0100
|
|
arc: C2 V02S0601
|
|
arc: C6 V02S0201
|
|
arc: C7 V02S0001
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H00R0000
|
|
arc: D2 N1_V02S0201
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 H02E0201
|
|
arc: D6 V02S0601
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V00B0100 F5
|
|
arc: V01S0000 Q4
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0501 F7
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEC.K0.INIT 1011101110001000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000110011
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 1100000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R29C88:PLC2
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 S1_V02N0501
|
|
arc: B0 V02S0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1011101110001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C36:PLC2
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q6
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C37:PLC2
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R30C39:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R30C40:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R30C42:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R30C45:PLC2
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S3_V06S0003 H06E0003
|
|
|
|
.tile R30C46:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M4 H02W0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0601 Q4
|
|
arc: N3_V06N0203 Q4
|
|
arc: S3_V06S0203 Q4
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C47:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C48:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R30C49:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
|
|
.tile R30C50:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S3_V06S0303 H06W0303
|
|
|
|
.tile R30C51:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R30C52:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R30C53:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R30C58:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R30C59:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R30C60:PLC2
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
|
|
.tile R30C64:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R30C65:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R30C70:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R30C71:PLC2
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R30C73:PLC2
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R30C74:PLC2
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0000 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 V00T0000
|
|
arc: M7 E1_H01W0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0701 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C75:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 N1_V02S0601
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V00B0000 F4
|
|
word: SLICEC.K0.INIT 0000000011111111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C76:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R30C77:PLC2
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00T0000 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: LSR1 V00T0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0203 Q7
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C78:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R30C79:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R30C81:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
|
|
.tile R30C82:PLC2
|
|
arc: H00R0100 H02E0701
|
|
arc: C3 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 H02E0001
|
|
arc: D7 H01W0000
|
|
arc: E1_H02E0501 Q5
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: LSR1 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N3_V06N0003 F3
|
|
arc: V00B0100 F7
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICED.K1.INIT 0000000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C83:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: H00R0100 H02E0501
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: V00T0000 H02W0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: LSR1 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V01S0000 Q3
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C84:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0201 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H01E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C85:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 H00L0100
|
|
arc: A5 V00T0000
|
|
arc: A6 E1_H02W0701
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 H01W0100
|
|
arc: B5 H00L0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 N1_V01N0001
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 E1_H01E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H00R0000
|
|
arc: D2 Q2
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F0
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M0 V00B0000
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M5 H00R0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0701 Q5
|
|
arc: V00B0000 F6
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 1010000000000000
|
|
word: SLICEC.K1.INIT 0000000001001100
|
|
word: SLICEA.K0.INIT 0001000000010000
|
|
word: SLICEA.K1.INIT 0101000000010000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C86:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: A0 F7
|
|
arc: A1 F7
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 F5
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 E1_H01W0000
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 V01S0000
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 E1_H02W0101
|
|
arc: C3 F4
|
|
arc: C4 H02E0401
|
|
arc: C5 V00T0000
|
|
arc: C6 V00T0000
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 F0
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 E1_H02W0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 F4
|
|
arc: H01W0100 F1
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0401 F6
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICED.K0.INIT 0000000010000000
|
|
word: SLICEC.K0.INIT 0101010101000000
|
|
word: SLICED.K1.INIT 0000001100000011
|
|
word: SLICEA.K0.INIT 0101010111111111
|
|
word: SLICEC.K1.INIT 0000000001000000
|
|
word: SLICEB.K1.INIT 0001000010000000
|
|
word: SLICEB.K0.INIT 1010101001100110
|
|
word: SLICEA.K1.INIT 0000000010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R30C87:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 V02S0701
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 V00T0000
|
|
arc: B0 E1_H01W0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B5 V00B0100
|
|
arc: C0 E1_H01W0000
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 V00T0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0001
|
|
arc: D5 V02N0601
|
|
arc: E1_H01E0001 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 F3
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0100
|
|
arc: M5 H00L0100
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0000001000000000
|
|
word: SLICEB.K0.INIT 0000001100000000
|
|
word: SLICEB.K1.INIT 1111000011110010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R30C88:PLC2
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: B0 V00T0000
|
|
arc: C0 H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 Q1
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEA.K1.INIT 1111111110101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R31C31:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R31C35:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R31C37:PLC2
|
|
arc: E3_H06E0003 F3
|
|
arc: F3 F3_SLICE
|
|
arc: N3_V06N0003 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R31C38:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R31C41:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R31C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile R31C46:PLC2
|
|
arc: S3_V06S0003 H06E0003
|
|
|
|
.tile R31C47:PLC2
|
|
arc: H00L0000 H02W0001
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: S3_V06S0003 Q3
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C48:PLC2
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
|
|
.tile R31C49:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W1_H02W0101 V06S0103
|
|
|
|
.tile R31C50:PLC2
|
|
arc: S3_V06S0003 H06E0003
|
|
|
|
.tile R31C52:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R31C53:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile R31C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R31C61:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R31C67:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R31C73:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R31C74:PLC2
|
|
arc: N1_V02N0401 H02W0401
|
|
|
|
.tile R31C75:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: W1_H02W0401 V06N0203
|
|
|
|
.tile R31C76:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R31C77:PLC2
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile R31C78:PLC2
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R31C79:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R31C80:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R31C81:PLC2
|
|
arc: E1_H02E0401 V06N0203
|
|
|
|
.tile R31C82:PLC2
|
|
arc: N1_V02N0401 H02E0401
|
|
|
|
.tile R31C85:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
|
|
.tile R31C86:PLC2
|
|
arc: N1_V02N0601 H02E0601
|
|
|
|
.tile R31C87:PLC2
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
|
|
.tile R31C88:PLC2
|
|
arc: N1_V02N0501 H02W0501
|
|
|
|
.tile R32C34:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R32C35:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
|
|
.tile R32C36:PLC2
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: S3_V06S0303 N1_V02S0601
|
|
|
|
.tile R32C37:PLC2
|
|
arc: N3_V06N0203 H06W0203
|
|
|
|
.tile R32C38:PLC2
|
|
arc: S3_V06S0203 H06W0203
|
|
|
|
.tile R32C40:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R32C41:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C45:PLC2
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
|
|
.tile R32C46:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: V00B0100 H02E0501
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q4
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0203 Q4
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C47:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: M1 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0301 Q1
|
|
arc: S3_V06S0103 Q1
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
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enum: CLK0.CLKMUX CLK
|
|
|
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.tile R32C48:PLC2
|
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arc: E3_H06E0003 S3_V06N0003
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0303 S3_V06N0203
|
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arc: W1_H02W0101 S1_V02N0101
|
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|
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.tile R32C49:PLC2
|
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arc: N3_V06N0003 S3_V06N0303
|
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arc: N3_V06N0303 S3_V06N0203
|
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arc: W1_H02W0101 S1_V02N0101
|
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arc: W1_H02W0601 E1_H02W0301
|
|
|
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.tile R32C50:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
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arc: N3_V06N0103 S3_V06N0103
|
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arc: N3_V06N0203 S3_V06N0203
|
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arc: N3_V06N0303 S3_V06N0303
|
|
|
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.tile R32C51:PLC2
|
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arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W1_H02W0301 V06S0003
|
|
|
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.tile R32C52:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R32C53:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
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.tile R32C58:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
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.tile R32C59:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
|
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.tile R32C60:PLC2
|
|
arc: N1_V02N0301 H01E0101
|
|
|
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.tile R32C74:PLC2
|
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arc: S3_V06S0203 N1_V02S0701
|
|
|
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.tile R32C75:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
|
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.tile R32C76:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
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.tile R32C77:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R32C78:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R32C79:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R32C84:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R32C87:PLC2
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R33C35:PLC2
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R33C41:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R33C47:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C49:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: W1_H02W0101 V02N0101
|
|
|
|
.tile R33C52:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R33C73:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R33C75:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R33C76:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R33C77:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: S3_V06S0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C78:PLC2
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
|
|
.tile R33C79:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R35C18:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R35C37:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R35C38:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R35C40:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R35C45:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R35C46:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R35C47:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R35C48:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R35C49:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R35C52:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R35C71:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R35C72:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R35C73:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R35C74:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R35C75:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R35C76:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R35C77:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R35C78:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R35C79:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R36C36:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R36C37:PLC2
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R36C39:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R36C40:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R36C43:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R36C45:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R36C46:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R36C47:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R36C48:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R36C49:PLC2
|
|
arc: H00R0000 H02W0601
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: CE0 N1_V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: N3_V06N0103 Q1
|
|
arc: S3_V06S0103 Q1
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C50:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
|
|
.tile R36C51:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R36C52:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
|
|
.tile R36C55:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R36C58:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R36C73:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R36C74:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0000 Q7
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
arc: S1_V02S0701 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C75:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R36C76:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
|
|
.tile R36C77:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R36C78:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R36C79:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R36C80:PLC2
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R37C37:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R37C38:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R37C46:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R37C47:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R37C49:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R37C50:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R37C52:PLC2
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R37C73:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R37C75:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R37C76:PLC2
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R37C78:PLC2
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R37C79:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R37C80:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R38C36:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R38C38:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R38C46:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R38C47:PLC2
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 S3_V06N0203
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arc: E3_H06E0303 S3_V06N0303
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0203 N3_V06S0103
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.tile R38C48:PLC2
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arc: E3_H06E0003 S3_V06N0003
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arc: N3_V06N0003 S3_V06N0303
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arc: N3_V06N0203 S3_V06N0103
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arc: N3_V06N0303 S3_V06N0203
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.tile R38C49:PLC2
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arc: E3_H06E0103 S3_V06N0103
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arc: N1_V02N0401 H06E0203
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arc: N1_V02N0501 H06E0303
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arc: N3_V06N0203 S3_V06N0203
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arc: N3_V06N0303 S3_V06N0303
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.tile R38C50:PLC2
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arc: N1_V02N0501 H06E0303
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0103 H06E0103
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arc: N3_V06N0203 H06E0203
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arc: N3_V06N0303 S3_V06N0303
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.tile R38C51:PLC2
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arc: N1_V02N0001 H06E0003
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arc: N1_V02N0501 S3_V06N0303
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0203
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.tile R38C52:PLC2
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arc: N1_V02N0101 H06E0103
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arc: N3_V06N0103 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0103
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.tile R38C74:PLC2
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arc: N1_V02N0701 N3_V06S0203
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arc: S1_V02S0301 N1_V02S0201
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arc: S3_V06S0003 N1_V02S0001
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arc: S3_V06S0203 N1_V02S0701
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.tile R38C76:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R38C77:PLC2
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arc: N1_V02N0501 S3_V06N0303
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0103
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arc: N3_V06N0303 S3_V06N0203
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.tile R38C78:PLC2
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arc: N1_V02N0701 S3_V06N0203
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0103
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arc: N3_V06N0303 S3_V06N0303
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.tile R38C79:PLC2
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0103 S3_V06N0103
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.tile R39C35:PLC2
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arc: S3_V06S0003 N3_V06S0303
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.tile R39C46:PLC2
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arc: E3_H06E0003 S3_V06N0003
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arc: E3_H06E0103 S3_V06N0103
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arc: E3_H06E0203 S3_V06N0203
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arc: E3_H06E0303 S3_V06N0303
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.tile R39C47:PLC2
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arc: S3_V06S0203 N3_V06S0203
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arc: S3_V06S0303 N3_V06S0203
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.tile R39C49:PLC2
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arc: N3_V06N0103 H06E0103
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arc: N3_V06N0303 H06E0303
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.tile R39C52:PLC2
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arc: N1_V02N0301 W3_H06E0003
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arc: N1_V02N0701 W3_H06E0203
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0103 S3_V06N0103
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arc: N3_V06N0203 S3_V06N0203
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arc: N3_V06N0303 S3_V06N0303
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.tile R39C73:PLC2
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arc: E3_H06E0103 S3_V06N0103
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arc: E3_H06E0203 S3_V06N0203
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arc: E3_H06E0303 S3_V06N0303
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arc: N3_V06N0003 S3_V06N0003
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.tile R39C75:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R39C76:PLC2
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arc: N1_V02N0101 H06E0103
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arc: N1_V02N0401 H06E0203
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arc: N1_V02N0601 H06E0303
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arc: N3_V06N0003 S1_V02N0001
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arc: N3_V06N0103 S3_V06N0003
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arc: N3_V06N0203 S1_V02N0701
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arc: N3_V06N0303 S3_V06N0303
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.tile R39C77:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R39C79:PLC2
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arc: N3_V06N0103 S3_V06N0103
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arc: N3_V06N0203 S3_V06N0203
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.tile R40C27:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C33:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C35:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R40C36:PLC2
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arc: N3_V06N0203 S3_V06N0103
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C37:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile R40C39:PLC2
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arc: S3_V06S0303 N3_V06S0203
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.tile R40C42:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C46:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R40C47:PLC2
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arc: S3_V06S0003 N3_V06S0303
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.tile R40C48:PLC2
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arc: N3_V06N0103 S3_V06N0103
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arc: S3_V06S0203 N3_V06S0203
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.tile R40C49:PLC2
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arc: S3_V06S0303 N3_V06S0203
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.tile R40C51:PLC2
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arc: N3_V06N0303 S3_V06N0303
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.tile R40C54:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R40C57:PLC2
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arc: N3_V06N0003 S3_V06N0303
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.tile R40C60:PLC2
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arc: N3_V06N0003 S3_V06N0303
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.tile R40C63:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R40C66:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R40C69:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C72:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C74:PLC2
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arc: S3_V06S0003 N1_V02S0301
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.tile R40C75:PLC2
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arc: N3_V06N0103 S3_V06N0003
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.tile R40C78:PLC2
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arc: N3_V06N0003 S3_V06N0303
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.tile R40C81:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R40C84:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R40C87:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R41C18:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R41C37:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R41C38:PLC2
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0103 N3_V06S0103
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.tile R41C40:PLC2
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arc: S3_V06S0003 N3_V06S0303
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.tile R41C45:PLC2
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arc: S3_V06S0203 N3_V06S0203
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.tile R41C46:PLC2
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0303
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.tile R41C47:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R41C48:PLC2
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arc: S1_V02S0001 S3_V06N0003
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arc: S1_V02S0401 S3_V06N0203
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arc: S3_V06S0003 N3_V06S0303
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.tile R41C49:PLC2
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0203 N3_V06S0103
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.tile R41C52:PLC2
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arc: N3_V06N0003 S3_V06N0303
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arc: N3_V06N0103 S3_V06N0103
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arc: N3_V06N0203 S3_V06N0203
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.tile R41C71:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R41C72:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R41C73:PLC2
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arc: E3_H06E0003 S3_V06N0003
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arc: E3_H06E0103 S3_V06N0103
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arc: E3_H06E0203 S3_V06N0203
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arc: S1_V02S0001 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0203 N3_V06S0203
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.tile R41C74:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R41C75:PLC2
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0203 N3_V06S0103
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.tile R41C76:PLC2
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arc: N1_V02N0001 H06E0003
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arc: N1_V02N0701 H06E0203
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arc: N3_V06N0003 S3_V06N0003
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arc: N3_V06N0103 H06E0103
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arc: N3_V06N0203 S3_V06N0103
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arc: N3_V06N0303 S3_V06N0203
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arc: S3_V06S0103 N3_V06S0003
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arc: V01S0000 N3_V06S0103
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.tile R41C77:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0003
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.tile R41C78:PLC2
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arc: S1_V02S0201 N3_V06S0103
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0303 N3_V06S0303
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arc: V01S0000 N3_V06S0103
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.tile R41C79:PLC2
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0303 N3_V06S0203
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.tile R42C36:PLC2
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arc: S1_V02S0001 N3_V06S0003
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.tile R42C37:PLC2
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arc: S1_V02S0201 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile R42C38:PLC2
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arc: S1_V02S0701 E1_H02W0701
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.tile R42C39:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile R42C40:PLC2
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arc: W1_H02W0701 N3_V06S0203
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.tile R42C45:PLC2
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arc: S1_V02S0001 N3_V06S0003
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.tile R42C46:PLC2
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arc: E1_H02E0601 N3_V06S0303
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arc: N3_V06N0103 S1_V02N0101
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arc: S1_V02S0101 N3_V06S0103
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arc: S1_V02S0701 N3_V06S0203
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0303 N3_V06S0303
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arc: V01S0100 N3_V06S0303
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.tile R42C47:PLC2
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arc: N3_V06N0203 S1_V02N0701
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arc: S1_V02S0401 N3_V06S0203
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arc: S1_V02S0501 H02W0501
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arc: S1_V02S0601 H02E0601
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.tile R42C48:PLC2
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arc: N3_V06N0103 S1_V02N0101
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0203 N3_V06S0103
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arc: W1_H02W0501 N3_V06S0303
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.tile R42C49:PLC2
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arc: S1_V02S0201 N3_V06S0103
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arc: S3_V06S0003 N3_V06S0003
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.tile R42C51:PLC2
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arc: S3_V06S0203 N3_V06S0203
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.tile R42C52:PLC2
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arc: N3_V06N0003 S1_V02N0001
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.tile R42C73:PLC2
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arc: S1_V02S0401 N3_V06S0203
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0303 N3_V06S0303
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arc: V01S0100 N3_V06S0303
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.tile R42C74:PLC2
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arc: E1_H02E0701 N3_V06S0203
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arc: E3_H06E0103 N3_V06S0103
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arc: S1_V02S0201 N3_V06S0103
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arc: S1_V02S0701 N3_V06S0203
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0203 N3_V06S0103
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.tile R42C75:PLC2
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arc: S1_V02S0101 N3_V06S0103
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.tile R42C76:PLC2
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arc: E1_H02E0201 W1_H02E0701
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arc: S1_V02S0101 N3_V06S0103
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arc: S1_V02S0701 W1_H02E0701
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0203 N1_V01S0000
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.tile R42C77:PLC2
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arc: N3_V06N0203 S1_V02N0701
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arc: N3_V06N0303 S1_V02N0601
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arc: S1_V02S0201 H06E0103
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arc: S1_V02S0401 N3_V06S0203
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0103 H06E0103
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arc: S3_V06S0303 N3_V06S0303
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.tile R42C78:PLC2
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arc: N3_V06N0003 S1_V02N0301
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arc: N3_V06N0103 S1_V02N0201
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arc: N3_V06N0203 S1_V02N0401
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arc: N3_V06N0303 S1_V02N0501
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arc: S1_V02S0201 W1_H02E0201
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arc: S1_V02S0301 E1_H02W0301
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arc: S1_V02S0601 N1_V01S0000
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arc: S1_V02S0701 E1_H02W0701
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.tile R42C79:PLC2
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arc: N3_V06N0003 S1_V02N0001
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arc: S1_V02S0501 N3_V06S0303
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.tile R42C80:PLC2
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arc: W1_H02W0301 N3_V06S0003
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arc: W1_H02W0701 N3_V06S0203
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.tile R43C37:PLC2
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arc: S3_V06S0203 N3_V06S0103
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.tile R43C38:PLC2
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arc: S1_V02S0301 N3_V06S0003
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.tile R43C46:PLC2
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arc: S1_V02S0301 N3_V06S0003
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arc: S3_V06S0103 N1_V01S0100
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.tile R43C47:PLC2
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arc: S1_V02S0301 N3_V06S0003
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.tile R43C48:PLC2
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arc: S1_V02S0101 N1_V02S0001
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arc: S1_V02S0501 N1_V02S0401
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.tile R43C49:PLC2
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arc: S1_V02S0301 N3_V06S0003
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arc: S1_V02S0501 N3_V06S0303
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arc: S3_V06S0103 N3_V06S0003
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.tile R43C50:PLC2
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arc: S1_V02S0001 N3_V06S0003
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arc: S1_V02S0301 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0003
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.tile R43C73:PLC2
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arc: S1_V02S0101 N1_V02S0001
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arc: S1_V02S0301 N3_V06S0003
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arc: S1_V02S0701 N3_V06S0203
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arc: S3_V06S0003 N3_V06S0303
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arc: S3_V06S0103 N1_V01S0100
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arc: V01S0000 N3_V06S0103
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.tile R43C75:PLC2
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arc: S1_V02S0001 N3_V06S0003
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arc: S3_V06S0303 N3_V06S0203
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.tile R43C76:PLC2
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arc: S1_V02S0501 N3_V06S0303
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.tile R43C78:PLC2
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arc: S1_V02S0201 N3_V06S0103
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arc: S1_V02S0401 N3_V06S0203
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N1_V02S0201
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arc: V01S0000 N3_V06S0103
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.tile R43C79:PLC2
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arc: S1_V02S0401 N3_V06S0203
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arc: S3_V06S0203 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile R43C80:PLC2
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arc: S1_V02S0401 N3_V06S0203
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arc: S1_V02S0701 N3_V06S0203
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.tile R44C35:PLC2
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arc: E1_H02E0601 S1_V02N0601
|
|
|
|
.tile R44C36:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: M0 H02E0601
|
|
arc: MUXCLK0 CLK0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C37:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
|
|
.tile R44C38:PLC2
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile R44C39:PLC2
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06E0203
|
|
|
|
.tile R44C42:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R44C43:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R44C45:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
|
|
.tile R44C46:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C47:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0601
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: A0 N1_V02S0501
|
|
arc: A2 V00T0000
|
|
arc: A3 V02N0701
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 V02N0301
|
|
arc: A6 H00R0000
|
|
arc: A7 W1_H02E0501
|
|
arc: B2 H02W0101
|
|
arc: B3 V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B5 V02N0501
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 V00B0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C48:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0100
|
|
arc: A2 V02N0701
|
|
arc: A3 V02S0501
|
|
arc: A4 V02N0101
|
|
arc: A5 V00T0000
|
|
arc: A6 V00T0100
|
|
arc: A7 V02S0101
|
|
arc: B0 V00B0000
|
|
arc: B1 V02N0301
|
|
arc: B2 H00R0100
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 H00R0000
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C49:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0103 Q2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C50:PLC2
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: W1_H02W0301 V02N0301
|
|
|
|
.tile R44C51:PLC2
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 H06E0303
|
|
|
|
.tile R44C52:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R44C72:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V06S0003
|
|
|
|
.tile R44C73:PLC2
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C74:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0601 Q6
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C75:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R44C76:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R44C77:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: V00T0000 H02W0201
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 V01N0101
|
|
arc: A4 H02W0701
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 H02E0701
|
|
arc: B0 V00T0000
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02N0501
|
|
arc: B7 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C78:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 H00L0000
|
|
arc: A1 H00R0000
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 V00B0000
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 V00T0000
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 V02N0301
|
|
arc: B0 H02E0301
|
|
arc: B1 V02N0101
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0501
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q7
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C79:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 V02N0501
|
|
arc: A1 H00R0000
|
|
arc: A2 V00T0000
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C80:PLC2
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R45C35:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
|
|
.tile R45C36:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 V02N0501
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 H02W0601
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0100 Q3
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C37:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: M1 W1_H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C38:PLC2
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
|
|
.tile R45C42:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R45C43:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R45C45:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
|
|
.tile R45C46:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 V02N0701
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 H02W0401
|
|
arc: M5 H00L0000
|
|
arc: M6 E1_H02W0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C47:PLC2
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 V02N0701
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H01E0101 Q1
|
|
arc: E3_H06E0003 Q3
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M6 H02E0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0601 Q4
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C48:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0501 Q5
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C49:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M6 E1_H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0203 Q7
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C50:PLC2
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
|
|
.tile R45C51:PLC2
|
|
arc: W1_H02W0401 V06S0203
|
|
|
|
.tile R45C52:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R45C72:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
|
|
.tile R45C73:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0100 H02W0701
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q6
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C74:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 H02E0601
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H02W0001
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C75:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: E3_H06E0203 Q4
|
|
arc: M1 H00R0100
|
|
arc: M4 H02W0401
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0103 Q1
|
|
arc: V01S0000 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C76:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0401 V06S0203
|
|
|
|
.tile R45C77:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: CE0 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 E1_H02W0601
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0701 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C78:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q3
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H02W0001
|
|
arc: M6 H02W0401
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: V01S0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C79:PLC2
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
|
|
.tile R45C80:PLC2
|
|
arc: N1_V02N0101 H06W0103
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: W1_H02W0201 V02N0201
|
|
|
|
.tile R45C83:PLC2
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R45C84:PLC2
|
|
arc: H01W0100 W3_H06E0303
|
|
|
|
.tile R47C18:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R47C34:PLC2
|
|
arc: E1_H02E0601 V02S0601
|
|
|
|
.tile R47C36:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C37:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: W1_H02W0001 V02S0001
|
|
|
|
.tile R47C38:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
|
|
.tile R47C39:PLC2
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
|
|
.tile R47C40:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
|
|
.tile R47C42:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R47C45:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
|
|
.tile R47C46:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: V00B0000 V02S0201
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: M2 V00B0000
|
|
arc: M4 H02W0401
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C47:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H02W0001
|
|
arc: M3 H00R0100
|
|
arc: M4 H02E0401
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0701 Q5
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C48:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: W1_H02W0001 V02S0001
|
|
|
|
.tile R47C49:PLC2
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
|
|
.tile R47C52:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R47C71:PLC2
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
|
|
.tile R47C72:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
|
|
.tile R47C73:PLC2
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02S0401
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0203 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C74:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 V00B0100
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0701 Q7
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C75:PLC2
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 V02S0401
|
|
|
|
.tile R47C76:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile R47C77:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H06E0203
|
|
|
|
.tile R47C78:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02S0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: H01W0000 Q4
|
|
arc: M0 H02W0601
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00B0000
|
|
arc: M6 V00T0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: V01S0100 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C79:PLC2
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0601 V02S0601
|
|
|
|
.tile R47C80:PLC2
|
|
arc: H01W0100 W3_H06E0303
|
|
|
|
.tile R48C36:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
|
|
.tile R48C37:PLC2
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R48C39:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
|
|
.tile R48C48:PLC2
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
|
|
.tile R48C49:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
|
|
.tile R48C74:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
|
|
.tile R48C77:PLC2
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R48C78:PLC2
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 H02E0601
|
|
|
|
.tile R49C78:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
|
|
.tile R4C30:PLC2
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R4C72:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
|
|
.tile R4C77:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R50C36:PLC2
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
|
|
.tile R51C78:PLC2
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0701 V01N0101
|
|
|
|
.tile R52C27:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R52C33:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R52C36:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R52C42:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R52C45:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R52C48:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R52C51:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R52C54:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R52C57:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R52C60:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R52C63:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R52C66:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R52C69:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R52C72:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R52C75:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R52C78:PLC2
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R52C81:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R52C84:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R52C87:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R53C18:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R59C18:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R64C27:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R64C33:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R64C36:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R64C42:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R64C45:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R64C48:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R64C51:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R64C54:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R64C57:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R64C60:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R64C63:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R64C66:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R64C69:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R64C72:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R64C75:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R64C78:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R64C81:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R64C84:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R64C87:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R65C18:PLC2
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R66C18:PLC2
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
|
|
.tile R68C18:PLC2
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
|
|
.tile R6C30:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R6C72:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
|
|
.tile R7C71:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C72:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R7C75:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile TAP_R11C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R12C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R13C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R14C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R15C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R16C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R17C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R18C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R19C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R19C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R31C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R32C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R33C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R33C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R36C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R36C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R44C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R44C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R44C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R45C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R45C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R45C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R47C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R47C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R47C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C78:MIB_DSP0 MIB_R22C78:MIB2_DSP0 MIB_R22C79:MIB_DSP1 MIB_R22C79:MIB2_DSP1 MIB_R22C80:MIB_DSP2 MIB_R22C80:MIB2_DSP2 MIB_R22C81:MIB_DSP3 MIB_R22C81:MIB2_DSP3 MIB_R22C82:MIB_DSP4 MIB_R22C82:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 MIB_R22C74:MIB_DSP5 MIB_R22C74:MIB2_DSP5 MIB_R22C75:MIB_DSP6 MIB_R22C75:MIB2_DSP6 MIB_R22C76:MIB_DSP7 MIB_R22C76:MIB2_DSP7 MIB_R22C77:MIB_DSP8 MIB_R22C77:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4 MIB_R22C56:MIB_DSP5 MIB_R22C56:MIB2_DSP5 MIB_R22C57:MIB_DSP6 MIB_R22C57:MIB2_DSP6 MIB_R22C58:MIB_DSP7 MIB_R22C58:MIB2_DSP7 MIB_R22C59:MIB_DSP8 MIB_R22C59:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C73:MIB_DSP4 MIB_R46C73:MIB2_DSP4 MIB_R46C74:MIB_DSP5 MIB_R46C74:MIB2_DSP5 MIB_R46C75:MIB_DSP6 MIB_R46C75:MIB2_DSP6 MIB_R46C76:MIB_DSP7 MIB_R46C76:MIB2_DSP7 MIB_R46C77:MIB_DSP8 MIB_R46C77:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 MIB_R22C74:MIB_DSP5 MIB_R22C74:MIB2_DSP5 MIB_R22C75:MIB_DSP6 MIB_R22C75:MIB2_DSP6 MIB_R22C76:MIB_DSP7 MIB_R22C76:MIB2_DSP7 MIB_R22C77:MIB_DSP8 MIB_R22C77:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C78:MIB_DSP0 MIB_R46C78:MIB2_DSP0 MIB_R46C79:MIB_DSP1 MIB_R46C79:MIB2_DSP1 MIB_R46C80:MIB_DSP2 MIB_R46C80:MIB2_DSP2 MIB_R46C81:MIB_DSP3 MIB_R46C81:MIB2_DSP3 MIB_R46C82:MIB_DSP4 MIB_R46C82:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 MIB_R22C27:MIB_DSP5 MIB_R22C27:MIB2_DSP5 MIB_R22C28:MIB_DSP6 MIB_R22C28:MIB2_DSP6 MIB_R22C29:MIB_DSP7 MIB_R22C29:MIB2_DSP7 MIB_R22C30:MIB_DSP8 MIB_R22C30:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C69:MIB_DSP0 MIB_R22C69:MIB2_DSP0 MIB_R22C70:MIB_DSP1 MIB_R22C70:MIB2_DSP1 MIB_R22C71:MIB_DSP2 MIB_R22C71:MIB2_DSP2 MIB_R22C72:MIB_DSP3 MIB_R22C72:MIB2_DSP3 MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C60:MIB_DSP0 MIB_R22C60:MIB2_DSP0 MIB_R22C61:MIB_DSP1 MIB_R22C61:MIB2_DSP1 MIB_R22C62:MIB_DSP2 MIB_R22C62:MIB2_DSP2 MIB_R22C63:MIB_DSP3 MIB_R22C63:MIB2_DSP3 MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C69:MIB_DSP0 MIB_R22C69:MIB2_DSP0 MIB_R22C70:MIB_DSP1 MIB_R22C70:MIB2_DSP1 MIB_R22C71:MIB_DSP2 MIB_R22C71:MIB2_DSP2 MIB_R22C72:MIB_DSP3 MIB_R22C72:MIB2_DSP3 MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 MIB_R22C27:MIB_DSP5 MIB_R22C27:MIB2_DSP5 MIB_R22C28:MIB_DSP6 MIB_R22C28:MIB2_DSP6 MIB_R22C29:MIB_DSP7 MIB_R22C29:MIB2_DSP7 MIB_R22C30:MIB_DSP8 MIB_R22C30:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C31:MIB_DSP0 MIB_R22C31:MIB2_DSP0 MIB_R22C32:MIB_DSP1 MIB_R22C32:MIB2_DSP1 MIB_R22C33:MIB_DSP2 MIB_R22C33:MIB2_DSP2 MIB_R22C34:MIB_DSP3 MIB_R22C34:MIB2_DSP3 MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C73:MIB_DSP4 MIB_R46C73:MIB2_DSP4 MIB_R46C74:MIB_DSP5 MIB_R46C74:MIB2_DSP5 MIB_R46C75:MIB_DSP6 MIB_R46C75:MIB2_DSP6 MIB_R46C76:MIB_DSP7 MIB_R46C76:MIB2_DSP7 MIB_R46C77:MIB_DSP8 MIB_R46C77:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C31:MIB_DSP0 MIB_R22C31:MIB2_DSP0 MIB_R22C32:MIB_DSP1 MIB_R22C32:MIB2_DSP1 MIB_R22C33:MIB_DSP2 MIB_R22C33:MIB2_DSP2 MIB_R22C34:MIB_DSP3 MIB_R22C34:MIB2_DSP3 MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C51:MIB_DSP0 MIB_R22C51:MIB2_DSP0 MIB_R22C52:MIB_DSP1 MIB_R22C52:MIB2_DSP1 MIB_R22C53:MIB_DSP2 MIB_R22C53:MIB2_DSP2 MIB_R22C54:MIB_DSP3 MIB_R22C54:MIB2_DSP3 MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 MIB_R22C36:MIB_DSP5 MIB_R22C36:MIB2_DSP5 MIB_R22C37:MIB_DSP6 MIB_R22C37:MIB2_DSP6 MIB_R22C38:MIB_DSP7 MIB_R22C38:MIB2_DSP7 MIB_R22C39:MIB_DSP8 MIB_R22C39:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 MIB_R22C36:MIB_DSP5 MIB_R22C36:MIB2_DSP5 MIB_R22C37:MIB_DSP6 MIB_R22C37:MIB2_DSP6 MIB_R22C38:MIB_DSP7 MIB_R22C38:MIB2_DSP7 MIB_R22C39:MIB_DSP8 MIB_R22C39:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C60:MIB_DSP0 MIB_R22C60:MIB2_DSP0 MIB_R22C61:MIB_DSP1 MIB_R22C61:MIB2_DSP1 MIB_R22C62:MIB_DSP2 MIB_R22C62:MIB2_DSP2 MIB_R22C63:MIB_DSP3 MIB_R22C63:MIB2_DSP3 MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C42:MIB_DSP0 MIB_R22C42:MIB2_DSP0 MIB_R22C43:MIB_DSP1 MIB_R22C43:MIB2_DSP1 MIB_R22C44:MIB_DSP2 MIB_R22C44:MIB2_DSP2 MIB_R22C45:MIB_DSP3 MIB_R22C45:MIB2_DSP3 MIB_R22C46:MIB_DSP4 MIB_R22C46:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C51:MIB_DSP0 MIB_R22C51:MIB2_DSP0 MIB_R22C52:MIB_DSP1 MIB_R22C52:MIB2_DSP1 MIB_R22C53:MIB_DSP2 MIB_R22C53:MIB2_DSP2 MIB_R22C54:MIB_DSP3 MIB_R22C54:MIB2_DSP3 MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C46:MIB_DSP4 MIB_R46C46:MIB2_DSP4 MIB_R46C47:MIB_DSP5 MIB_R46C47:MIB2_DSP5 MIB_R46C48:MIB_DSP6 MIB_R46C48:MIB2_DSP6 MIB_R46C49:MIB_DSP7 MIB_R46C49:MIB2_DSP7 MIB_R46C50:MIB_DSP8 MIB_R46C50:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C35:MIB_DSP4 MIB_R46C35:MIB2_DSP4 MIB_R46C36:MIB_DSP5 MIB_R46C36:MIB2_DSP5 MIB_R46C37:MIB_DSP6 MIB_R46C37:MIB2_DSP6 MIB_R46C38:MIB_DSP7 MIB_R46C38:MIB2_DSP7 MIB_R46C39:MIB_DSP8 MIB_R46C39:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C82:MIB_DSP4 MIB_R22C82:MIB2_DSP4 MIB_R22C83:MIB_DSP5 MIB_R22C83:MIB2_DSP5 MIB_R22C84:MIB_DSP6 MIB_R22C84:MIB2_DSP6 MIB_R22C85:MIB_DSP7 MIB_R22C85:MIB2_DSP7 MIB_R22C86:MIB_DSP8 MIB_R22C86:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C46:MIB_DSP4 MIB_R46C46:MIB2_DSP4 MIB_R46C47:MIB_DSP5 MIB_R46C47:MIB2_DSP5 MIB_R46C48:MIB_DSP6 MIB_R46C48:MIB2_DSP6 MIB_R46C49:MIB_DSP7 MIB_R46C49:MIB2_DSP7 MIB_R46C50:MIB_DSP8 MIB_R46C50:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C46:MIB_DSP4 MIB_R22C46:MIB2_DSP4 MIB_R22C47:MIB_DSP5 MIB_R22C47:MIB2_DSP5 MIB_R22C48:MIB_DSP6 MIB_R22C48:MIB2_DSP6 MIB_R22C49:MIB_DSP7 MIB_R22C49:MIB2_DSP7 MIB_R22C50:MIB_DSP8 MIB_R22C50:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C46:MIB_DSP4 MIB_R22C46:MIB2_DSP4 MIB_R22C47:MIB_DSP5 MIB_R22C47:MIB2_DSP5 MIB_R22C48:MIB_DSP6 MIB_R22C48:MIB2_DSP6 MIB_R22C49:MIB_DSP7 MIB_R22C49:MIB2_DSP7 MIB_R22C50:MIB_DSP8 MIB_R22C50:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C82:MIB_DSP4 MIB_R22C82:MIB2_DSP4 MIB_R22C83:MIB_DSP5 MIB_R22C83:MIB2_DSP5 MIB_R22C84:MIB_DSP6 MIB_R22C84:MIB2_DSP6 MIB_R22C85:MIB_DSP7 MIB_R22C85:MIB2_DSP7 MIB_R22C86:MIB_DSP8 MIB_R22C86:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C78:MIB_DSP0 MIB_R22C78:MIB2_DSP0 MIB_R22C79:MIB_DSP1 MIB_R22C79:MIB2_DSP1 MIB_R22C80:MIB_DSP2 MIB_R22C80:MIB2_DSP2 MIB_R22C81:MIB_DSP3 MIB_R22C81:MIB2_DSP3 MIB_R22C82:MIB_DSP4 MIB_R22C82:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4 MIB_R22C56:MIB_DSP5 MIB_R22C56:MIB2_DSP5 MIB_R22C57:MIB_DSP6 MIB_R22C57:MIB2_DSP6 MIB_R22C58:MIB_DSP7 MIB_R22C58:MIB2_DSP7 MIB_R22C59:MIB_DSP8 MIB_R22C59:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C42:MIB_DSP0 MIB_R22C42:MIB2_DSP0 MIB_R22C43:MIB_DSP1 MIB_R22C43:MIB2_DSP1 MIB_R22C44:MIB_DSP2 MIB_R22C44:MIB2_DSP2 MIB_R22C45:MIB_DSP3 MIB_R22C45:MIB2_DSP3 MIB_R22C46:MIB_DSP4 MIB_R22C46:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|