83 lines
1.8 KiB
Verilog
83 lines
1.8 KiB
Verilog
module layer #(
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parameter DATA_WIDTH = 16,
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parameter FRAC_BITS = 8,
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parameter N_INPUTS = 64,
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parameter N_NEURONS = 8,
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parameter PARALLEL = 8,
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parameter ACC_WIDTH = 40
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)(
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input clk,
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input rst,
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input start,
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input signed [DATA_WIDTH*N_INPUTS-1:0] x_bus,
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input signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0]
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weights_bus,
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input signed [DATA_WIDTH*N_NEURONS-1:0]
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bias_bus,
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output signed [DATA_WIDTH*N_NEURONS-1:0]
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y_bus,
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output busy,
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output done
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);
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wire [N_NEURONS-1:0] neuron_busy;
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wire [N_NEURONS-1:0] neuron_done;
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genvar n;
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generate
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for (n = 0; n < N_NEURONS; n = n + 1) begin : GEN_NEURON
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neuron_parallel #(
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.DATA_WIDTH(DATA_WIDTH),
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.FRAC_BITS(FRAC_BITS),
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.N_INPUTS(N_INPUTS),
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.PARALLEL(PARALLEL),
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.ACC_WIDTH(ACC_WIDTH)
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) u_neuron (
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.clk(clk),
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.rst(rst),
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.start(start),
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.x_bus(x_bus),
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.w_bus(
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weights_bus[
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n*N_INPUTS*DATA_WIDTH
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+: N_INPUTS*DATA_WIDTH
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]
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),
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.bias(
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bias_bus[
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n*DATA_WIDTH
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+: DATA_WIDTH
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]
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),
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.y(
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y_bus[
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n*DATA_WIDTH
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+: DATA_WIDTH
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]
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),
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.busy(neuron_busy[n]),
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.done(neuron_done[n])
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);
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end
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endgenerate
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assign busy = |neuron_busy;
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assign done = &neuron_done;
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endmodule |