micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
1.3 KiB
1.3 KiB
| 1 | configuration,n_slots,pfd,cycles,cycles_per_tile_steady_state,sustained_mac_per_cycle,utilization_pct_theoretical,fmax_mhz,lut4,ccu2c,ff,dsp,bram,classification |
|---|---|
| 2 | current_nms_pf_baseline,2,8,185398,4.0,0.1767,1.10,95.25,1908,362,3449,16,0,POST-P&R MEASURED + RTL SIMULATION (EXP-0024) |
| 3 | isolated_trace_old_design_zero_latency,1,16,81,4.0,n/a,25.0,n/a,n/a,n/a,n/a,n/a,n/a,RTL SIMULATION isolated (EXP-0025) -- 4 cycles/tile hard floor, independent of memory latency |
| 4 | isolated_trace_new_design_zero_latency_real_wpf,1,16,80,4.0,n/a,25.0,n/a,n/a,n/a,n/a,n/a,n/a,RTL SIMULATION isolated (EXP-0026) -- fix works but masked by weight-fetch word-rate (co-dominant 4 cyc/tile) |
| 5 | isolated_trace_new_design_weightfetch_bypassed,1,16,30,1.0,n/a,100.0,n/a,n/a,n/a,n/a,n/a,n/a,RTL SIMULATION isolated scratch (EXP-0027) -- k->infinity endpoint: PROVES 4x ceiling removed once weight-fetch is not the limiter |
| 6 | nms_stream_real_dstress,1,8,n/a,n/a,n/a,n/a,142.92,1433,206,2250,8,0,POST-P&R MEASURED (EXP-0028) |
| 7 | nms_stream_real_dstress,2,8,185270,4.0,0.1769,1.11,92.57,2014,371,3459,16,0,POST-P&R MEASURED + RTL SIMULATION bit-exact PASS 256/256 (EXP-0028) |
| 8 | nms_stream_real_dstress,4,8,n/a,n/a,n/a,n/a,55.22,2937,705,5877,32,0,POST-P&R MEASURED -- FAILS 80MHz target (EXP-0028 N=4 check; same pre-existing nms_activation_fill_ctrl.v priority-scan regression as EXP-0022, unrelated to this STEP's own fix) |