tools/fpga_benchmark.py: parametric Yosys + nextpnr-ecp5 benchmark harness for the LFE5U-45F-8BG381 (speed grade -8, 80 MHz target), sweeping PARALLEL over the neuron layer and parsing Fmax/LUT4/DFF/DSP utilization out of the nextpnr report into JSON/CSV. synth/ecp5/p2, p4, p8: real synthesis+PnR results backing the same-price-tier FPGA comparison (P2: 87.88 MHz PASS, P4: 75.01 MHz FAIL, P8: 147.62 MHz PASS -- non-monotonic, dominated by placement noise since the whole design uses <2% of the device's LUT4 fabric at every setting, and P8 notably maps to 0 DSP blocks vs 8/16 for P2/P4). synth/ecp5/top.v: benchmark harness top-level, reworked to generate deterministic non-constant X/weights/bias via `keep`-attributed generate blocks so Yosys can't constant-fold the datapath away. Also adds .gitignore for Python's __pycache__/*.pyc.
15758 lines
353 KiB
Plaintext
15758 lines
353 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R13C1:CIB_LR
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arc: E3_H06E0303 JQ5
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.tile CIB_R19C1:CIB_LR
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arc: S1_V02S0501 E3_H06W0303
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.tile CIB_R1C36:CIB
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arc: JA0 E1_H02W0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C37:CIB
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arc: E3_H06E0303 S3_V06N0303
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arc: JA0 H02W0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C38:CIB
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arc: JA0 S1_V02N0501
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arc: W1_H02W0501 S3_V06N0303
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arc: W1_H02W0701 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C39:CIB
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arc: JA0 V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C41:CIB
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arc: E1_H02E0501 S1_V02N0501
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.tile CIB_R1C42:CIB
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C43:CIB
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arc: E3_H06E0303 W3_H06E0303
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arc: H00R0000 S1_V02N0601
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arc: JA0 H00R0000
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enum: CIB.JB0MUX 0
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.tile CIB_R1C44:CIB
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arc: E1_H02E0501 S3_V06N0303
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arc: JA0 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C45:CIB
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C47:CIB
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arc: JA0 S1_V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C48:CIB
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arc: JD7 E1_H01W0100
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.tile CIB_R1C49:CIB
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arc: H01W0100 W3_H06E0303
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.tile CIB_R1C53:CIB
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arc: E1_H02E0501 V06N0303
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.tile CIB_R1C54:CIB
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C65:CIB
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arc: E1_H02E0701 V06N0203
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.tile CIB_R1C66:CIB
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C69:CIB
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arc: E1_H02E0701 V06N0203
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arc: H00L0100 S1_V02N0101
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arc: JA0 H00L0100
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enum: CIB.JB0MUX 0
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.tile CIB_R1C70:CIB
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C72:CIB
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arc: JA0 S1_V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R20C1:CIB_LR
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arc: E1_H01E0001 E3_H06W0003
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arc: JA0 V02S0501
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arc: JA3 E1_H01E0001
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arc: S1_V02S0501 E3_H06W0303
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arc: S1_V02S0701 H06W0203
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R20C89:CIB_LR
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arc: JA0 W1_H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R22C1:CIB_LR_S
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arc: JA0 N1_V02S0701
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arc: JA3 N1_V02S0501
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enum: CIB.JB3MUX 0
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enum: CIB.JB0MUX 0
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.tile CIB_R22C22:CIB_DSP
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arc: E3_H06E0003 JQ0
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arc: E3_H06E0103 JQ1
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arc: E3_H06E0203 JQ4
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arc: E3_H06E0303 JQ6
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arc: N1_V02N0201 JQ2
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arc: N1_V02N0301 JQ3
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arc: N1_V02N0501 JQ5
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arc: N1_V02N0701 JQ7
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JA2MUX 0
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enum: CIB.JC3MUX 0
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enum: CIB.JA0MUX 0
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.tile CIB_R22C23:CIB_DSP
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arc: E1_H02E0301 E3_H06W0003
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arc: E3_H06E0003 JQ0
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arc: E3_H06E0103 JQ1
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arc: E3_H06E0203 JQ4
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arc: E3_H06E0303 JQ5
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arc: N1_V01N0101 JQ2
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arc: N1_V02N0101 JQ3
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arc: N1_V02N0601 JQ6
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arc: N1_V02N0701 JQ7
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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.tile CIB_R22C24:CIB_DSP
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arc: H00R0000 V02N0601
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arc: JD3 H00R0000
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arc: JLSR0 H02E0301
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arc: JLSR1 H02E0301
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arc: N1_V02N0301 H02E0301
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD6MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JD2MUX 1
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.tile CIB_R22C25:CIB_DSP
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD6MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD4MUX 0
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.tile CIB_R22C26:CIB_DSP
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arc: E1_H01E0001 JF7
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arc: E1_H01E0101 JF6
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arc: E3_H06E0203 JF4
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arc: E3_H06E0303 JQ5
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arc: H00R0100 E1_H02W0501
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arc: JCE0 H00R0100
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arc: JCE1 H00R0100
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arc: JCE2 H00R0100
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arc: JCE3 H00R0100
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arc: JD5 V02N0601
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arc: N1_V01N0001 JF5
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arc: N1_V01N0101 JQ4
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arc: N1_V02N0401 JQ6
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arc: N1_V02N0501 JQ7
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD6MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD4MUX 1
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JD0MUX 0
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.tile CIB_R22C27:CIB_DSP
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arc: E1_H01E0001 JF2
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arc: E1_H01E0101 JF4
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arc: E1_H02E0001 JQ0
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arc: E1_H02E0301 JQ1
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arc: E3_H06E0003 JQ3
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arc: E3_H06E0103 JQ2
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arc: E3_H06E0203 JF7
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arc: E3_H06E0303 JQ6
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arc: N1_V01N0001 JQ4
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arc: N1_V01N0101 JQ5
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arc: N1_V02N0001 JF0
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arc: N1_V02N0101 JF3
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arc: N1_V02N0301 JF1
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arc: N1_V02N0401 H01E0001
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arc: N1_V02N0501 JQ7
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arc: N1_V02N0601 JF6
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arc: N1_V02N0701 H01E0101
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arc: S1_V02S0501 JF5
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD6MUX 0
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JA2MUX 0
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enum: CIB.JC3MUX 0
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enum: CIB.JA0MUX 0
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.tile CIB_R22C28:CIB_DSP
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arc: E1_H01E0001 JF1
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arc: E1_H01E0101 JF2
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arc: E1_H02E0301 JQ3
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arc: E1_H02E0401 W3_H06E0203
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arc: E1_H02E0501 S1_V02N0501
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arc: E3_H06E0103 W3_H06E0003
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arc: E3_H06E0203 W3_H06E0103
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arc: E3_H06E0303 W3_H06E0303
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arc: JD7 V02N0601
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arc: JLSR0 H02W0301
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arc: JLSR1 H02W0301
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arc: N1_V01N0001 JQ1
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arc: N1_V01N0101 JQ0
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arc: N1_V02N0001 JQ2
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arc: N1_V02N0201 JF0
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arc: N1_V02N0301 JF3
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arc: N1_V02N0401 H01E0001
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arc: N1_V02N0701 H01E0101
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arc: W1_H02W0501 S1_V02N0501
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JB6MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD6MUX 1
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.tile CIB_R22C29:CIB_DSP
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arc: E1_H02E0301 E3_H06W0003
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arc: E1_H02E0501 H01E0101
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arc: E3_H06E0003 W3_H06E0303
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arc: E3_H06E0103 W3_H06E0003
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arc: E3_H06E0203 W3_H06E0103
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arc: E3_H06E0303 W3_H06E0203
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arc: JLSR1 H02E0501
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arc: N1_V02N0001 W1_H02E0001
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arc: N1_V02N0101 E1_H02W0101
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arc: N1_V02N0201 H01E0001
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arc: N1_V02N0301 W1_H02E0301
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arc: W1_H02W0301 E3_H06W0003
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arc: W3_H06W0003 E3_H06W0003
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD6MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JD0MUX 0
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.tile CIB_R22C30:CIB_DSP
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arc: E1_H02E0501 W1_H02E0401
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arc: E3_H06E0003 W1_H02E0301
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arc: H00R0100 W1_H02E0501
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arc: JCE3 H00R0100
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arc: JLSR0 H02E0301
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arc: JLSR1 H02E0301
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arc: N1_V02N0101 H06E0103
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arc: N1_V02N0301 H06E0003
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
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enum: CIB.JD1MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD6MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JD0MUX 0
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.tile CIB_R22C31:CIB_DSP
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arc: E1_H01E0001 JF7
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arc: E1_H01E0101 JF6
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arc: E1_H02E0201 JQ2
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arc: E1_H02E0301 JQ3
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arc: E1_H02E0401 JQ6
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arc: E1_H02E0501 W1_H02E0501
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arc: E3_H06E0003 JQ0
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arc: E3_H06E0103 JQ1
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arc: E3_H06E0203 JQ7
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arc: E3_H06E0303 JQ5
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arc: H00R0000 V02N0401
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arc: H00R0100 H02W0501
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arc: JCE0 H00R0100
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arc: JD1 H00R0000
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arc: JLSR0 W1_H02E0301
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arc: JLSR1 W1_H02E0301
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arc: N1_V01N0001 JQ4
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arc: N1_V01N0101 JF5
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arc: N1_V02N0001 JF0
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arc: N1_V02N0101 H06E0103
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arc: N1_V02N0201 JF2
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arc: N1_V02N0301 JF3
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arc: N1_V02N0401 H06E0203
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arc: N1_V02N0501 H02E0501
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arc: N1_V02N0601 JF4
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arc: N1_V02N0701 H02W0701
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arc: W1_H02W0101 JF1
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enum: CIB.JA3MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JA1MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JB6MUX 0
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enum: CIB.JD7MUX 0
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enum: CIB.JB4MUX 0
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enum: CIB.JD5MUX 0
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enum: CIB.JB2MUX 0
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enum: CIB.JD3MUX 0
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enum: CIB.JB0MUX 0
|
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enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 1
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C32:CIB_DSP
|
|
arc: E1_H01E0001 JF7
|
|
arc: E1_H01E0101 JF6
|
|
arc: E1_H02E0001 JQ0
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0601 JQ6
|
|
arc: E1_H02E0701 JQ7
|
|
arc: E3_H06E0003 JQ3
|
|
arc: E3_H06E0103 JQ2
|
|
arc: E3_H06E0203 JQ4
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: N1_V01N0001 JQ1
|
|
arc: N1_V01N0101 JF3
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 JF2
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0103 JF1
|
|
arc: N3_V06N0303 JF5
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C33:CIB_DSP
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: JD5 E1_H02W0001
|
|
arc: JLSR0 E1_H02W0301
|
|
arc: JLSR1 E1_H02W0301
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 1
|
|
|
|
.tile CIB_R22C34:CIB_DSP
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E3_H06E0003 W1_H02E0001
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
|
|
.tile CIB_R22C35:CIB_DSP
|
|
arc: E1_H01E0001 JF4
|
|
arc: E1_H01E0101 JF6
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0303 JQ6
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H01W0100 JQ4
|
|
arc: JCE0 H00R0000
|
|
arc: JCE1 H00R0000
|
|
arc: JCE2 S1_V02N0601
|
|
arc: JCE3 S1_V02N0601
|
|
arc: JD7 E1_H02W0001
|
|
arc: N1_V01N0001 JQ7
|
|
arc: N1_V01N0101 JQ5
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0501 JF7
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0701 JF5
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 1
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C36:CIB_DSP
|
|
arc: E1_H01E0001 JF4
|
|
arc: E1_H01E0101 JF2
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 JQ7
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0303 JQ6
|
|
arc: H01W0000 JQ2
|
|
arc: H01W0100 JQ3
|
|
arc: N1_V01N0001 JQ5
|
|
arc: N1_V01N0101 JQ4
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 JF1
|
|
arc: N1_V02N0201 JQ0
|
|
arc: N1_V02N0301 JF3
|
|
arc: N1_V02N0501 JF7
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0303 JF6
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 JF5
|
|
arc: V01S0100 JQ1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C37:CIB_DSP
|
|
arc: E1_H01E0001 JF3
|
|
arc: E1_H01E0101 JF2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 JQ3
|
|
arc: E1_H02E0301 JQ3
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: JLSR0 E1_H02W0301
|
|
arc: JLSR1 E1_H02W0301
|
|
arc: N1_V01N0101 JQ2
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0101 JF1
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V01S0100 JQ0
|
|
arc: W1_H02W0001 V02S0001
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 1
|
|
|
|
.tile CIB_R22C38:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: JD1 H02E0001
|
|
arc: JLSR1 H02W0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 W3_H06E0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C39:CIB_DSP
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: JCE3 H00R0100
|
|
arc: JLSR0 E1_H02W0301
|
|
arc: JLSR1 E1_H02W0301
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C40:CIB_DSP
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0501 H02W0501
|
|
|
|
.tile CIB_R22C41:CIB_DSP
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
|
|
.tile CIB_R22C42:CIB_DSP
|
|
arc: E1_H01E0001 JF2
|
|
arc: E1_H01E0101 JF6
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 JF7
|
|
arc: JCE0 H00R0100
|
|
arc: JD3 H02W0001
|
|
arc: JLSR0 H02E0301
|
|
arc: JLSR1 H02E0301
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 JF3
|
|
arc: N1_V02N0201 JF0
|
|
arc: N1_V02N0301 JF1
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 1
|
|
|
|
.tile CIB_R22C43:CIB_DSP
|
|
arc: E1_H01E0001 JF1
|
|
arc: E1_H01E0101 JF7
|
|
arc: H01W0000 JF6
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0101 JF3
|
|
arc: N1_V02N0001 JF2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 JF0
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0701 JF5
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0401 JF4
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R22C44:CIB_DSP
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C45:CIB_DSP
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
|
|
.tile CIB_R22C47:CIB_DSP
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile CIB_R22C50:CIB_DSP
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile CIB_R22C51:CIB_DSP
|
|
arc: E1_H01E0101 JQ5
|
|
arc: E1_H02E0501 JQ7
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 JQ1
|
|
arc: E3_H06E0203 JQ4
|
|
arc: N1_V01N0101 JQ3
|
|
arc: S1_V02S0001 JQ2
|
|
arc: S1_V02S0401 JQ6
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C52:CIB_DSP
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: E1_H02E0501 JQ7
|
|
arc: E1_H02E0601 JQ6
|
|
arc: E3_H06E0003 JQ3
|
|
arc: E3_H06E0103 JQ2
|
|
arc: E3_H06E0303 JQ5
|
|
arc: S1_V02S0101 JQ1
|
|
arc: S1_V02S0201 JQ0
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0601 JQ4
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C53:CIB_DSP
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: JLSR0 H02E0301
|
|
arc: JLSR1 H02E0301
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 1
|
|
|
|
.tile CIB_R22C54:CIB_DSP
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H06E0203
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
|
|
.tile CIB_R22C55:CIB_DSP
|
|
arc: E1_H01E0001 JQ6
|
|
arc: E1_H01E0101 JQ4
|
|
arc: E1_H02E0501 JQ7
|
|
arc: E3_H06E0303 JQ5
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: H01W0000 JF7
|
|
arc: H01W0100 JF6
|
|
arc: JCE0 H00R0100
|
|
arc: JCE1 H00R0100
|
|
arc: JCE2 H00R0100
|
|
arc: JCE3 H00R0100
|
|
arc: N1_V01N0101 JF5
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V01S0100 JF4
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 1
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C56:CIB_DSP
|
|
arc: E1_H01E0001 JQ5
|
|
arc: E1_H01E0101 JF6
|
|
arc: E1_H02E0101 JQ3
|
|
arc: E1_H02E0201 JQ2
|
|
arc: E1_H02E0301 JQ1
|
|
arc: E1_H02E0401 JQ4
|
|
arc: E1_H02E0701 JQ7
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 JQ6
|
|
arc: H01W0000 JF4
|
|
arc: H01W0100 JF2
|
|
arc: N1_V02N0701 JF7
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 JF3
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 JF5
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V01S0100 JF0
|
|
arc: W1_H02W0301 JF1
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R22C57:CIB_DSP
|
|
arc: E1_H01E0001 JQ2
|
|
arc: E1_H02E0101 JQ3
|
|
arc: E1_H02E0301 JQ1
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: H01W0000 JF2
|
|
arc: H01W0100 JF3
|
|
arc: JLSR0 E1_H02W0301
|
|
arc: JLSR1 E1_H02W0301
|
|
arc: S1_V02S0101 JF1
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V01S0100 JF0
|
|
arc: W1_H02W0701 H01E0101
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 1
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C58:CIB_DSP
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: JLSR1 V00T0000
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 H02E0301
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C59:CIB_DSP
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0000 H02E0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: JCE3 H00R0000
|
|
arc: JLSR0 V00B0000
|
|
arc: JLSR1 V00B0000
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 H02E0601
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C60:CIB_DSP
|
|
arc: E1_H01E0001 JF0
|
|
arc: E1_H01E0101 JF1
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H01W0000 JF4
|
|
arc: H01W0100 JF2
|
|
arc: JCE0 H00R0000
|
|
arc: JLSR0 H02E0301
|
|
arc: JLSR1 H02E0301
|
|
arc: N1_V01N0101 JF7
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 JF6
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V01S0100 JF5
|
|
arc: W1_H02W0101 JF3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 1
|
|
|
|
.tile CIB_R22C61:CIB_DSP
|
|
arc: E1_H01E0101 JF4
|
|
arc: H01W0000 JF0
|
|
arc: H01W0100 JF2
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0101 JF3
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 JF1
|
|
arc: S1_V02S0401 JF6
|
|
arc: S1_V02S0501 JF7
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0100 JF5
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0501 H01E0101
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JD7MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
enum: CIB.JB2MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R22C62:CIB_DSP
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0701 H01E0101
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JD1MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C63:CIB_DSP
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
|
|
.tile CIB_R22C64:CIB_DSP
|
|
arc: E1_H01E0101 JQ6
|
|
arc: E1_H02E0501 JQ7
|
|
arc: H01W0100 JQ4
|
|
arc: S1_V02S0101 E3_H06W0103
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0701 JQ5
|
|
|
|
.tile CIB_R22C65:CIB_DSP
|
|
arc: E1_H01E0001 JQ2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E1_H02E0401 JQ4
|
|
arc: E1_H02E0501 JQ5
|
|
arc: E1_H02E0701 JQ7
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H01W0100 JQ3
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 JQ1
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V01S0000 JQ0
|
|
arc: V01S0100 JQ6
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C66:CIB_DSP
|
|
arc: E1_H01E0101 JQ2
|
|
arc: E1_H02E0101 JQ3
|
|
arc: N1_V01N0101 JQ1
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V01S0000 JQ0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 1
|
|
|
|
.tile CIB_R22C67:CIB_DSP
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: JLSR1 V00T0100
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C68:CIB_DSP
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
arc: H00R0100 H02E0701
|
|
arc: JCE3 H00R0100
|
|
arc: JLSR0 H02E0301
|
|
arc: JLSR1 H02E0301
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C69:CIB_DSP
|
|
arc: E1_H01E0001 JF0
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0501 JQ7
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: H01W0000 JF4
|
|
arc: H01W0100 JF3
|
|
arc: JCE0 H00R0100
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V01N0001 JF7
|
|
arc: N1_V01N0101 JQ2
|
|
arc: N1_V02N0001 JF2
|
|
arc: N1_V02N0301 JF1
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0301 JQ1
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: S3_V06S0303 JQ6
|
|
arc: V00B0100 V02N0101
|
|
arc: V01S0000 JQ4
|
|
arc: V01S0100 JQ5
|
|
arc: W1_H02W0701 JF5
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 JF6
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 1
|
|
|
|
.tile CIB_R22C70:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: E1_H01E0101 JQ6
|
|
arc: H01W0000 JF0
|
|
arc: H01W0100 JF4
|
|
arc: JLSR1 V00T0000
|
|
arc: N1_V01N0001 JQ1
|
|
arc: N1_V01N0101 JQ2
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 JQ4
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V01S0000 JQ5
|
|
arc: V01S0100 JF3
|
|
arc: W1_H02W0301 JF1
|
|
arc: W1_H02W0701 JF5
|
|
arc: W3_H06W0103 JF2
|
|
arc: W3_H06W0203 JF7
|
|
arc: W3_H06W0303 JF6
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R22C71:CIB_DSP
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: JLSR0 W1_H02E0301
|
|
arc: JLSR1 W1_H02E0301
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 1
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C72:CIB_DSP
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
|
|
.tile CIB_R22C73:CIB_DSP
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H01W0000 JF7
|
|
arc: H01W0100 JF6
|
|
arc: JCE0 H00R0000
|
|
arc: JCE1 H00R0000
|
|
arc: JCE2 S1_V02N0601
|
|
arc: JCE3 S1_V02N0601
|
|
arc: S1_V02S0701 JF5
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 JF4
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 1
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C74:CIB_DSP
|
|
arc: H01W0000 JF7
|
|
arc: H01W0100 JF1
|
|
arc: N1_V02N0001 JF0
|
|
arc: S1_V02S0001 JF2
|
|
arc: S1_V02S0401 JF4
|
|
arc: S1_V02S0701 JF5
|
|
arc: W1_H02W0301 JF3
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 JF6
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB6MUX 1
|
|
enum: CIB.JD7MUX 1
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R22C75:CIB_DSP
|
|
arc: H01W0000 JF0
|
|
arc: H01W0100 JF3
|
|
arc: JLSR0 W1_H02E0301
|
|
arc: JLSR1 W1_H02E0301
|
|
arc: N1_V02N0101 JF1
|
|
arc: W1_H02W0201 JF2
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JB4MUX 1
|
|
enum: CIB.JD5MUX 1
|
|
enum: CIB.JB2MUX 1
|
|
enum: CIB.JD3MUX 1
|
|
enum: CIB.JB0MUX 1
|
|
enum: CIB.JD1MUX 1
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
|
|
.tile CIB_R22C76:CIB_DSP
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C77:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile CIB_R22C83:CIB_DSP
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R22C89:CIB_LR_S
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R23C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: JA0 E1_H02W0701
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: S1_V02S0701 E3_H06W0203
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R23C89:CIB_LR
|
|
arc: JA3 W1_H02E0701
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R25C1:CIB_LR
|
|
arc: JA0 N1_V02S0501
|
|
arc: JA3 N1_V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R25C89:CIB_LR
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
|
|
.tile CIB_R26C89:CIB_LR
|
|
arc: H00L0100 V02S0101
|
|
arc: JA0 V02S0701
|
|
arc: JA3 H00L0100
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R28C89:CIB_LR
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: JA0 H00L0100
|
|
arc: JA3 N1_V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R29C1:CIB_LR
|
|
arc: JA0 E1_H02W0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R29C89:CIB_LR
|
|
arc: JA0 W1_H02E0501
|
|
arc: JA3 H01E0001
|
|
arc: S1_V02S0501 H06E0303
|
|
enum: CIB.JB0MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R31C1:CIB_LR
|
|
arc: JA0 E1_H02W0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R31C89:CIB_LR
|
|
arc: JA0 N1_V02S0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R5C1:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R5C89:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C15:CIB
|
|
arc: JA0 N1_V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C18:CIB
|
|
arc: JA0 H02W0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C19:CIB
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile CIB_R70C3:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C42:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C43:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C45:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile MIB_R0C36:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C37:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C38:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C39:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C44:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C45:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C47:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C54:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C66:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C69:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C70:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C72:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C50:EBR_SPINE_UR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C77:EBR_SPINE_UR1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R12C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R13C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C36:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C37:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C38:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C39:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C44:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C45:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C47:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C54:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C66:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C69:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C70:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C72:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C90:PICR0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C0:PICL1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C90:PICR1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R22C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R22C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C90:PICR0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C0:PICL1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C90:PICR1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R25C0:PICL2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C90:PICR0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C90:PICR1_DQS0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C90:PICR2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C0:PICL0_DQS2
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C0:PICL1_DQS3
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C0:PICL2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R71C15:PICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile R11C38:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R11C41:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R11C43:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R11C47:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R12C39:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R12C53:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R12C65:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R12C69:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R13C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R13C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R13C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R13C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R13C37:PLC2
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R13C38:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R13C44:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R13C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R15C41:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R15C69:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R16C32:PLC2
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0501 S3_V06N0303
|
|
|
|
.tile R17C34:PLC2
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
|
|
.tile R17C37:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
|
|
.tile R17C38:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R17C41:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R17C43:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile R17C47:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R18C31:PLC2
|
|
arc: E3_H06E0003 V01N0001
|
|
|
|
.tile R18C32:PLC2
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
|
|
.tile R18C34:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00R0000 V02N0601
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: A2 W1_H02E0701
|
|
arc: B0 V02N0301
|
|
arc: B3 V01N0001
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C35:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: V00T0000 V02N0401
|
|
arc: A0 V01N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0501
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0701
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C36:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: V00T0000 V02N0601
|
|
arc: A2 V01N0101
|
|
arc: A4 V00T0000
|
|
arc: A6 H00R0000
|
|
arc: B0 V01N0001
|
|
arc: B1 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B5 V02N0701
|
|
arc: B7 V02N0501
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C37:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: V00T0000 V02N0601
|
|
arc: A0 V01N0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0301
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C38:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: S3_V06S0003 F0
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C39:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: A0 H02W0501
|
|
arc: A2 V00B0000
|
|
arc: B3 V01N0001
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011100
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C40:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: A2 V01N0101
|
|
arc: A4 V00T0000
|
|
arc: A6 H00R0000
|
|
arc: B0 V01N0001
|
|
arc: B1 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B5 V02N0501
|
|
arc: B7 V02N0701
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 1001100110011100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C41:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00R0000 V02N0601
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: V00T0000 V02N0401
|
|
arc: A2 V01N0101
|
|
arc: A4 V00T0000
|
|
arc: A6 H00R0000
|
|
arc: B0 V01N0001
|
|
arc: B1 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B5 V02N0501
|
|
arc: B7 V02N0701
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C42:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00T0000 V02N0601
|
|
arc: A0 V01N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V01N0001
|
|
arc: B3 V02N0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0011001100111100
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C43:PLC2
|
|
arc: E1_H01E0001 F0
|
|
arc: F0 F0_SLICE
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R18C44:PLC2
|
|
arc: S1_V02S0201 H01E0001
|
|
|
|
.tile R18C53:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R18C65:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R18C69:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R19C13:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R19C19:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R19C25:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R19C31:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A4 H02W0701
|
|
arc: A5 H02W0701
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 E1_H02W0101
|
|
arc: B3 V02N0301
|
|
arc: B6 E1_H02W0301
|
|
arc: C0 V02N0401
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 V00T0000
|
|
arc: C7 E1_H02W0401
|
|
arc: D0 H00R0000
|
|
arc: D3 V00B0100
|
|
arc: D4 S1_V02N0601
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 V02N0401
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F6
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F0
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
word: SLICED.K1.INIT 1010010101011010
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEC.K1.INIT 1010010101011010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R19C32:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 V01N0101
|
|
arc: B0 V00T0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 E1_H02W0101
|
|
arc: C5 V00T0000
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: D5 V02N0601
|
|
arc: D6 V01N0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 F0
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 1001100101100110
|
|
word: SLICEB.K0.INIT 1110111010001000
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C33:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A1 H02W0501
|
|
arc: A2 H02W0701
|
|
arc: A3 E1_H02W0501
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 H02W0501
|
|
arc: A7 H02W0701
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 H02E0101
|
|
arc: B3 V02N0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 V02N0501
|
|
arc: B6 H02E0101
|
|
arc: B7 W1_H02E0301
|
|
arc: C0 H00L0100
|
|
arc: C2 V02N0401
|
|
arc: C4 V00T0100
|
|
arc: D0 V02N0001
|
|
arc: D1 H02E0001
|
|
arc: D2 V00B0100
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 V02N0601
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 H02E0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0601 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F2
|
|
word: SLICEB.K1.INIT 1001100101100110
|
|
word: SLICEB.K0.INIT 1010010101011010
|
|
word: SLICEC.K1.INIT 1110111010001000
|
|
word: SLICED.K0.INIT 1110111010001000
|
|
word: SLICEC.K0.INIT 1100001100111100
|
|
word: SLICEA.K0.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1110111010001000
|
|
word: SLICEA.K1.INIT 1001100101100110
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R19C34:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 V00B0000
|
|
arc: A5 V02S0301
|
|
arc: A6 H02E0701
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 H02W0301
|
|
arc: B2 H00L0000
|
|
arc: B3 V02N0301
|
|
arc: B4 V02N0501
|
|
arc: B5 W1_H02E0301
|
|
arc: B6 H01E0101
|
|
arc: B7 H02E0101
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 F6
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F4
|
|
arc: N1_V02N0701 F5
|
|
arc: S3_V06S0003 F3
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F4
|
|
arc: W1_H02W0501 Q7
|
|
arc: W1_H02W0601 Q6
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 1100110011001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C35:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: A0 H00R0000
|
|
arc: A1 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 S1_V02N0301
|
|
arc: A5 H02E0501
|
|
arc: A6 V02N0301
|
|
arc: A7 V02N0101
|
|
arc: B0 V02S0101
|
|
arc: B1 V00B0000
|
|
arc: B2 H00L0000
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 V02N0701
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 H02E0301
|
|
arc: B7 W1_H02E0301
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE1 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F5
|
|
arc: N1_V02N0601 F4
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S3_V06S0003 F0
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0501 Q7
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C36:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: A0 H02E0501
|
|
arc: A1 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V00B0000
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 H00R0000
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V02N0301
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V01N0001
|
|
arc: B4 V02N0701
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F4
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0301 Q1
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C37:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 V02N0501
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V02N0301
|
|
arc: A5 V02N0101
|
|
arc: A6 H00L0000
|
|
arc: A7 H02W0501
|
|
arc: B0 H02W0101
|
|
arc: B1 V00T0000
|
|
arc: B2 H02E0301
|
|
arc: B3 W1_H02E0301
|
|
arc: B4 H02W0301
|
|
arc: B5 H00R0000
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 V02N0701
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q3
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C38:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 F7
|
|
arc: A1 F5
|
|
arc: A4 H02E0501
|
|
arc: A5 V00T0100
|
|
arc: B0 V00B0000
|
|
arc: B1 H01W0100
|
|
arc: B6 V00T0000
|
|
arc: B7 V00T0000
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0401
|
|
arc: D6 H02W0201
|
|
arc: D7 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F6
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0101 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: V00B0000 F4
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEC.K1.INIT 1010010101011010
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C39:PLC2
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A2 V00B0000
|
|
arc: A3 V01N0101
|
|
arc: A4 V02N0101
|
|
arc: A5 V00T0000
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 H02W0101
|
|
arc: B3 V01N0001
|
|
arc: B4 H00R0000
|
|
arc: B5 V00B0100
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 S1_V02N0501
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F6
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q4
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 1010101010101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C40:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 V01N0101
|
|
arc: A2 H02E0701
|
|
arc: A3 V02N0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0301
|
|
arc: A6 H00R0000
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V01N0001
|
|
arc: B1 V02N0101
|
|
arc: B2 H00L0000
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0000
|
|
arc: B7 E1_H02W0301
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F5
|
|
arc: N1_V02N0601 F4
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C41:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A0 H02W0501
|
|
arc: A1 S1_V02N0501
|
|
arc: A2 V01N0101
|
|
arc: A3 H02W0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V02N0301
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V01N0001
|
|
arc: B1 V00T0000
|
|
arc: B2 H00R0000
|
|
arc: B3 V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B5 V02N0501
|
|
arc: B6 V00B0000
|
|
arc: B7 V02N0701
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0501 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F5
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C42:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 V02N0501
|
|
arc: A1 H00R0000
|
|
arc: A2 V00B0000
|
|
arc: A3 V00T0000
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V02N0101
|
|
arc: A6 V00T0100
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 H00R0100
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 S1_V02N0301
|
|
arc: B3 V01N0001
|
|
arc: B4 H00L0000
|
|
arc: B5 H02W0101
|
|
arc: B6 V02N0701
|
|
arc: B7 V00B0100
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0501 Q5
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C43:PLC2
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 H02W0501
|
|
arc: A1 F7
|
|
arc: A4 H02E0701
|
|
arc: B0 V00B0000
|
|
arc: B1 E1_H01W0100
|
|
arc: B5 H02W0101
|
|
arc: B6 H02W0101
|
|
arc: B7 V01S0000
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 H01E0001
|
|
arc: C6 H02E0401
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02W0201
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R19C44:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 H02E0001
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 F3
|
|
arc: C1 H02W0601
|
|
arc: C2 H02W0401
|
|
arc: C3 H00L0000
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 S1_V02N0201
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 H01E0101
|
|
arc: D3 V02S0201
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 F4
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
arc: V00T0100 F3
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 1010010101011010
|
|
word: SLICEA.K1.INIT 0101000001010101
|
|
word: SLICEA.K0.INIT 0100010001010101
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEB.K0.INIT 0000000011110011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R19C45:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: H00R0000 V02N0401
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
arc: A1 E1_H01E0001
|
|
arc: B0 V02N0301
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 0000110000001111
|
|
word: SLICEA.K1.INIT 0000101000001111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R19C46:PLC2
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
|
|
.tile R19C51:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R19C57:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R19C63:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R19C69:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R19C75:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R19C7:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R19C81:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C87:PLC2
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
|
|
.tile R20C11:PLC2
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R20C12:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R20C13:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C14:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R20C18:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C19:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R20C20:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R20C22:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
|
|
.tile R20C23:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
|
|
.tile R20C24:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02W0501
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C25:PLC2
|
|
arc: E3_H06E0103 W1_H02E0101
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0601
|
|
arc: W1_H02W0501 V06N0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C26:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R20C27:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R20C28:PLC2
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R20C29:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R20C30:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R20C31:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 H02E0101
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: A2 V00B0000
|
|
arc: A3 V00T0000
|
|
arc: A4 V00T0100
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 H00R0000
|
|
arc: A7 H02E0501
|
|
arc: B0 E1_H02W0101
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 H00L0000
|
|
arc: B5 H02E0301
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 V02N0701
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F7
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: V01S0000 F6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R20C32:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 V00B0000
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 V02N0301
|
|
arc: A5 V02N0101
|
|
arc: A6 H00R0000
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 V00T0000
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 H00L0000
|
|
arc: B5 H02E0101
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 N1_V02S0501
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F5
|
|
arc: V01S0000 F3
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R20C33:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 W1_H02E0701
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V00B0000
|
|
arc: B2 H00L0000
|
|
arc: B6 H02W0301
|
|
arc: B7 V02S0701
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0001
|
|
arc: D6 F2
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0201 F2
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F6
|
|
arc: S1_V02S0201 F2
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R20C34:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A3 H02W0501
|
|
arc: A4 W1_H02E0701
|
|
arc: A7 H02W0501
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B2 V02S0301
|
|
arc: B5 W1_H02E0101
|
|
arc: B6 H02E0301
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0401
|
|
arc: C3 H00L0000
|
|
arc: C4 V02S0001
|
|
arc: C5 V02S0001
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 V02N0001
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 H01E0101
|
|
arc: D3 V02N0001
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 V02N0401
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 F2
|
|
arc: S1_V02S0501 F5
|
|
word: SLICEA.K0.INIT 1111110011000000
|
|
word: SLICEA.K1.INIT 1100001100111100
|
|
word: SLICEB.K0.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
word: SLICED.K1.INIT 1111101010100000
|
|
word: SLICEB.K1.INIT 1010010101011010
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1010010101011010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R20C35:PLC2
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A0 V02S0501
|
|
arc: A2 V00T0000
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 V00B0000
|
|
arc: B1 E1_H02W0101
|
|
arc: B5 H00L0000
|
|
arc: B6 V02S0501
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 V02N0401
|
|
arc: C3 V02S0601
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0001
|
|
arc: C7 H02E0401
|
|
arc: D0 W1_H02E0201
|
|
arc: D1 W1_H02E0201
|
|
arc: D2 H00R0000
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 W1_H02E0201
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 W1_H02E0201
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0301 F3
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0701 F7
|
|
arc: V01S0100 F2
|
|
word: SLICEA.K1.INIT 1100001100111100
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEA.K0.INIT 1111101010100000
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1010010101011010
|
|
word: SLICEB.K0.INIT 1111101010100000
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R20C36:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: A1 V02S0701
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02S0101
|
|
arc: A7 H00R0000
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 V02S0101
|
|
arc: B6 V00B0000
|
|
arc: C0 V02S0401
|
|
arc: C3 V02S0601
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0201
|
|
arc: C7 V02N0201
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 W1_H02E0201
|
|
arc: D5 H02E0201
|
|
arc: D6 W1_H02E0201
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F0
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0701 F5
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEA.K1.INIT 1001100101100110
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1111101010100000
|
|
word: SLICED.K1.INIT 1010010101011010
|
|
word: SLICEC.K1.INIT 1111101010100000
|
|
word: SLICEB.K0.INIT 1001100101100110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
|
|
.tile R20C37:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
arc: A0 H00R0000
|
|
arc: A7 H00R0000
|
|
arc: B1 V00T0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 V02S0301
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 E1_H02W0101
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 V02S0601
|
|
arc: C3 V02N0601
|
|
arc: C4 V00T0100
|
|
arc: C5 V02N0201
|
|
arc: C6 V00T0100
|
|
arc: C7 V02N0201
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 H02E0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 H02E0201
|
|
arc: D5 E1_H02W0201
|
|
arc: D6 V02N0601
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0701 F7
|
|
arc: V01S0100 F6
|
|
word: SLICED.K1.INIT 1111101010100000
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
word: SLICEA.K0.INIT 1010010101011010
|
|
word: SLICEA.K1.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1100001100111100
|
|
word: SLICEB.K0.INIT 1100001100111100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R20C38:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: B4 V02S0701
|
|
arc: C4 W1_H02E0401
|
|
arc: D4 V02N0401
|
|
arc: E1_H01E0101 F4
|
|
arc: F4 F4_SLICE
|
|
word: SLICEC.K0.INIT 1100001100111100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R20C39:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: A0 H00L0000
|
|
arc: A2 H02W0701
|
|
arc: A4 V02S0301
|
|
arc: A6 V02S0301
|
|
arc: A7 V02S0101
|
|
arc: B1 V00T0000
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 V02S0101
|
|
arc: B5 H00L0000
|
|
arc: C0 H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C3 W1_H02E0401
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 V02N0201
|
|
arc: C6 S1_V02N0201
|
|
arc: C7 W1_H02E0401
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 H02E0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0401
|
|
arc: D5 H02W0201
|
|
arc: D6 V02N0401
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F6
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0701 F7
|
|
word: SLICEB.K0.INIT 1110111010001000
|
|
word: SLICEA.K1.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1010010101011010
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1010010101011010
|
|
word: SLICEA.K0.INIT 1010010101011010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C40:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A1 V02S0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V02S0101
|
|
arc: A5 V00B0000
|
|
arc: B0 V02S0101
|
|
arc: B2 V02S0301
|
|
arc: B3 H02E0101
|
|
arc: B4 W1_H02E0101
|
|
arc: B6 V02N0701
|
|
arc: B7 V02N0701
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 H02E0401
|
|
arc: C2 W1_H02E0601
|
|
arc: C4 E1_H02W0401
|
|
arc: C5 V02N0201
|
|
arc: C6 V00T0000
|
|
arc: C7 V00T0000
|
|
arc: D0 V00T0100
|
|
arc: D1 H02W0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: D5 H02E0001
|
|
arc: D6 V02N0601
|
|
arc: D7 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F7
|
|
arc: V01S0100 F2
|
|
word: SLICEB.K1.INIT 1110111010001000
|
|
word: SLICEC.K0.INIT 1001011010010110
|
|
word: SLICEC.K1.INIT 1010010101011010
|
|
word: SLICED.K1.INIT 1111110011000000
|
|
word: SLICEA.K0.INIT 1111110011000000
|
|
word: SLICEB.K0.INIT 1100001100111100
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
word: SLICEA.K1.INIT 1010010101011010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R20C41:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A2 V02N0701
|
|
arc: A7 H00R0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: B2 H02E0101
|
|
arc: B3 V02S0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H02E0101
|
|
arc: B6 E1_H02W0301
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0001
|
|
arc: C6 V01N0101
|
|
arc: C7 V02N0201
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: D4 V02N0601
|
|
arc: D5 S1_V02N0601
|
|
arc: D6 H02E0201
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 F0
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0701 F7
|
|
arc: V01S0100 F6
|
|
word: SLICEB.K0.INIT 1001100101100110
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1111101010100000
|
|
word: SLICEA.K1.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1100001100111100
|
|
word: SLICEC.K0.INIT 1100001100111100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
|
|
.tile R20C42:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A2 H02E0501
|
|
arc: A4 V00B0000
|
|
arc: A5 V02S0101
|
|
arc: A7 H02E0501
|
|
arc: B0 V02S0101
|
|
arc: B1 V00B0000
|
|
arc: B3 H02E0101
|
|
arc: B6 H02E0301
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C4 V02N0201
|
|
arc: C5 V01N0101
|
|
arc: C6 V02N0201
|
|
arc: C7 V02N0201
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 V01N0001
|
|
arc: D5 V02N0601
|
|
arc: D6 V01N0001
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0601 F4
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEA.K0.INIT 1111110011000000
|
|
word: SLICEB.K0.INIT 1111101010100000
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEC.K1.INIT 1010010101011010
|
|
word: SLICEA.K1.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1010010101011010
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R20C43:PLC2
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 H02E0501
|
|
arc: A1 H02E0501
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0101
|
|
arc: B2 V02S0101
|
|
arc: B3 V02N0101
|
|
arc: B6 H02E0101
|
|
arc: B7 V00T0000
|
|
arc: C0 H02E0601
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0601
|
|
arc: C3 V02N0601
|
|
arc: C4 H02E0401
|
|
arc: C5 H02E0401
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0001
|
|
arc: D0 V02N0001
|
|
arc: D1 W1_H02E0201
|
|
arc: D2 H02W0201
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0001
|
|
arc: D6 H02W0201
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F4
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0101 F3
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEC.K1.INIT 1111101010100000
|
|
word: SLICEA.K0.INIT 1111101010100000
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICEA.K1.INIT 1010010101011010
|
|
word: SLICEB.K0.INIT 1100001100111100
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1010010101011010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R20C44:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A0 V02S0501
|
|
arc: A1 H02W0701
|
|
arc: C0 V02S0401
|
|
arc: C1 V02S0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K1.INIT 0000101000001111
|
|
word: SLICEA.K0.INIT 0000101000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C45:PLC2
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C6 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D6 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0401 F6
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 F1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0401 F6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K1.INIT 0000110000001100
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 1111111100110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R20C4:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R20C5:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
|
|
.tile R20C7:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R20C87:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
|
|
.tile R20C8:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R21C23:PLC2
|
|
arc: E3_H06E0303 V01N0101
|
|
|
|
.tile R21C26:PLC2
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 V01N0101
|
|
|
|
.tile R21C27:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0103 V01N0101
|
|
|
|
.tile R21C28:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0203 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
|
|
.tile R21C29:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R21C30:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
|
|
.tile R21C31:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: A2 V02N0701
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 W1_H02E0701
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 H00L0000
|
|
arc: A7 V02S0301
|
|
arc: B0 V02S0101
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 W1_H02E0301
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0601 F6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C32:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 H02E0501
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 H02E0701
|
|
arc: A5 H02W0701
|
|
arc: A6 E1_H02W0501
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 H02W0301
|
|
arc: B3 H02W0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02S0501
|
|
arc: B6 V00T0000
|
|
arc: B7 H02E0301
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F2
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C33:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 V02N0701
|
|
arc: A0 V02N0501
|
|
arc: A1 H02E0701
|
|
arc: A2 H02E0701
|
|
arc: B0 H02E0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0301
|
|
arc: B6 V02S0501
|
|
arc: B7 N1_V02S0701
|
|
arc: C6 V02S0201
|
|
arc: C7 V02S0201
|
|
arc: D6 F2
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 F0
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0001 F2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
word: SLICED.K1.INIT 1111110011000000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R21C34:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0100 H02W0301
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: B0 W1_H02E0301
|
|
arc: B3 H02W0301
|
|
arc: C0 H00L0100
|
|
arc: C3 W1_H02E0401
|
|
arc: D0 W1_H02E0201
|
|
arc: D3 V00T0100
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
word: SLICEB.K1.INIT 1100001100111100
|
|
word: SLICEA.K0.INIT 1111110011000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R21C35:PLC2
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A2 H02W0501
|
|
arc: A3 H02W0501
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0301
|
|
arc: B6 V00T0000
|
|
arc: C6 W1_H02E0401
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 W1_H02E0001
|
|
arc: D6 W1_H02E0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0401 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1110111010001000
|
|
word: SLICEB.K0.INIT 1001100101100110
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
|
|
.tile R21C36:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A2 V00T0000
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 H02E0501
|
|
arc: A6 H00L0000
|
|
arc: A7 V02N0101
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B4 V02N0701
|
|
arc: B5 H00R0000
|
|
arc: B6 V00B0000
|
|
arc: B7 S1_V02N0501
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0103 F2
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F4
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F3
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C37:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: A0 V02N0501
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 V00B0000
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 E1_H02W0501
|
|
arc: A5 H02E0501
|
|
arc: A6 H00L0000
|
|
arc: A7 V02N0101
|
|
arc: B0 V00T0000
|
|
arc: B1 H02E0301
|
|
arc: B2 H02E0101
|
|
arc: B3 H00R0000
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 V02N0701
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 V00B0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 F0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C38:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 V02N0701
|
|
arc: A1 H00R0000
|
|
arc: A2 V00B0000
|
|
arc: B0 H02E0101
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0301 F1
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C39:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 N1_V02S0701
|
|
arc: A3 W1_H02E0701
|
|
arc: A4 H02W0701
|
|
arc: A5 H02W0701
|
|
arc: A6 H00L0000
|
|
arc: A7 W1_H02E0701
|
|
arc: B2 H00L0000
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 N1_V02S0501
|
|
arc: C0 W1_H02E0401
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 H02W0601
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 V00T0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 H00R0000
|
|
arc: D3 V00T0100
|
|
arc: D4 H02E0201
|
|
arc: D5 H02E0201
|
|
arc: D6 V00B0000
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F4
|
|
arc: N1_V02N0701 F5
|
|
word: SLICEB.K0.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1010010101011010
|
|
word: SLICEA.K0.INIT 1111101010100000
|
|
word: SLICED.K1.INIT 1111101010100000
|
|
word: SLICEC.K1.INIT 1110111010001000
|
|
word: SLICEA.K1.INIT 1010010101011010
|
|
word: SLICEB.K1.INIT 1010010101011010
|
|
word: SLICEC.K0.INIT 1001100101100110
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R21C40:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A2 V00T0000
|
|
arc: A3 V02N0701
|
|
arc: A4 H02W0701
|
|
arc: A5 V00B0000
|
|
arc: A6 H00R0000
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 V01N0001
|
|
arc: B2 V02N0101
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 H02E0101
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 H02E0301
|
|
arc: B7 V02N0501
|
|
arc: E1_H01E0001 F4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 F6
|
|
arc: N1_V01N0001 F2
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 F7
|
|
arc: W1_H02W0601 F6
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C41:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: A0 V02N0701
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 V00T0000
|
|
arc: A3 H02W0501
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0301
|
|
arc: A6 H00R0000
|
|
arc: A7 H02E0701
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 V00B0000
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0101
|
|
arc: B4 H00L0000
|
|
arc: B5 V00B0100
|
|
arc: B6 V02N0501
|
|
arc: B7 S1_V02N0701
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0701 F7
|
|
arc: V01S0000 F7
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0601 F4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C42:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 V02N0501
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: B0 V00B0000
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 E1_H02W0301
|
|
arc: B6 V00T0000
|
|
arc: B7 V00T0000
|
|
arc: C6 H02E0601
|
|
arc: C7 H02E0401
|
|
arc: D6 F0
|
|
arc: D7 F0
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F6
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0001 F2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R21C43:PLC2
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 E1_H02W0701
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 N1_V02S0301
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 E1_H01W0100
|
|
arc: B2 N1_V02S0301
|
|
arc: B4 H01E0101
|
|
arc: B5 H02W0101
|
|
arc: B7 H02E0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 H02E0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 V00T0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 H01E0101
|
|
arc: D3 H02E0201
|
|
arc: D4 H00R0100
|
|
arc: D5 H02E0001
|
|
arc: D7 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0401 F4
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0301 F3
|
|
arc: W1_H02W0701 F5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1011101010111111
|
|
word: SLICEB.K0.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1010010101011010
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1001100101100110
|
|
word: SLICEC.K0.INIT 1110111010001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R21C44:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00R0000 H02W0401
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 W3_H06E0103
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A7 Q7
|
|
arc: B0 V01N0001
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 Q3
|
|
arc: B6 V01S0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0301 Q3
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F5
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C45:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A2 F5
|
|
arc: A3 H02E0501
|
|
arc: A4 V00B0000
|
|
arc: A5 V00T0000
|
|
arc: B2 V02N0101
|
|
arc: B3 H00R0100
|
|
arc: B4 N1_V01S0000
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C4 H01E0001
|
|
arc: C5 V02S0201
|
|
arc: C6 Q6
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0001
|
|
arc: D3 H01E0101
|
|
arc: D4 F2
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0601 Q6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0100 F5
|
|
arc: W1_H02W0601 F4
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0101010101010100
|
|
word: SLICEC.K0.INIT 1111101100000000
|
|
word: SLICED.K0.INIT 0000111100001111
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 1111111100001010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R21C46:PLC2
|
|
arc: B0 W1_H02E0301
|
|
arc: C0 H02E0601
|
|
arc: C4 S1_V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D4 H02E0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 F0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00B0000 F4
|
|
word: SLICEC.K0.INIT 1111000011111111
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C51:PLC2
|
|
arc: E3_H06E0303 V01N0101
|
|
|
|
.tile R21C52:PLC2
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
|
|
.tile R21C54:PLC2
|
|
arc: S1_V02S0501 H06E0303
|
|
|
|
.tile R21C55:PLC2
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0701 H02W0701
|
|
|
|
.tile R21C56:PLC2
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile R21C60:PLC2
|
|
arc: S1_V02S0701 V01N0101
|
|
|
|
.tile R21C61:PLC2
|
|
arc: S1_V02S0101 V01N0101
|
|
|
|
.tile R21C65:PLC2
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0701 H06W0203
|
|
|
|
.tile R21C66:PLC2
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0701 H06W0203
|
|
|
|
.tile R21C67:PLC2
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
|
|
.tile R21C68:PLC2
|
|
arc: W3_H06W0203 E1_H02W0401
|
|
|
|
.tile R21C69:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0203 V01N0001
|
|
|
|
.tile R21C70:PLC2
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: W1_H02W0401 V02N0401
|
|
|
|
.tile R21C72:PLC2
|
|
arc: W3_H06W0003 E1_H02W0001
|
|
|
|
.tile R21C73:PLC2
|
|
arc: W3_H06W0103 E1_H02W0101
|
|
|
|
.tile R21C74:PLC2
|
|
arc: W1_H02W0001 V02N0001
|
|
|
|
.tile R21C75:PLC2
|
|
arc: W1_H02W0101 V02N0101
|
|
|
|
.tile R23C11:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R23C12:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R23C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C14:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C15:PLC2
|
|
arc: S3_V06S0203 H06W0203
|
|
|
|
.tile R23C18:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C19:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C20:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C24:PLC2
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R23C25:PLC2
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C26:PLC2
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R23C27:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
|
|
.tile R23C28:PLC2
|
|
arc: N1_V02N0601 H06W0303
|
|
|
|
.tile R23C29:PLC2
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R23C30:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: V00B0100 H02W0701
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
arc: A6 V02N0101
|
|
arc: B6 E1_H02W0301
|
|
arc: C6 E1_H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 V02N0601
|
|
arc: F6 F6_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0401 Q6
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICED.K0.INIT 1111000111111101
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C32:PLC2
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R23C33:PLC2
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
|
|
.tile R23C34:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
|
|
.tile R23C35:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
|
|
.tile R23C36:PLC2
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 E1_H02W0101
|
|
arc: C0 V02S0401
|
|
arc: C2 W1_H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D2 V02S0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 0000000011110011
|
|
word: SLICEB.K0.INIT 0000000011110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C37:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: A1 S1_V02N0501
|
|
arc: B0 V02S0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 V02S0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N3_V06N0003 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 0000000011001111
|
|
word: SLICEA.K1.INIT 0000000010101111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R23C38:PLC2
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A2 S1_V02N0501
|
|
arc: A4 F7
|
|
arc: A7 H00R0000
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0301
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 H02W0101
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 V02S0601
|
|
arc: C1 N1_V02S0401
|
|
arc: C2 N1_V02S0401
|
|
arc: C4 V01N0101
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0601
|
|
arc: D7 V01N0001
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N3_V06N0103 Q1
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0301 F3
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0203 F4
|
|
word: SLICEA.K1.INIT 0000110000001111
|
|
word: SLICEA.K0.INIT 0011000000110011
|
|
word: SLICEB.K0.INIT 0000101000001111
|
|
word: SLICEB.K1.INIT 0000000000110011
|
|
word: SLICED.K1.INIT 0011001100110010
|
|
word: SLICEC.K0.INIT 1010101010100010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R23C39:PLC2
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 V02N0201
|
|
arc: D2 H00R0000
|
|
arc: D3 V02N0201
|
|
arc: D4 E1_H01W0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0203 F4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: S1_V02S0001 F2
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0601 F4
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K0.INIT 1111111100001111
|
|
word: SLICEB.K1.INIT 0000000011110000
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R23C3:PLC2
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
|
|
.tile R23C40:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0000 H02E0601
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0501
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H00R0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 F1
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K1.INIT 1111111100001010
|
|
word: SLICEA.K0.INIT 1111111100001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C41:PLC2
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: B3 N1_V02S0101
|
|
arc: C3 S1_V02N0601
|
|
arc: D3 H02W0001
|
|
arc: F3 F3_SLICE
|
|
arc: N1_V02N0101 F3
|
|
word: SLICEB.K1.INIT 1100001100111100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R23C42:PLC2
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
|
|
.tile R23C43:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R23C44:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
|
|
.tile R23C45:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
|
|
.tile R23C46:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: N1_V02N0001 H06E0003
|
|
|
|
.tile R23C47:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: A5 V02N0101
|
|
arc: B5 W1_H02E0101
|
|
arc: C5 V02N0001
|
|
arc: D5 H02E0001
|
|
arc: F5 F5_SLICE
|
|
arc: N3_V06N0303 F5
|
|
word: SLICEC.K1.INIT 1111111111111110
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R23C48:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q4
|
|
arc: LSR1 H02W0301
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C49:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
|
|
.tile R23C50:PLC2
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
|
|
.tile R23C51:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 V02S0401
|
|
|
|
.tile R23C52:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 V02S0601
|
|
|
|
.tile R23C53:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
|
|
.tile R23C54:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 V02S0001
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0601
|
|
arc: A2 H02W0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V02S0101
|
|
arc: A5 V00T0000
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 V02S0301
|
|
arc: B0 H02E0301
|
|
arc: B2 H00L0000
|
|
arc: B3 H02W0301
|
|
arc: B4 H02E0101
|
|
arc: B5 N1_V02S0501
|
|
arc: B6 V02S0701
|
|
arc: B7 W1_H02E0301
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0103 F2
|
|
arc: E3_H06E0303 F6
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C55:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00R0000 V02S0601
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 V02S0501
|
|
arc: A2 V00T0000
|
|
arc: A3 H02W0501
|
|
arc: A4 V02S0101
|
|
arc: A5 V00B0000
|
|
arc: A6 H02E0701
|
|
arc: A7 H00R0000
|
|
arc: B0 V02S0301
|
|
arc: B1 H02W0301
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0101
|
|
arc: B4 V02S0701
|
|
arc: B5 N1_V02S0701
|
|
arc: B6 E1_H02W0301
|
|
arc: B7 E1_H02W0101
|
|
arc: E1_H01E0101 F1
|
|
arc: E3_H06E0003 F3
|
|
arc: E3_H06E0203 F7
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C56:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 V02S0701
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 W1_H02E0501
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: S3_V06S0103 F1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C57:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
|
|
.tile R23C58:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: S3_V06S0103 H06E0103
|
|
|
|
.tile R23C59:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0501
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: A2 V00T0000
|
|
arc: A3 V02S0501
|
|
arc: A4 V02S0301
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 H00R0000
|
|
arc: A7 H02W0501
|
|
arc: B0 V02S0101
|
|
arc: B2 H00L0000
|
|
arc: B3 H00R0100
|
|
arc: B4 V02S0701
|
|
arc: B5 H02E0101
|
|
arc: B6 V00B0000
|
|
arc: B7 W1_H02E0301
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0601 F6
|
|
arc: S3_V06S0203 F7
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C5:PLC2
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
|
|
.tile R23C60:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0601
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A0 H00L0000
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0701
|
|
arc: A4 V02S0301
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 H02W0701
|
|
arc: B0 V00T0000
|
|
arc: B1 V02S0101
|
|
arc: B2 H00R0000
|
|
arc: B3 H02W0301
|
|
arc: B4 V00B0100
|
|
arc: B5 H02W0101
|
|
arc: B6 V00B0000
|
|
arc: B7 W1_H02E0301
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0501 F7
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0301 F1
|
|
arc: S3_V06S0203 F4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0000 F6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C61:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 V02S0701
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0501
|
|
arc: B0 V00T0000
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: E1_H01E0101 F1
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: S1_V02S0201 F0
|
|
arc: S3_V06S0103 F2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C62:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R23C63:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
|
|
.tile R23C64:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0701 H06W0203
|
|
|
|
.tile R23C65:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0000 V02S0401
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0601
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 H02E0701
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 V00T0000
|
|
arc: A6 H00R0000
|
|
arc: A7 V02S0301
|
|
arc: B0 W1_H02E0101
|
|
arc: B2 V02S0101
|
|
arc: B3 N1_V02S0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V00B0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F6
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0000 F4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C66:PLC2
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00R0000 V02S0601
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 H00R0000
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A3 V02S0501
|
|
arc: A4 H02E0701
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 V02S0101
|
|
arc: A7 N1_V02S0301
|
|
arc: B0 V00B0000
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 V02S0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 V02S0701
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V02N0701
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F6
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 F1
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C67:PLC2
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W3_H06W0203 E1_H02W0701
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0701
|
|
arc: A2 V02S0701
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: B6 V00T0000
|
|
arc: B7 V00T0000
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 S1_V02N0201
|
|
arc: D6 E1_H02W0201
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F7
|
|
arc: V00T0000 F0
|
|
arc: V01S0000 F2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R23C68:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A0 W1_H02E0501
|
|
arc: A1 W1_H02E0501
|
|
arc: A3 H01E0001
|
|
arc: B5 H01E0101
|
|
arc: B6 H01E0101
|
|
arc: B7 H01E0101
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C3 S1_V02N0601
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V00T0000
|
|
arc: C7 S1_V02N0001
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D3 H00R0000
|
|
arc: D5 V02N0401
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F5
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
word: SLICED.K1.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1010010101011010
|
|
word: SLICEA.K1.INIT 1111101010100000
|
|
word: SLICEA.K0.INIT 1010010101011010
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R23C69:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A2 V00B0000
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02S0101
|
|
arc: A6 N1_V02S0301
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 H02E0101
|
|
arc: B2 H00R0000
|
|
arc: B3 V02S0301
|
|
arc: B4 N1_V02S0501
|
|
arc: B5 V02S0701
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V02S0501
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F3
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C70:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02S0601
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 V02S0501
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 H02W0501
|
|
arc: A5 V02S0101
|
|
arc: A6 V00T0100
|
|
arc: A7 N1_V02S0101
|
|
arc: B0 E1_H02W0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 H00L0000
|
|
arc: B3 H00R0000
|
|
arc: B4 N1_V02S0701
|
|
arc: B5 V00B0100
|
|
arc: B6 V00T0000
|
|
arc: B7 N1_V01S0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F2
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0501 F7
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0203 F4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C71:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
arc: A0 V02S0701
|
|
arc: A1 H00R0000
|
|
arc: A2 V00T0000
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0201 F0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C72:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
|
|
.tile R23C73:PLC2
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R23C74:PLC2
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R23C78:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
|
|
.tile R23C79:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R23C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R23C85:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
|
|
.tile R23C87:PLC2
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
|
|
.tile R23C8:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R24C28:PLC2
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
|
|
.tile R24C31:PLC2
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0601 H02W0601
|
|
|
|
.tile R24C32:PLC2
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
|
|
.tile R24C34:PLC2
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: N1_V02N0501 E3_H06W0303
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R24C35:PLC2
|
|
arc: N1_V02N0601 H02E0601
|
|
|
|
.tile R24C37:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R24C38:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A2 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 N1_V02S0301
|
|
arc: B3 Q3
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q7
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 F7
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0601 F6
|
|
arc: V00B0000 Q4
|
|
arc: W3_H06W0303 F5
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C39:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N3_V06N0103 H06W0103
|
|
arc: V00B0000 V02S0001
|
|
arc: A2 F7
|
|
arc: A7 H02E0501
|
|
arc: B2 H02E0101
|
|
arc: B7 H01E0101
|
|
arc: C7 H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02W0201
|
|
arc: D7 H00R0100
|
|
arc: E3_H06E0103 Q2
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0201 F2
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 1000100000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C40:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C42:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R24C43:PLC2
|
|
arc: N1_V02N0501 H06W0303
|
|
|
|
.tile R24C45:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C46:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R24C47:PLC2
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
|
|
.tile R24C48:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R24C49:PLC2
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
|
|
.tile R24C51:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
|
|
.tile R24C52:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C53:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: A7 V00T0100
|
|
arc: B7 W1_H02E0101
|
|
arc: C7 V00T0000
|
|
arc: D7 H02E0001
|
|
arc: F7 F7_SLICE
|
|
arc: N3_V06N0203 F7
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C54:PLC2
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00R0000 H02E0401
|
|
arc: V00T0000 H02W0001
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C55:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: A0 V01N0101
|
|
arc: A3 V02N0501
|
|
arc: B0 F3
|
|
arc: B3 V01N0001
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 V02N0601
|
|
arc: C6 V02S0001
|
|
arc: C7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D2 F0
|
|
arc: D3 S1_V02N0001
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0201 F0
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0501 F7
|
|
arc: V00B0000 F6
|
|
arc: V00T0000 F0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICED.K0.INIT 1111000011111111
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1000100000000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 0000111100000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C56:PLC2
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: B0 H01W0100
|
|
arc: C0 N1_V02S0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0011000011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C57:PLC2
|
|
arc: H00R0000 H02W0401
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: A2 H02W0501
|
|
arc: B0 H02W0301
|
|
arc: B2 E1_H01W0100
|
|
arc: C0 H00L0000
|
|
arc: C1 H02E0601
|
|
arc: C2 E1_H01W0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 W1_H02E0001
|
|
arc: D2 H00R0000
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 F2
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S3_V06S0003 F0
|
|
arc: V00T0100 F1
|
|
arc: V01S0000 F0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K1.INIT 1111111100001111
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R24C58:PLC2
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 S1_V02N0301
|
|
arc: B2 V01N0001
|
|
arc: B3 Q3
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C59:PLC2
|
|
arc: A2 H02W0701
|
|
arc: A7 H02W0701
|
|
arc: B7 N1_V01S0000
|
|
arc: C2 V02N0601
|
|
arc: D2 N1_V01S0000
|
|
arc: D7 V02N0601
|
|
arc: F2 F2_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0203 F7
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1110111010001000
|
|
word: SLICEB.K0.INIT 1010010101011010
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R24C60:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R24C61:PLC2
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 H02W0201
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S3_V06S0203 H06W0203
|
|
arc: V00B0100 V02S0101
|
|
arc: B0 H01W0100
|
|
arc: C0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0011000011111100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R24C62:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: V00B0000 H02E0601
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: A2 H02E0701
|
|
arc: A4 V00B0000
|
|
arc: A7 H02E0701
|
|
arc: B0 H02W0301
|
|
arc: B5 H00R0000
|
|
arc: C0 V02N0601
|
|
arc: C2 S1_V02N0401
|
|
arc: C4 W1_H02E0601
|
|
arc: C5 H02E0601
|
|
arc: C7 V02S0201
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D2 V02S0201
|
|
arc: D4 H01W0000
|
|
arc: D5 H01W0000
|
|
arc: D7 S1_V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0100 F4
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1010010101011010
|
|
word: SLICEB.K0.INIT 1111101010100000
|
|
word: SLICED.K1.INIT 1010010101011010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C63:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: B2 E1_H02W0301
|
|
arc: C2 H00L0000
|
|
arc: D2 W1_H02E0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: S1_V02S0001 F2
|
|
arc: V01S0100 F2
|
|
word: SLICEB.K0.INIT 1100110011111100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R24C64:PLC2
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: E3_H06E0203 F7
|
|
arc: F7 F7_SLICE
|
|
arc: S1_V02S0501 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R24C65:PLC2
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: A0 V02N0501
|
|
arc: B3 V01N0001
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02S0501
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 V02N0401
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 V00T0000
|
|
arc: C5 E1_H02W0601
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D3 V00T0100
|
|
arc: D4 V02N0601
|
|
arc: D5 V01N0001
|
|
arc: D7 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F7
|
|
word: SLICEA.K0.INIT 0000101000001111
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1100001100111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R24C66:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: A0 H00L0000
|
|
arc: A1 V01N0101
|
|
arc: A3 V02S0501
|
|
arc: A4 N1_V01S0100
|
|
arc: B2 E1_H02W0301
|
|
arc: B5 H00L0000
|
|
arc: B6 V02S0501
|
|
arc: B7 V00B0000
|
|
arc: C0 V02S0601
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 V02N0601
|
|
arc: C3 H00R0100
|
|
arc: C4 V01N0101
|
|
arc: C5 V02N0001
|
|
arc: C6 V00T0000
|
|
arc: C7 E1_H02W0601
|
|
arc: D0 V02N0201
|
|
arc: D1 H00R0000
|
|
arc: D2 N1_V02S0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V02S0401
|
|
arc: D5 V02S0601
|
|
arc: D6 H00R0100
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F6
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F1
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F2
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
word: SLICEA.K0.INIT 1111101010100000
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEA.K1.INIT 1010010101011010
|
|
word: SLICEB.K0.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1111101010100000
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R24C67:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0601 E1_H02W0601
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A4 V02S0301
|
|
arc: A5 V02N0101
|
|
arc: A6 V02N0301
|
|
arc: B0 V02S0301
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0101
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0601
|
|
arc: C2 V02S0401
|
|
arc: C3 V02S0401
|
|
arc: C4 V02S0001
|
|
arc: C5 V02S0201
|
|
arc: C7 E1_H02W0401
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 V02N0401
|
|
arc: D5 V00B0000
|
|
arc: D6 V00B0000
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0101 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: N1_V01N0101 F4
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F0
|
|
word: SLICEA.K0.INIT 1111110011000000
|
|
word: SLICEB.K0.INIT 1100001100111100
|
|
word: SLICEC.K0.INIT 1010010101011010
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICEA.K1.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
word: SLICEC.K1.INIT 1010010101011010
|
|
word: SLICED.K0.INIT 1110111010001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
|
|
.tile R24C68:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: S1_V02S0101 W3_H06E0103
|
|
arc: S1_V02S0201 W3_H06E0103
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: S3_V06S0303 H06W0303
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: A6 H00R0000
|
|
arc: B0 V00B0000
|
|
arc: B1 H02W0101
|
|
arc: B5 H02W0101
|
|
arc: B7 V00T0000
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 V02N0401
|
|
arc: C3 H02W0401
|
|
arc: C4 V02N0201
|
|
arc: C5 H02E0601
|
|
arc: C6 H02E0601
|
|
arc: C7 H02W0401
|
|
arc: D0 V02N0201
|
|
arc: D1 V00T0100
|
|
arc: D2 H00R0000
|
|
arc: D3 V00T0100
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 H02E0001
|
|
arc: D6 V02N0401
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F7
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F0
|
|
word: SLICEC.K0.INIT 1010010101011010
|
|
word: SLICEB.K0.INIT 1010010101011010
|
|
word: SLICED.K0.INIT 1111101010100000
|
|
word: SLICEA.K0.INIT 1111110011000000
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICEA.K1.INIT 1100001100111100
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1111101010100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R24C69:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: B0 V01N0001
|
|
arc: B4 E1_H02W0101
|
|
arc: B7 V00T0000
|
|
arc: C0 V02N0401
|
|
arc: C4 W1_H02E0601
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D4 V02N0601
|
|
arc: D7 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N3_V06N0003 Q0
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEA.K0.INIT 0011000000110011
|
|
word: SLICEC.K0.INIT 1100001100111100
|
|
word: SLICED.K1.INIT 1111110011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R24C70:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
|
|
.tile R24C71:PLC2
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
|
|
.tile R24C73:PLC2
|
|
arc: N1_V02N0601 H06E0303
|
|
|
|
.tile R25C19:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R25C22:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C28:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C34:PLC2
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R25C35:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
|
|
.tile R25C36:PLC2
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
|
|
.tile R25C37:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0501 H06E0303
|
|
|
|
.tile R25C38:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
|
|
.tile R25C40:PLC2
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R25C41:PLC2
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: W3_H06W0003 V06N0003
|
|
|
|
.tile R25C46:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C52:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C55:PLC2
|
|
arc: H00R0100 V02S0501
|
|
arc: V00T0000 V02S0401
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B2 V01N0001
|
|
arc: B3 Q3
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0601 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q5
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C56:PLC2
|
|
arc: B6 N1_V01S0000
|
|
arc: C6 V02S0001
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0101 F6
|
|
arc: E3_H06E0303 F6
|
|
arc: F6 F6_SLICE
|
|
arc: V01S0100 F6
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111001111110000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R25C57:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: W1_H02W0301 H01E0101
|
|
|
|
.tile R25C58:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: C1 H02E0601
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02E0001
|
|
arc: D2 Q2
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: V01S0000 F1
|
|
word: SLICEA.K1.INIT 0000000011110000
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
|
|
.tile R25C59:PLC2
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
|
|
.tile R25C60:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: S1_V02S0501 H06W0303
|
|
|
|
.tile R25C61:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: B4 H02E0301
|
|
arc: B5 H02E0301
|
|
arc: C4 H02W0601
|
|
arc: C5 H02W0601
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 E1_H01W0100
|
|
arc: E1_H01E0101 F4
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: S1_V02S0501 F5
|
|
word: SLICEC.K0.INIT 1111110011000000
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R25C62:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: A0 V02N0701
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 N1_V02S0101
|
|
arc: A6 H02E0701
|
|
arc: A7 H02E0701
|
|
arc: B0 H02W0301
|
|
arc: B1 H02W0301
|
|
arc: B4 H02E0301
|
|
arc: B5 H02E0301
|
|
arc: C1 H02W0601
|
|
arc: C6 V01N0101
|
|
arc: C7 V01N0101
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0001
|
|
arc: D4 H01W0000
|
|
arc: D5 H01W0000
|
|
arc: D6 H00R0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 F5
|
|
word: SLICEA.K0.INIT 1110111000100010
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
word: SLICED.K1.INIT 1111101010100000
|
|
word: SLICED.K0.INIT 1010010101011010
|
|
word: SLICEC.K0.INIT 1110111010001000
|
|
word: SLICEC.K1.INIT 1001100101100110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C63:PLC2
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0100 H02E0101
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: A4 V02N0101
|
|
arc: A7 V02N0101
|
|
arc: B0 V02S0301
|
|
arc: B3 V02N0101
|
|
arc: B4 H02E0101
|
|
arc: B7 H02E0101
|
|
arc: C0 S1_V02N0401
|
|
arc: C3 H00L0100
|
|
arc: C4 V02N0001
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D3 V01S0100
|
|
arc: D7 H01W0000
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1001011010010110
|
|
word: SLICED.K1.INIT 1001100101100110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C64:PLC2
|
|
arc: H00R0100 V02S0701
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: A3 H02W0701
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 E1_H01W0000
|
|
arc: A6 H02W0701
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 V00B0000
|
|
arc: B2 H02W0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B5 H02W0101
|
|
arc: C0 H02W0601
|
|
arc: C1 W1_H02E0401
|
|
arc: C2 E1_H01W0000
|
|
arc: C4 H02W0601
|
|
arc: C6 V00T0100
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 V02N0201
|
|
arc: D2 H02W0201
|
|
arc: D3 V00T0100
|
|
arc: D4 H02W0001
|
|
arc: D5 H02W0201
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0401 F4
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K1.INIT 0000110000001111
|
|
word: SLICEB.K0.INIT 1100001100111100
|
|
word: SLICEC.K1.INIT 1110111010001000
|
|
word: SLICED.K0.INIT 1010010101011010
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEB.K1.INIT 1110111010001000
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R25C65:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 V02N0501
|
|
arc: A3 H01E0001
|
|
arc: A4 H02E0701
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 H00L0000
|
|
arc: A7 V02S0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H01E0101
|
|
arc: B6 H02E0101
|
|
arc: B7 V00B0000
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F5
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q5
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 Q4
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0401 F6
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 1100110011001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C66:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 V02S0601
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: A0 H02E0701
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0701
|
|
arc: A4 V02S0101
|
|
arc: A5 H02E0501
|
|
arc: A6 V02S0301
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 V00B0000
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 H00L0000
|
|
arc: B3 N1_V02S0301
|
|
arc: B4 H02W0101
|
|
arc: B5 H00R0000
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V00T0000
|
|
arc: CE0 H02E0101
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C67:PLC2
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: A0 H00R0000
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 V02S0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0101
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 V02S0301
|
|
arc: B0 H02W0301
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0100
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 E1_H02W0101
|
|
arc: B6 V02S0501
|
|
arc: B7 N1_V02S0501
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C68:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 N1_V02S0501
|
|
arc: A2 V02N0701
|
|
arc: A3 H02W0501
|
|
arc: A4 N1_V02S0101
|
|
arc: A5 V00T0000
|
|
arc: A6 H00R0000
|
|
arc: A7 H02W0701
|
|
arc: B0 H00R0100
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 V02N0301
|
|
arc: B3 H00L0000
|
|
arc: B4 V02S0701
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0100
|
|
arc: CE0 V02S0201
|
|
arc: CE1 V02S0201
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0601 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C69:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 V01N0101
|
|
arc: A4 N1_V02S0101
|
|
arc: A6 N1_V02S0101
|
|
arc: A7 H00R0000
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 V00T0000
|
|
arc: B5 H01E0101
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 H01E0101
|
|
arc: C4 V00B0100
|
|
arc: C5 V02S0201
|
|
arc: C6 V00B0100
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H00L0100
|
|
arc: D5 V02S0401
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F4
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F1
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0601 F6
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICED.K1.INIT 1001100101100110
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICED.K0.INIT 1001011010010110
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R25C70:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: A0 H01E0001
|
|
arc: A5 V02S0301
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B6 V00B0000
|
|
arc: C0 E1_H02W0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C5 H02E0401
|
|
arc: C6 V00B0100
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D5 H00R0100
|
|
arc: D6 H00R0100
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F6
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W1_H02W0201 F2
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 0101000001010101
|
|
word: SLICEC.K1.INIT 1010010101011010
|
|
word: SLICEB.K0.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1100001100111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R25C71:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0601 W3_H06E0303
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: B0 W1_H02E0101
|
|
arc: C0 W1_H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 0011000000110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C72:PLC2
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
|
|
.tile R25C76:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R25C77:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R25C82:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R25C83:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R26C53:PLC2
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
|
|
.tile R26C54:PLC2
|
|
arc: E3_H06E0303 V06S0303
|
|
|
|
.tile R26C55:PLC2
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C56:PLC2
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
|
|
.tile R26C57:PLC2
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
|
|
.tile R26C58:PLC2
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R26C59:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02S0501
|
|
arc: B0 H02W0101
|
|
arc: B1 V00T0000
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0101
|
|
arc: C0 H00L0100
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H00L0000
|
|
arc: C3 E1_H01W0000
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00B0100
|
|
arc: D2 H02W0201
|
|
arc: D3 H02W0001
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V01S0100 F2
|
|
word: SLICEB.K0.INIT 1111110011000000
|
|
word: SLICEA.K1.INIT 1111110011000000
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1100001100111100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C60:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: E1_H02E0701 H01E0101
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: S3_V06S0303 H01E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: A2 V02N0701
|
|
arc: A3 V01N0101
|
|
arc: B3 H01W0100
|
|
arc: B5 H00R0000
|
|
arc: B6 V00B0000
|
|
arc: C0 V02N0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0601
|
|
arc: C5 V01N0101
|
|
arc: C6 V02N0201
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D5 H00R0100
|
|
arc: D6 S1_V02N0401
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0100 F2
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 1001011010010110
|
|
word: SLICEB.K0.INIT 1111101010100000
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R26C61:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: H00R0100 V02S0701
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: V00T0100 V02N0701
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V00B0000
|
|
arc: B2 E1_H02W0301
|
|
arc: B5 H02W0301
|
|
arc: B6 V02N0701
|
|
arc: B7 H02W0301
|
|
arc: C0 H02W0401
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 E1_H02W0401
|
|
arc: C5 V02S0201
|
|
arc: C6 H02E0401
|
|
arc: C7 V02S0201
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00T0100
|
|
arc: D2 S1_V02N0201
|
|
arc: D5 H01W0000
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V01S0100 F1
|
|
word: SLICEB.K0.INIT 1111110000110000
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICED.K1.INIT 1111110011000000
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
word: SLICEA.K1.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R26C62:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: A1 V02N0501
|
|
arc: A4 S1_V02N0101
|
|
arc: A7 H00R0000
|
|
arc: B0 V02N0101
|
|
arc: B1 H02W0301
|
|
arc: B2 H00R0000
|
|
arc: B3 H02E0101
|
|
arc: B4 H02W0301
|
|
arc: B5 H02E0101
|
|
arc: B6 S1_V02N0501
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 H02E0401
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V00T0100
|
|
arc: C7 W1_H02E0601
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00B0100
|
|
arc: D2 H02E0201
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 V02N0401
|
|
arc: D5 H02E0001
|
|
arc: D6 S1_V02N0601
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F7
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1110111000100010
|
|
word: SLICEC.K0.INIT 1011101110001000
|
|
word: SLICED.K0.INIT 1111110000001100
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
word: SLICEB.K0.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1010010101011010
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C63:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: A0 V01N0101
|
|
arc: A2 V02N0501
|
|
arc: A6 V00T0100
|
|
arc: A7 H00L0000
|
|
arc: B1 H02E0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 H02E0101
|
|
arc: B5 W1_H02E0101
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 W1_H02E0101
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 H00L0100
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 H00L0000
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V00T0100
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 V00T0100
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 N1_V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 H02E0201
|
|
arc: D2 V00B0100
|
|
arc: D3 V00T0100
|
|
arc: D4 H00L0100
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0001 Q2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0601 F4
|
|
arc: V01S0000 F5
|
|
arc: V01S0100 F7
|
|
word: SLICEB.K0.INIT 1111000010101010
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
word: SLICED.K1.INIT 1110100011101000
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1100001100111100
|
|
word: SLICEC.K0.INIT 1111110011000000
|
|
word: SLICEA.K1.INIT 1100001100111100
|
|
word: SLICED.K0.INIT 1001011010010110
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C64:PLC2
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: A0 V01N0101
|
|
arc: B0 H02E0301
|
|
arc: B1 V02N0101
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 W1_H02E0101
|
|
arc: B6 W1_H02E0101
|
|
arc: C1 V02N0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 H02E0401
|
|
arc: C5 H02E0401
|
|
arc: C6 H02E0401
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0001
|
|
arc: D2 V00T0100
|
|
arc: D3 V00T0100
|
|
arc: D4 H01W0000
|
|
arc: D5 H02E0001
|
|
arc: D6 H01W0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F6
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F2
|
|
word: SLICEA.K0.INIT 1110111000100010
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1100001100111100
|
|
word: SLICEC.K0.INIT 1111110011000000
|
|
word: SLICEC.K1.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C65:PLC2
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 H02E0501
|
|
arc: A4 V00T0000
|
|
arc: A6 N1_V01S0100
|
|
arc: B2 V02N0101
|
|
arc: B3 V02S0101
|
|
arc: B5 V02S0701
|
|
arc: B7 N1_V01S0000
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011010
|
|
word: SLICEC.K1.INIT 1001100110011100
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 1001100110011100
|
|
word: SLICEB.K0.INIT 1001100110011100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R26C66:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: H00L0000 V02S0201
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: A4 V00T0000
|
|
arc: A6 N1_V01S0100
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0301
|
|
arc: B2 H00L0000
|
|
arc: B3 V02S0101
|
|
arc: B5 V02S0501
|
|
arc: B7 N1_V01S0000
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 1001100110011100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R26C67:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: A4 N1_V01S0100
|
|
arc: B0 V00B0000
|
|
arc: B1 V02S0101
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B5 V02S0501
|
|
arc: B6 V00T0000
|
|
arc: B7 N1_V01S0000
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R26C68:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: A4 N1_V01S0100
|
|
arc: A6 H00R0000
|
|
arc: B0 V00T0000
|
|
arc: B1 V02S0101
|
|
arc: B2 N1_V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B5 V02S0501
|
|
arc: B7 N1_V01S0000
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0101010101011010
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 0011001100111100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R26C69:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: B6 N1_V01S0000
|
|
arc: C2 N1_V01S0100
|
|
arc: C6 N1_V02S0201
|
|
arc: D2 F0
|
|
arc: D6 N1_V02S0401
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0201 F2
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R26C70:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: B0 W1_H02E0101
|
|
arc: C0 V02S0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 0000110000001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C71:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: B0 V02S0101
|
|
arc: C0 V02S0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 0011000000110011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C76:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C77:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C82:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R26C83:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R27C41:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
|
|
.tile R27C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R27C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R27C58:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
|
|
.tile R27C59:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: A3 N1_V02S0701
|
|
arc: B2 V02N0101
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 N1_V02S0701
|
|
arc: C2 S1_V02N0601
|
|
arc: C4 S1_V02N0201
|
|
arc: CE1 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: D4 V02N0601
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0601 F4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K0.INIT 0000000011001111
|
|
word: SLICEC.K0.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1001100101100110
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R27C60:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00L0000 H02W0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A1 H02W0701
|
|
arc: A7 V02N0101
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: C0 H02W0601
|
|
arc: C7 E1_H02W0601
|
|
arc: CE0 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V00B0100
|
|
arc: D7 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0000 Q7
|
|
word: SLICED.K1.INIT 1111101001010000
|
|
word: SLICEA.K1.INIT 1110111000100010
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C61:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: A2 V02S0701
|
|
arc: A3 W1_H02E0501
|
|
arc: A4 V02S0101
|
|
arc: A5 W1_H02E0701
|
|
arc: A6 H02E0501
|
|
arc: A7 H00R0000
|
|
arc: B0 V02N0301
|
|
arc: B3 V02S0301
|
|
arc: B4 W1_H02E0101
|
|
arc: B5 V02S0501
|
|
arc: B6 W1_H02E0301
|
|
arc: B7 V00B0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E3_H06E0003 F3
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F4
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F6
|
|
arc: W1_H02W0601 F4
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 1010101010101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R27C62:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A0 V02S0701
|
|
arc: A1 H02E0501
|
|
arc: A2 N1_V02S0501
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V00T0000
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 N1_V02S0301
|
|
arc: A7 H00R0000
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 V02S0301
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 V00B0100
|
|
arc: B5 H02E0301
|
|
arc: B6 N1_V01S0000
|
|
arc: B7 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0201 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F3
|
|
arc: N1_V02N0401 F4
|
|
arc: N1_V02N0501 F7
|
|
arc: N1_V02N0601 F6
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F7
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F0
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R27C63:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: A0 V02S0501
|
|
arc: A1 V02S0701
|
|
arc: A2 H02W0501
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 H02E0501
|
|
arc: A5 V02S0101
|
|
arc: A6 N1_V01S0100
|
|
arc: A7 N1_V02S0301
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 V02S0301
|
|
arc: B3 H00R0000
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H00L0000
|
|
arc: B6 N1_V02S0701
|
|
arc: B7 V00T0000
|
|
arc: E1_H02E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F3
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0203 F4
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R27C64:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
arc: A0 V02S0701
|
|
arc: A1 H00R0000
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0501
|
|
arc: A4 V02S0301
|
|
arc: A5 E1_H02W0701
|
|
arc: A6 V02N0101
|
|
arc: A7 H02W0501
|
|
arc: B0 N1_V02S0301
|
|
arc: B1 V00B0000
|
|
arc: B2 H00R0100
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 V00T0000
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0101 F0
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0401 F4
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0103 F2
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F0
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R27C65:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00L0000
|
|
arc: A4 S1_V02N0101
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V02N0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B5 H02E0301
|
|
arc: B6 V00B0000
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V02N0201
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 V02S0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V02N0601
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 H00R0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 Q5
|
|
arc: H01W0100 F7
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0100 F0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 1111000011001100
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICED.K1.INIT 1111101010100000
|
|
word: SLICED.K0.INIT 1100001100111100
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
|
|
.tile R27C66:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0301 H01E0101
|
|
arc: A1 W1_H02E0701
|
|
arc: A2 S1_V02N0501
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 S1_V02N0101
|
|
arc: B0 H02E0101
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 S1_V02N0501
|
|
arc: B7 V00B0000
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0601
|
|
arc: C2 H02E0401
|
|
arc: C3 H02W0601
|
|
arc: C4 H02E0401
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0201
|
|
arc: C7 V00T0100
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 W1_H02E0201
|
|
arc: D2 V01S0100
|
|
arc: D3 V00T0100
|
|
arc: D4 H01W0000
|
|
arc: D5 V00B0000
|
|
arc: D6 V00B0000
|
|
arc: D7 H00L0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F2
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00T0100 Q1
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0401 F4
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0601 F6
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEA.K1.INIT 1111101000001010
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
word: SLICEC.K1.INIT 1111101010100000
|
|
word: SLICED.K0.INIT 1010010101011010
|
|
word: SLICEC.K0.INIT 1111110011000000
|
|
word: SLICEB.K0.INIT 1010010101011010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R27C67:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A3 N1_V02S0701
|
|
arc: A7 H00R0000
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 V00B0000
|
|
arc: B2 S1_V02N0101
|
|
arc: B5 H00R0000
|
|
arc: C0 H02E0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 H02W0601
|
|
arc: C5 V02S0201
|
|
arc: C7 N1_V02S0201
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 N1_V02S0201
|
|
arc: D2 V01S0100
|
|
arc: D3 V02S0201
|
|
arc: D5 H00R0100
|
|
arc: D7 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0501 F7
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1100001100111100
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
word: SLICEB.K1.INIT 1111101010100000
|
|
word: SLICEA.K1.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1010010101011010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R27C68:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 H02W0401
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A6 H00R0000
|
|
arc: B0 S1_V02N0101
|
|
arc: B2 H00R0000
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 H00R0000
|
|
arc: B5 H00R0000
|
|
arc: C0 H02W0601
|
|
arc: C2 H00L0000
|
|
arc: C3 H02W0601
|
|
arc: C4 V00T0000
|
|
arc: C5 N1_V02S0201
|
|
arc: C6 V00T0000
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 N1_V02S0201
|
|
arc: D3 V01S0100
|
|
arc: D4 N1_V02S0601
|
|
arc: D5 H02E0201
|
|
arc: D6 N1_V02S0601
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0201 F2
|
|
arc: N1_V02N0601 F6
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEC.K0.INIT 1111110011000000
|
|
word: SLICEB.K1.INIT 1111110011000000
|
|
word: SLICED.K0.INIT 1010010101011010
|
|
word: SLICEA.K0.INIT 1100001100111100
|
|
word: SLICEB.K0.INIT 1111110011000000
|
|
word: SLICEC.K1.INIT 1100001100111100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R27C69:PLC2
|
|
arc: H00L0100 V02N0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A0 V02N0501
|
|
arc: B2 V02N0301
|
|
arc: C0 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
word: SLICEA.K0.INIT 0000000010101111
|
|
word: SLICEB.K0.INIT 0011001100000011
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R28C10:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
|
|
.tile R28C16:PLC2
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R28C17:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R28C23:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R28C29:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R28C35:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C3:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R28C40:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
|
|
.tile R28C41:PLC2
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 F0
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 F0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C43:PLC2
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
|
|
.tile R28C44:PLC2
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile R28C45:PLC2
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
|
|
.tile R28C47:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R28C50:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R28C51:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C53:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
|
|
.tile R28C57:PLC2
|
|
arc: C3 S1_V02N0601
|
|
arc: D3 S1_V02N0001
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: F3 F3_SLICE
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R28C58:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: S1_V02S0101 H01E0101
|
|
|
|
.tile R28C59:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0001 E3_H06W0003
|
|
|
|
.tile R28C60:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: A0 H02W0701
|
|
arc: C0 H02W0401
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C61:PLC2
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A3 V00T0000
|
|
arc: A7 V02S0101
|
|
arc: B0 W1_H02E0101
|
|
arc: B2 V02S0301
|
|
arc: B4 V02S0701
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V02S0501
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F6
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 F4
|
|
arc: N1_V01N0001 F3
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0701 F5
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C62:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: A3 V00T0000
|
|
arc: B0 V02S0101
|
|
arc: B1 V00B0000
|
|
arc: B2 V02S0301
|
|
arc: B4 V02S0501
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V02S0701
|
|
arc: B7 H02W0101
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 F4
|
|
arc: N1_V01N0001 F0
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0701 F5
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C63:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: A3 V00T0000
|
|
arc: A7 H02W0501
|
|
arc: B0 V02S0301
|
|
arc: B1 V00B0000
|
|
arc: B2 V02S0101
|
|
arc: B4 V02S0501
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V02S0701
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 F4
|
|
arc: V01S0100 F6
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C64:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A3 V00T0000
|
|
arc: B0 V02S0301
|
|
arc: B1 V00B0000
|
|
arc: B2 V02S0101
|
|
arc: B4 V02S0501
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V02S0701
|
|
arc: B7 H02W0101
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0501 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 F3
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C65:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0101
|
|
arc: A6 V02N0101
|
|
arc: B0 V02S0301
|
|
arc: C4 E1_H02W0601
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 S1_V02N0201
|
|
arc: D4 H02E0201
|
|
arc: D5 V00B0000
|
|
arc: D6 V00B0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0201 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0100 F6
|
|
arc: N1_V01N0101 F4
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010010101011010
|
|
word: SLICEC.K1.INIT 1111101010100000
|
|
word: SLICED.K0.INIT 1010010101011010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R28C66:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 V02N0101
|
|
arc: A2 W1_H02E0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V02N0101
|
|
arc: A6 V02N0101
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 V02N0101
|
|
arc: C0 H00L0100
|
|
arc: C1 N1_V02S0401
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 H02W0601
|
|
arc: C6 H02W0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 V01S0100
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 V00B0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D6 H01W0000
|
|
arc: E1_H01E0101 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 F3
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0201 Q0
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0401 F6
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
word: SLICEB.K0.INIT 1010101011110000
|
|
word: SLICEC.K0.INIT 1111101010100000
|
|
word: SLICEB.K1.INIT 1010010101011010
|
|
word: SLICED.K0.INIT 1111101010100000
|
|
word: SLICEA.K1.INIT 1100001100111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C67:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 W1_H02E0701
|
|
arc: C0 W1_H02E0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1111000010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C68:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R28C69:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: W1_H02W0501 V06S0303
|
|
|
|
.tile R28C9:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R29C11:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R29C15:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R29C17:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C23:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C29:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C35:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C3:PLC2
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
|
|
.tile R29C40:PLC2
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
|
|
.tile R29C41:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R29C47:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R29C54:PLC2
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
|
|
.tile R29C55:PLC2
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
|
|
.tile R29C58:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
|
|
.tile R29C59:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: V00T0000 H02E0201
|
|
arc: B0 H01W0100
|
|
arc: C0 H02W0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000000011110011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R29C5:PLC2
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
|
|
.tile R29C60:PLC2
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: B3 H02W0301
|
|
arc: E1_H01E0001 F3
|
|
arc: F3 F3_SLICE
|
|
word: SLICEB.K1.INIT 0011001100110011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R29C61:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A0 V02N0701
|
|
arc: A2 V02S0701
|
|
arc: A3 H01E0001
|
|
arc: A4 V02S0301
|
|
arc: A5 N1_V01S0100
|
|
arc: B6 V02S0501
|
|
arc: B7 N1_V01S0000
|
|
word: SLICED.K1.INIT 1001100110011100
|
|
word: SLICED.K0.INIT 1001100110011100
|
|
word: SLICEC.K1.INIT 1001100110011010
|
|
word: SLICEC.K0.INIT 1001100110011010
|
|
word: SLICEB.K1.INIT 1001100110011010
|
|
word: SLICEB.K0.INIT 1001100110011010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R29C62:PLC2
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 V02S0701
|
|
arc: A4 V02S0101
|
|
arc: A5 N1_V01S0100
|
|
arc: B1 V00B0000
|
|
arc: B2 V02S0301
|
|
arc: B3 H00L0000
|
|
arc: B6 V02S0501
|
|
arc: B7 V00T0000
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0011001100111100
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0011001100111100
|
|
word: SLICEA.K0.INIT 1001100110011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R29C63:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0000 V02S0001
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: V00B0000 V02S0201
|
|
arc: A0 V02S0701
|
|
arc: A1 H00L0000
|
|
arc: A3 V00B0000
|
|
arc: A4 V02S0301
|
|
arc: A7 N1_V01S0100
|
|
arc: B2 V02S0101
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V02S0501
|
|
word: SLICED.K1.INIT 0101010101011010
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0011001100111100
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0101010101011010
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R29C64:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0000 V02S0201
|
|
arc: A0 V02S0501
|
|
arc: A1 H00L0000
|
|
arc: A3 V00B0000
|
|
arc: A4 V02S0301
|
|
arc: A5 N1_V01S0100
|
|
arc: B2 V02S0101
|
|
arc: B6 V02S0701
|
|
arc: B7 N1_V01S0000
|
|
word: SLICED.K1.INIT 0011001100111100
|
|
word: SLICED.K0.INIT 0011001100111100
|
|
word: SLICEC.K1.INIT 0101010101011010
|
|
word: SLICEC.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 0101010101011010
|
|
word: SLICEB.K0.INIT 0011001100111100
|
|
word: SLICEA.K1.INIT 0101010101011010
|
|
word: SLICEA.K0.INIT 0101010101011010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R29C65:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: B4 E1_H02W0101
|
|
arc: B7 E1_H02W0101
|
|
arc: C4 E1_H02W0401
|
|
arc: C6 V02S0001
|
|
arc: C7 E1_H02W0401
|
|
arc: D4 V02N0601
|
|
arc: D6 F0
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0303 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICEC.K0.INIT 1111110011000000
|
|
word: SLICED.K1.INIT 1100001100111100
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R29C66:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: N1_V02N0101 H02W0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: C0 V02S0401
|
|
arc: C1 V02S0401
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02W0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K1.INIT 0000010100001111
|
|
word: SLICEA.K0.INIT 0000111100000101
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R29C67:PLC2
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 V02S0701
|
|
arc: C0 W1_H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 0000000010101111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R29C68:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
|
|
.tile R29C72:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R29C73:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R29C78:PLC2
|
|
arc: E1_H02E0201 W3_H06E0103
|
|
|
|
.tile R29C79:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R29C80:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
|
|
.tile R29C82:PLC2
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
|
|
.tile R29C85:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
|
|
.tile R29C86:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R29C87:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
|
|
.tile R29C88:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R2C39:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
|
|
.tile R30C57:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R30C60:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
|
|
.tile R30C61:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R30C62:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: B0 H02W0301
|
|
arc: C0 H02W0401
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 1100110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R30C63:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: B0 N1_V02S0101
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C64:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: C0 N1_V02S0601
|
|
arc: C1 V02S0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 N1_V02S0201
|
|
arc: E1_H01E0001 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K1.INIT 1111110000110000
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C65:PLC2
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A0 N1_V02S0701
|
|
arc: C0 H00L0000
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C66:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 H06E0003
|
|
|
|
.tile R30C67:PLC2
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
|
|
.tile R31C19:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R31C3:PLC2
|
|
arc: W1_H02W0701 V06S0203
|
|
|
|
.tile R35C15:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R37C19:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R3C38:PLC2
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R3C41:PLC2
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: W3_H06W0303 S3_V06N0303
|
|
|
|
.tile R3C43:PLC2
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R3C44:PLC2
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
|
|
.tile R3C47:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R3C69:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
|
|
.tile R3C72:PLC2
|
|
arc: N1_V02N0701 H06E0203
|
|
|
|
.tile R41C15:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R43C19:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R47C15:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R49C19:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R4C39:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
|
|
.tile R4C53:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R4C65:PLC2
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R4C69:PLC2
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R53C15:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R55C19:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R59C15:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R5C41:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R5C43:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
|
|
.tile R5C44:PLC2
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
|
|
.tile R61C19:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R65C15:PLC2
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R66C15:PLC2
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
|
|
.tile R67C19:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R68C15:PLC2
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile R6C39:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R6C53:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
|
|
.tile R6C65:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R6C69:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R7C37:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R7C38:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R7C44:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R9C38:PLC2
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
|
|
.tile R9C41:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R9C47:PLC2
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile R9C69:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile TAP_R19C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R19C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R20C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R21C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C31:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C51:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C51:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C51:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C51:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C51:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C51:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C51:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile_group MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 MIB_R22C74:MIB_DSP5 MIB_R22C74:MIB2_DSP5 MIB_R22C75:MIB_DSP6 MIB_R22C75:MIB2_DSP6 MIB_R22C76:MIB_DSP7 MIB_R22C76:MIB2_DSP7 MIB_R22C77:MIB_DSP8 MIB_R22C77:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 MIB_R22C27:MIB_DSP5 MIB_R22C27:MIB2_DSP5 MIB_R22C28:MIB_DSP6 MIB_R22C28:MIB2_DSP6 MIB_R22C29:MIB_DSP7 MIB_R22C29:MIB2_DSP7 MIB_R22C30:MIB_DSP8 MIB_R22C30:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C69:MIB_DSP0 MIB_R22C69:MIB2_DSP0 MIB_R22C70:MIB_DSP1 MIB_R22C70:MIB2_DSP1 MIB_R22C71:MIB_DSP2 MIB_R22C71:MIB2_DSP2 MIB_R22C72:MIB_DSP3 MIB_R22C72:MIB2_DSP3 MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4 MIB_R22C27:MIB_DSP5 MIB_R22C27:MIB2_DSP5 MIB_R22C28:MIB_DSP6 MIB_R22C28:MIB2_DSP6 MIB_R22C29:MIB_DSP7 MIB_R22C29:MIB2_DSP7 MIB_R22C30:MIB_DSP8 MIB_R22C30:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 MIB_R22C36:MIB_DSP5 MIB_R22C36:MIB2_DSP5 MIB_R22C37:MIB_DSP6 MIB_R22C37:MIB2_DSP6 MIB_R22C38:MIB_DSP7 MIB_R22C38:MIB2_DSP7 MIB_R22C39:MIB_DSP8 MIB_R22C39:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C31:MIB_DSP0 MIB_R22C31:MIB2_DSP0 MIB_R22C32:MIB_DSP1 MIB_R22C32:MIB2_DSP1 MIB_R22C33:MIB_DSP2 MIB_R22C33:MIB2_DSP2 MIB_R22C34:MIB_DSP3 MIB_R22C34:MIB2_DSP3 MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C60:MIB_DSP0 MIB_R22C60:MIB2_DSP0 MIB_R22C61:MIB_DSP1 MIB_R22C61:MIB2_DSP1 MIB_R22C62:MIB_DSP2 MIB_R22C62:MIB2_DSP2 MIB_R22C63:MIB_DSP3 MIB_R22C63:MIB2_DSP3 MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C42:MIB_DSP0 MIB_R22C42:MIB2_DSP0 MIB_R22C43:MIB_DSP1 MIB_R22C43:MIB2_DSP1 MIB_R22C44:MIB_DSP2 MIB_R22C44:MIB2_DSP2 MIB_R22C45:MIB_DSP3 MIB_R22C45:MIB2_DSP3 MIB_R22C46:MIB_DSP4 MIB_R22C46:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C31:MIB_DSP0 MIB_R22C31:MIB2_DSP0 MIB_R22C32:MIB_DSP1 MIB_R22C32:MIB2_DSP1 MIB_R22C33:MIB_DSP2 MIB_R22C33:MIB2_DSP2 MIB_R22C34:MIB_DSP3 MIB_R22C34:MIB2_DSP3 MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C22:MIB_DSP0 MIB_R22C22:MIB2_DSP0 MIB_R22C23:MIB_DSP1 MIB_R22C23:MIB2_DSP1 MIB_R22C24:MIB_DSP2 MIB_R22C24:MIB2_DSP2 MIB_R22C25:MIB_DSP3 MIB_R22C25:MIB2_DSP3 MIB_R22C26:MIB_DSP4 MIB_R22C26:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C35:MIB_DSP4 MIB_R22C35:MIB2_DSP4 MIB_R22C36:MIB_DSP5 MIB_R22C36:MIB2_DSP5 MIB_R22C37:MIB_DSP6 MIB_R22C37:MIB2_DSP6 MIB_R22C38:MIB_DSP7 MIB_R22C38:MIB2_DSP7 MIB_R22C39:MIB_DSP8 MIB_R22C39:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4 MIB_R22C56:MIB_DSP5 MIB_R22C56:MIB2_DSP5 MIB_R22C57:MIB_DSP6 MIB_R22C57:MIB2_DSP6 MIB_R22C58:MIB_DSP7 MIB_R22C58:MIB2_DSP7 MIB_R22C59:MIB_DSP8 MIB_R22C59:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4 MIB_R22C56:MIB_DSP5 MIB_R22C56:MIB2_DSP5 MIB_R22C57:MIB_DSP6 MIB_R22C57:MIB2_DSP6 MIB_R22C58:MIB_DSP7 MIB_R22C58:MIB2_DSP7 MIB_R22C59:MIB_DSP8 MIB_R22C59:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C69:MIB_DSP0 MIB_R22C69:MIB2_DSP0 MIB_R22C70:MIB_DSP1 MIB_R22C70:MIB2_DSP1 MIB_R22C71:MIB_DSP2 MIB_R22C71:MIB2_DSP2 MIB_R22C72:MIB_DSP3 MIB_R22C72:MIB2_DSP3 MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C51:MIB_DSP0 MIB_R22C51:MIB2_DSP0 MIB_R22C52:MIB_DSP1 MIB_R22C52:MIB2_DSP1 MIB_R22C53:MIB_DSP2 MIB_R22C53:MIB2_DSP2 MIB_R22C54:MIB_DSP3 MIB_R22C54:MIB2_DSP3 MIB_R22C55:MIB_DSP4 MIB_R22C55:MIB2_DSP4
|
|
enum: MULT18_1.REG_INPUTA_CLK NONE
|
|
enum: MULT18_1.REG_INPUTA_CE CE0
|
|
enum: MULT18_1.REG_INPUTA_RST RST0
|
|
enum: MULT18_1.REG_INPUTB_CLK NONE
|
|
enum: MULT18_1.REG_INPUTB_CE CE0
|
|
enum: MULT18_1.REG_INPUTB_RST RST0
|
|
enum: MULT18_1.REG_INPUTC_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_1.REG_PIPELINE_CE CE0
|
|
enum: MULT18_1.REG_PIPELINE_RST RST0
|
|
enum: MULT18_1.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_1.CLK0_DIV ENABLED
|
|
enum: MULT18_1.CLK1_DIV ENABLED
|
|
enum: MULT18_1.CLK2_DIV ENABLED
|
|
enum: MULT18_1.CLK3_DIV ENABLED
|
|
enum: MULT18_1.GSR ENABLED
|
|
enum: MULT18_1.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_1.RESETMODE SYNC
|
|
enum: MULT18_1.MODE MULT18X18D
|
|
enum: MULT18_1.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_1.CLK0MUX CLK0
|
|
enum: MULT18_1.CLK1MUX CLK1
|
|
enum: MULT18_1.CLK2MUX CLK2
|
|
enum: MULT18_1.CLK3MUX CLK3
|
|
enum: MULT18_1.CE0MUX CE0
|
|
enum: MULT18_1.CE1MUX CE1
|
|
enum: MULT18_1.CE2MUX CE2
|
|
enum: MULT18_1.CE3MUX CE3
|
|
enum: MULT18_1.RST0MUX RST0
|
|
enum: MULT18_1.RST1MUX RST1
|
|
enum: MULT18_1.RST2MUX RST2
|
|
enum: MULT18_1.RST3MUX RST3
|
|
|