FPGA-Neural

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micheleandClaude Sonnet 5 cbd16dd727 docs: sync physical/architecture docs with EXP-0081/0082 reality, add 32-bit vs dual-channel analysis

- PHYSICAL_REALIZATION.md: replace stale "1 tile = 1 burst" layout
  description with the real EXP-0081/0082 "2 tiles = 1 burst" convention;
  add EXP-0082 signoff row and history table.
- ARCHITECTURE_ANALYSIS.md: mark §5.1 (denser activation packing) DONE with
  real re-measured numbers (bandwidth ceiling fraction 25%->50%, WNS
  +0.030->+0.068ns); add §5.4, the real device-data-backed comparison of
  32-bit single-channel widening vs a second independent DDR3 channel
  (decided: 32-bit widening, per real DQS/bank pin-conflict analysis);
  update scaling-path recommendation to reflect the user's final directive
  (widen channel -> build DDRManager -> N=2/4/8/16 tests, N=8 target, N=16
  documentary).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-20 10:07:16 +02:00

ARCHITECTURE_ANALYSIS.md

docs: sync physical/architecture docs with EXP-0081/0082 reality, add 32-bit vs dual-channel analysis

2026-09-20 10:07:16 +02:00

FPGA-Neural-Flash-Subsystem-Verification.md

fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7)

2026-09-04 10:16:31 +02:00

PHYSICAL_REALIZATION.md

docs: sync physical/architecture docs with EXP-0081/0082 reality, add 32-bit vs dual-channel analysis

2026-09-20 10:07:16 +02:00

v2-description.md

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00