micheleandClaude Sonnet 5
ca17765fe3
Found a real, previously-masked bug in spi_host_bridge_v3.v's physical layer (inherited unchanged from V1/V2): the bit_count==0 MISO bypass corrupts the last bit of any multi-byte response whose value happens to end in a 1 -- every prior test's response data coincidentally ended in 0, hiding it until the new DEVICE_ID register (0x...01) exposed it via a real bit-exact mismatch. Fixed by removing the bypass (verified unnecessary for this protocol's actual usage). Added REG_WRITE/REG_READ opcodes (0x30/0x31) and a register file (DEVICE_ID/CONTROL/STATUS/N_SLOTS) for general device control beyond job submission, per explicit user request. Full regression: 38/38 PASS, including new cases specifically targeting the bit-corruption bug for both REG_READ and READ_MEM. New hardware/v3/constraints/n2_system_ddr3_top.xdc: reserves the FPGA's dedicated Master-SPI config-flash pins (found colliding with auto-placed design ports in the real routed checkpoint) and assigns the neural-processor management SPI to real, verified-free, edge- adjacent pins on xc7a100tcsg324-2. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
45 lines
2.4 KiB
Tcl
45 lines
2.4 KiB
Tcl
# ============================================================
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# V3 -- top-level pin/IOSTANDARD constraints for n2_system_ddr3_top.v,
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# real xc7a100tcsg324-2, board is the user's own custom design (bare
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# chip + DDR3, no dev board). DDR3 pins themselves are NOT here --
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# those come from the MIG-generated mig_7series_0.xdc (dictated by
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# the FPGA's internal DDR3 PHY hardware, not a free choice).
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#
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# Verified against the real device via a routed checkpoint query
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# (open_checkpoint + get_package_pins/get_ports on n2_system_ddr3_
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# top_routed.dcp), not guessed from a datasheet table.
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# ============================================================
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# ---- reserve the dedicated Master-SPI configuration-flash pins
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# (bank 14) for a FUTURE external config flash -- prevents Vivado's
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# auto-placement from ever landing one of THIS design's own ports on
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# them (it already had, by accident, before this constraint existed:
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# job_out_done on L13/FCS_B, a result bit on R16/RDWR_B, another on
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# V15/CSI_B). These pins are not driven by this design at all; they
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# stay free for the flash CCLK/D00_MOSI/D01_DIN/FCS_B/EMCCLK/RDWR_B/
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# CSI_B wiring described in the accompanying configuration writeup.
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set_property PROHIBIT true [get_package_pins {K17 K18 L13 L16 R16 V15}]
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# ---- neural-processor management SPI (-> spi_host_bridge_v3.v):
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# job submission + register file. Bank 15, column A/B (package edge,
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# physically adjacent pins for short/easy PCB routing), well clear of
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# both DDR3 (banks 34/35) and the reserved config-flash pins above.
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# IOSTANDARD assumes bank 15 is powered at 3.3V on the custom board --
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# change to match whatever VCCO the user's own power plan uses for
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# that bank.
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set_property PACKAGE_PIN A15 [get_ports sclk]
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set_property PACKAGE_PIN B16 [get_ports mosi]
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set_property PACKAGE_PIN B17 [get_ports miso]
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set_property PACKAGE_PIN A16 [get_ports cs_n]
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set_property IOSTANDARD LVCMOS33 [get_ports sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports mosi]
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set_property IOSTANDARD LVCMOS33 [get_ports miso]
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set_property IOSTANDARD LVCMOS33 [get_ports cs_n]
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# ---- sys_rst: not part of the DDR3 MIG's own pin set (that's
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# sys_rst too, but MIG's XDC only constrains the DDR3-facing timing,
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# not necessarily IOSTANDARD for every board variant) -- pin left to
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# auto-placement for now (low pin-count, no real board decision yet
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# on where the reset source sits); explicitly constrain once the PCB
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# layout for the reset circuit (button/supervisor IC) is decided.
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