micheleandClaude Sonnet 5
685a4d6cfe
New brief (N=8 timing closure, LFE5U-85F retarget, 4/8/16 x 1/2-bank SDRAM sweep). Phase 0: no RTL changes, only measure the current baseline. ERR-0030: constraints/v2_unified.lpf's FREQUENCY PORT "clk" was still 80MHz, a leftover from the STEP19 freeze, never updated to the project's real 64MHz target -- fixed (LPF only, zero RTL/datapath effect). ERR-0031 (bigger one): the first two synthesis attempts targeted nms_neural_multiprocessor_sdram_unified.v, which is NOT the real board-level top -- it's an obsolete wrapper only exercised by one testbench now. The real target is fpga_neural_v2_top.v (adds the real PLL, reset_sync, spi_host_bridge, and a second arbitration level), which is what actually goes through synthesis+P&R for hardware. Re-targeted correctly, matched against constraints/v2_board_top.lpf (all 17 ports real-ball-assigned). An N_SLOTS=8 P&R attempt against the WRONG (wrapper) target ran for 2h42m without converging on a single seed; discarded rather than trusted. N_SLOTS=8 baseline deferred by explicit user request until N_SLOTS=4 is fully understood -- re-attempt against the correct fpga_neural_v2_top target with an agreed time budget. Result (EXP-0049, fresh 8-seed nextpnr-ecp5 P&R, real pins): N_SLOTS=4 8/8 PASS at 64MHz, worst-seed 81.20MHz, mean 91.05MHz. Higher than DEC-0042's historical worst/best (64.55/77.21MHz) despite identical RTL -- disclosed, unresolved (leading hypothesis: nextpnr-ecp5 build/version difference), adopted as the operative baseline for this session's toolchain going forward. Full writeup in errors.log/timing.log/ experiments.log (EXP-0049). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
98 lines
5.6 KiB
Plaintext
98 lines
5.6 KiB
Plaintext
// FPGA-Neural V2 -- STEP19 single-SDRAM hardware freeze.
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// Target: nms_neural_multiprocessor_sdram_unified (N_SLOTS=4)
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// FPGA: LFE5U-45F-8BG381, package CABGA381, speed grade -8
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//
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// STATUS: PARTIAL, now with real ball-level SDRAM assignment (see
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// below for how this improved after the freeze's own documentation
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// was drafted -- the real Lattice pinout CSV, FPGA-SC-02034-3-0-
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// ECP5U-45-Pinout.csv rev 3.0, was found to already be on disk at
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// ~/Downloads/, and its own summary at docs/pinouts.md (repo root)
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// already gives real JTAG/config/power ball assignments -- neither
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// was invented here).
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//
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// - clk/rst: reuse hardware/v1/constraints/spi_neuron_top.lpf's own
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// real, already-validated ball assignment for the SAME FPGA/
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// package (H5, B4) -- the SAME physical signals, zero
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// reinterpretation.
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// - sdram_*: real balls from banks 6/7 of the same official CSV,
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// selected as plain-GPIO pads (no PLL/PCLK dual function, avoiding
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// balls reserved for clock-capable inputs) -- a real, sourced,
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// but NOT YET electrically cross-verified assignment (VCCIO6/7
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// bank voltage compatibility with the AS4C4M16SA-6TIN's own
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// LVCMOS33 requirement should be confirmed against the real
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// Lattice hardware checklist before board layout; not done this
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// round).
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//
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// STILL NOT constrained: the 110-pin reg_* host bus -- deliberately
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// NOT ball-assigned yet, since that bus is itself a real, separate
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// BLOCKER (a raw test-harness parallel bus, not a physical protocol --
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// see PINOUT.md); assigning balls to an interface that will be
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// redesigned would be premature, wasted work.
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BLOCK ASYNCPATHS;
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BLOCK RESETPATHS;
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// Updated from the STEP19 freeze's original 80 MHz to the project's
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// current 64 MHz target (see decisions.log DEC-0038+/errors.log
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// ERR-0029/DEC-0042): this file's own FREQUENCY directive was never
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// bumped down when the achievable target moved from 80 to 64 MHz,
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// silently making every nextpnr PASS/FAIL label using this LPF report
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// against the wrong, stale bar (only the achieved MHz number itself
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// was real; the FAIL/PASS annotation next to it was not) -- see
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// errors.log for the disclosed fix.
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FREQUENCY PORT "clk" 64 MHZ;
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LOCATE COMP "clk" SITE "H5";
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IOBUF PORT "clk" IO_TYPE=LVCMOS33;
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LOCATE COMP "rst" SITE "B4";
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IOBUF PORT "rst" IO_TYPE=LVCMOS33;
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// ---- SDRAM interface (37 signals), real balls, banks 6/7 ----
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LOCATE COMP "sdram_cke" SITE "B5"; IOBUF PORT "sdram_cke" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_cs_n" SITE "C5"; IOBUF PORT "sdram_cs_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_ras_n" SITE "C4"; IOBUF PORT "sdram_ras_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_cas_n" SITE "A3"; IOBUF PORT "sdram_cas_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_we_n" SITE "B3"; IOBUF PORT "sdram_we_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_ba[0]" SITE "E4"; IOBUF PORT "sdram_ba[0]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_ba[1]" SITE "C3"; IOBUF PORT "sdram_ba[1]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[0]" SITE "D5"; IOBUF PORT "sdram_a[0]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[1]" SITE "D3"; IOBUF PORT "sdram_a[1]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[2]" SITE "F4"; IOBUF PORT "sdram_a[2]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[3]" SITE "E5"; IOBUF PORT "sdram_a[3]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[4]" SITE "E3"; IOBUF PORT "sdram_a[4]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[5]" SITE "F5"; IOBUF PORT "sdram_a[5]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[6]" SITE "A2"; IOBUF PORT "sdram_a[6]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[7]" SITE "B1"; IOBUF PORT "sdram_a[7]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[8]" SITE "C2"; IOBUF PORT "sdram_a[8]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[9]" SITE "C1"; IOBUF PORT "sdram_a[9]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[10]" SITE "D2"; IOBUF PORT "sdram_a[10]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_a[11]" SITE "D1"; IOBUF PORT "sdram_a[11]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[0]" SITE "E1"; IOBUF PORT "sdram_dq[0]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[1]" SITE "G5"; IOBUF PORT "sdram_dq[1]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[2]" SITE "H3"; IOBUF PORT "sdram_dq[2]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[3]" SITE "J5"; IOBUF PORT "sdram_dq[3]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[4]" SITE "K3"; IOBUF PORT "sdram_dq[4]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[5]" SITE "K2"; IOBUF PORT "sdram_dq[5]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[6]" SITE "H1"; IOBUF PORT "sdram_dq[6]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[7]" SITE "J1"; IOBUF PORT "sdram_dq[7]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[8]" SITE "K1"; IOBUF PORT "sdram_dq[8]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[9]" SITE "K4"; IOBUF PORT "sdram_dq[9]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[10]" SITE "L4"; IOBUF PORT "sdram_dq[10]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[11]" SITE "L5"; IOBUF PORT "sdram_dq[11]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[12]" SITE "M5"; IOBUF PORT "sdram_dq[12]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[13]" SITE "M4"; IOBUF PORT "sdram_dq[13]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[14]" SITE "N4"; IOBUF PORT "sdram_dq[14]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dq[15]" SITE "N5"; IOBUF PORT "sdram_dq[15]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dqm[0]" SITE "P5"; IOBUF PORT "sdram_dqm[0]" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdram_dqm[1]" SITE "N3"; IOBUF PORT "sdram_dqm[1]" IO_TYPE=LVCMOS33;
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// ---- OPEN: reg_valid, reg_ready, reg_node_id, reg_required,
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// reg_producer_ids, reg_x_base, reg_w_base, reg_n_tiles,
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// reg_result_addr (110 signals, the raw host/registration bus) --
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// deliberately unassigned, see file header. ----
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