michele
cfd5e98a0e
tools/fpga_benchmark.py: parametric Yosys + nextpnr-ecp5 benchmark harness for the LFE5U-45F-8BG381 (speed grade -8, 80 MHz target), sweeping PARALLEL over the neuron layer and parsing Fmax/LUT4/DFF/DSP utilization out of the nextpnr report into JSON/CSV. synth/ecp5/p2, p4, p8: real synthesis+PnR results backing the same-price-tier FPGA comparison (P2: 87.88 MHz PASS, P4: 75.01 MHz FAIL, P8: 147.62 MHz PASS -- non-monotonic, dominated by placement noise since the whole design uses <2% of the device's LUT4 fabric at every setting, and P8 notably maps to 0 DSP blocks vs 8/16 for P2/P4). synth/ecp5/top.v: benchmark harness top-level, reworked to generate deterministic non-constant X/weights/bias via `keep`-attributed generate blocks so Yosys can't constant-fold the datapath away. Also adds .gitignore for Python's __pycache__/*.pyc.
11778 lines
259 KiB
Plaintext
11778 lines
259 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C30:CIB_EBR
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arc: N1_V02N0201 N1_V01S0000
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R11C1:CIB_LR
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arc: JA0 E1_H02W0501
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arc: JA3 E1_H02W0701
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arc: S1_V02S0501 E3_H06W0303
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R11C89:CIB_LR
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arc: JA0 N1_V02S0701
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arc: S1_V02S0701 W1_H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R13C1:CIB_LR
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arc: JA3 N1_V02S0501
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arc: S3_V06S0003 H06W0003
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arc: S3_V06S0103 N3_V06S0103
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enum: CIB.JB3MUX 0
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.tile CIB_R13C89:CIB_LR
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arc: JA0 N1_V02S0701
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enum: CIB.JB0MUX 0
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.tile CIB_R16C89:CIB_LR
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R19C1:CIB_LR
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0203 N3_V06S0103
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.tile CIB_R1C15:CIB
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arc: JA0 H02W0501
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arc: S3_V06S0203 E3_H06W0203
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enum: CIB.JB0MUX 0
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.tile CIB_R1C16:CIB
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arc: S3_V06S0003 E3_H06W0003
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arc: W1_H02W0501 S1_V02N0501
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.tile CIB_R1C18:CIB
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arc: S3_V06S0203 H06W0203
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.tile CIB_R1C19:CIB
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arc: S3_V06S0003 H06W0003
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.tile CIB_R1C20:CIB
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arc: JA0 V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C21:CIB
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arc: S1_V02S0101 E3_H06W0103
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arc: S3_V06S0103 E3_H06W0103
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R1C22:CIB
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arc: E1_H02E0701 S1_V02N0701
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arc: S3_V06S0003 JQ0
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C23:CIB
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arc: E1_H02E0701 V01N0101
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C24:CIB
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arc: S1_V02S0101 H06W0103
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arc: S3_V06S0103 H06W0103
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.tile CIB_R1C25:CIB
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arc: JA0 W1_H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C27:CIB
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C29:CIB
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arc: JA0 S1_V02N0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C31:CIB
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arc: E1_H02E0301 V06N0003
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.tile CIB_R1C32:CIB
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arc: H00L0100 H02E0301
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arc: JA0 H00L0100
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enum: CIB.JB0MUX 0
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.tile CIB_R1C33:CIB
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arc: S3_V06S0003 E3_H06W0003
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C39:CIB
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C41:CIB
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arc: E1_H02E0701 V06N0203
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.tile CIB_R1C42:CIB
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arc: E1_H01E0101 JQ0
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arc: E1_H02E0501 V02N0501
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.tile CIB_R1C43:CIB
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arc: E3_H06E0303 H01E0101
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arc: JA0 W1_H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C44:CIB
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arc: JA0 W1_H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C45:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C47:CIB
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arc: JA0 E1_H02W0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C48:CIB
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arc: JD7 E1_H01W0100
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.tile CIB_R1C49:CIB
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arc: H01W0100 W3_H06E0303
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arc: JA0 V02N0701
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arc: W1_H02W0701 V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C50:CIB
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arc: JA0 V02N0701
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enum: CIB.JB0MUX 0
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.tile CIB_R1C64:CIB
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arc: E1_H02E0701 S3_V06N0203
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.tile CIB_R1C66:CIB
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arc: E1_H02E0701 W1_H02E0701
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.tile CIB_R1C67:CIB
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R25C1:CIB_LR
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arc: S1_V02S0701 N3_V06S0203
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arc: V01S0000 N3_V06S0103
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.tile CIB_R26C1:CIB_LR
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arc: JA0 E1_H02W0501
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arc: JA3 E1_H02W0501
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arc: S1_V02S0501 E1_H01W0100
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arc: S3_V06S0203 N1_V01S0000
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enum: CIB.JB3MUX 0
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enum: CIB.JB0MUX 0
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.tile CIB_R26C89:CIB_LR
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arc: JA3 V02N0501
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enum: CIB.JB3MUX 0
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.tile CIB_R27C1:CIB_LR
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arc: S1_V02S0701 N1_V02S0701
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.tile CIB_R27C89:CIB_LR
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arc: N1_V02N0501 W3_H06E0303
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arc: S1_V02S0701 H02E0701
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.tile CIB_R28C1:CIB_LR
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arc: JA0 N1_V02S0501
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arc: JA3 N1_V02S0501
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R28C89:CIB_LR
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arc: JA3 W1_H02E0701
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enum: CIB.JB3MUX 0
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.tile CIB_R29C1:CIB_LR
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arc: JA0 N1_V02S0701
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arc: JA3 N1_V02S0701
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arc: S1_V02S0501 H06W0303
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R29C89:CIB_LR
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arc: JA3 N1_V02S0701
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arc: S1_V02S0501 H06E0303
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enum: CIB.JB3MUX 0
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.tile CIB_R31C1:CIB_LR
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arc: JA0 N1_V02S0501
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arc: JA3 E1_H02W0501
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arc: S1_V02S0701 V01N0101
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enum: CIB.JB3MUX 0
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enum: CIB.JB0MUX 0
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.tile CIB_R31C89:CIB_LR
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arc: JA3 N1_V02S0501
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enum: CIB.JB3MUX 0
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.tile CIB_R32C1:CIB_LR
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arc: JA0 V02S0701
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arc: JA3 V02S0701
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arc: N1_V01N0101 N3_V06S0203
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arc: S1_V02S0701 N3_V06S0203
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R34C1:CIB_LR_S
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arc: JA0 N1_V02S0701
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enum: CIB.JB0MUX 0
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.tile CIB_R5C1:CIB_PLL1
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R5C89:CIB_PLL1
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R70C18:CIB
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arc: JA0 N1_V02S0501
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enum: CIB.JB0MUX 0
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.tile CIB_R70C3:CIB_PLL3
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R70C42:VCIB_DCU0
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C43:VCIB_DCUA
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C44:VCIB_DCUB
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C45:VCIB_DCUC
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C46:VCIB_DCUD
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enum: CIB.JA1MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C47:VCIB_DCUF
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C48:VCIB_DCU3
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C49:VCIB_DCU2
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C50:VCIB_DCUG
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C51:VCIB_DCUH
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C52:VCIB_DCUI
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C53:VCIB_DCU1
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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.tile CIB_R70C69:VCIB_DCU0
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C6:CIB_EFB0
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enum: CIB.JB3MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C70:VCIB_DCUA
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C71:VCIB_DCUB
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R7C1:CIB_LR
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile CIB_R7C89:CIB_LR
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
|
|
.tile CIB_R9C89:CIB_LR
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
|
|
.tile MIB_R0C15:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C20:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C22:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C23:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C25:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C29:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C32:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C44:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C45:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C47:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C49:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C50:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C67:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C12:EBR_SPINE_UL1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R11C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R11C90:PICR0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R12C0:PICL1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R12C90:PICR1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R13C0:PICL2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R13C90:PICR2
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R15C90:PICR1_DQS0
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R16C90:PICR2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C15:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C20:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C22:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C23:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C25:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C29:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C32:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C44:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C45:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C47:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C49:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C50:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C67:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C0:PICL0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C90:PICR0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C0:PICL1_DQS0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C90:PICR1_DQS0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C0:PICL0_DQS2
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C0:PICL1_DQS3
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C0:PICL2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile R11C11:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R11C13:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R11C15:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
|
|
.tile R11C17:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: A0 H02W0701
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 W1_H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 S1_V02N0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V00T0100 F1
|
|
arc: V01S0000 F0
|
|
word: SLICEA.K1.INIT 1111000011111111
|
|
word: SLICEA.K0.INIT 1010000010100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R11C18:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0000 H02W0001
|
|
arc: A2 F5
|
|
arc: A5 E1_H01W0000
|
|
arc: B5 H00L0000
|
|
arc: C1 H00L0100
|
|
arc: C5 V00T0000
|
|
arc: C7 H01E0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V01S0100
|
|
arc: D2 Q2
|
|
arc: D5 H00L0100
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 F7
|
|
arc: H01W0000 Q2
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICED.K1.INIT 0000111100000000
|
|
word: SLICEB.K0.INIT 0101010110101010
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0000111111110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R11C19:PLC2
|
|
arc: H00R0100 H02E0501
|
|
arc: A1 H00L0100
|
|
arc: A2 H00L0100
|
|
arc: A4 V00T0000
|
|
arc: A5 V02N0301
|
|
arc: A7 V00T0100
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B5 E1_H02W0301
|
|
arc: B7 V00T0000
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 E1_H02W0601
|
|
arc: C4 V00T0100
|
|
arc: C5 H02W0401
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 H02E0001
|
|
arc: D4 H02E0001
|
|
arc: D5 W1_H02E0001
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0601 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: LSR1 H02W0501
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0201 F2
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F2
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110101010101010
|
|
word: SLICEB.K0.INIT 0000000001000000
|
|
word: SLICEA.K0.INIT 0011110011110000
|
|
word: SLICED.K1.INIT 0000000000010000
|
|
word: SLICEC.K0.INIT 0000000000000101
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C20:PLC2
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0501
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A1 V01N0101
|
|
arc: B1 V01N0001
|
|
arc: C1 V02N0601
|
|
arc: D1 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: S1_V02S0301 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R11C21:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 V01N0101
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 V00T0000
|
|
arc: A5 V00T0000
|
|
arc: A6 E1_H02W0701
|
|
arc: B0 V00T0000
|
|
arc: B1 H00R0100
|
|
arc: B2 H00L0000
|
|
arc: B3 H00L0000
|
|
arc: C0 H00L0000
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 V00B0100
|
|
arc: C5 V00B0100
|
|
arc: C7 V00B0100
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 E1_H02W0001
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR1 V00T0100
|
|
arc: M0 H02E0601
|
|
arc: M1 H02W0001
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
word: SLICEA.K0.INIT 1001000101010101
|
|
word: SLICEA.K1.INIT 0100001100110011
|
|
word: SLICEB.K0.INIT 0101010101010100
|
|
word: SLICEB.K1.INIT 0101010101010001
|
|
word: SLICEC.K0.INIT 1010010100001111
|
|
word: SLICEC.K1.INIT 1010010100001111
|
|
word: SLICED.K0.INIT 0101010101010101
|
|
word: SLICED.K1.INIT 0000111100001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R11C22:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: A0 H00L0000
|
|
arc: A1 S1_V02N0701
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 V00T0000
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 S1_V02N0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H02W0401
|
|
arc: C2 V02N0601
|
|
arc: C3 H02W0401
|
|
arc: C4 V02N0001
|
|
arc: C5 H02W0401
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0201
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 S1_V02N0401
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 S1_V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR1 H02E0501
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0701 Q7
|
|
word: SLICED.K1.INIT 0000000011111111
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
word: SLICEA.K0.INIT 1000001100110011
|
|
word: SLICEA.K1.INIT 0001010110010101
|
|
word: SLICEB.K0.INIT 0101010101010100
|
|
word: SLICEB.K1.INIT 0011001000110011
|
|
word: SLICEC.K0.INIT 1010000001011111
|
|
word: SLICEC.K1.INIT 1010000001011111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R11C23:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A1 V02N0701
|
|
arc: B0 V01N0001
|
|
arc: B1 S1_V02N0301
|
|
arc: C0 H02E0601
|
|
arc: C1 H00L0100
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K0.INIT 0011111111000000
|
|
word: SLICEA.K1.INIT 1111111111111110
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R11C24:PLC2
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
|
|
.tile R11C27:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R11C33:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R11C39:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R11C3:PLC2
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
|
|
.tile R11C45:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R11C51:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R11C57:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R11C5:PLC2
|
|
arc: W1_H02W0601 E3_H06W0303
|
|
|
|
.tile R11C63:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R11C69:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R11C75:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R11C7:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R11C81:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R11C87:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R12C17:PLC2
|
|
arc: B0 V02N0101
|
|
arc: C0 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000110011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R12C18:PLC2
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A1 V01N0101
|
|
arc: A6 H00L0000
|
|
arc: B1 E1_H02W0101
|
|
arc: B6 E1_H02W0101
|
|
arc: C1 H00L0000
|
|
arc: C6 V01N0101
|
|
arc: D1 E1_H02W0001
|
|
arc: D6 E1_H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00L0100
|
|
arc: M6 E1_H02W0401
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R12C19:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 H02W0301
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: A1 V02N0701
|
|
arc: B1 E1_H01W0100
|
|
arc: C1 E1_H01W0000
|
|
arc: D1 H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M1 H00L0100
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0000
|
|
arc: M4 H02W0401
|
|
arc: M5 H00L0100
|
|
arc: M6 H02W0401
|
|
arc: S1_V02S0101 F3
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R12C20:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: V00T0100 V02N0501
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 F5
|
|
arc: A4 V00B0000
|
|
arc: A5 V00B0000
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 N1_V01N0001
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: D2 Q2
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D5 H02E0201
|
|
arc: E1_H01E0101 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0601 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEC.K1.INIT 1010000000000000
|
|
word: SLICEC.K0.INIT 0101101010101010
|
|
word: SLICEA.K1.INIT 0101010110101010
|
|
word: SLICEA.K0.INIT 0101101011110000
|
|
word: SLICEB.K1.INIT 0011001111001100
|
|
word: SLICEB.K0.INIT 0111111110000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R12C21:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: V00T0100 V02S0501
|
|
arc: A5 V02N0101
|
|
arc: A7 H00L0000
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B3 E1_H02W0301
|
|
arc: B5 V02N0501
|
|
arc: B7 V02N0701
|
|
arc: C1 V02S0601
|
|
arc: C2 H00L0000
|
|
arc: C5 E1_H01E0101
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: D2 V02N0201
|
|
arc: D3 V02S0001
|
|
arc: D5 V02N0401
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 H02E0501
|
|
arc: M4 E1_H02W0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 F4
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0201 Q2
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 0011001111001100
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 1000000100000011
|
|
word: SLICEA.K1.INIT 0000000011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R12C22:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0000 H02E0201
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 H02W0101
|
|
arc: A1 S1_V02N0701
|
|
arc: A5 V00T0100
|
|
arc: A7 H00L0000
|
|
arc: B1 E1_H01W0100
|
|
arc: B5 S1_V02N0501
|
|
arc: C0 V02S0601
|
|
arc: C1 V02S0601
|
|
arc: C2 V02S0601
|
|
arc: C3 V02S0601
|
|
arc: C5 V00T0000
|
|
arc: C7 V02N0001
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D2 H02W0001
|
|
arc: D3 H02W0001
|
|
arc: D5 H00R0100
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0701 F5
|
|
arc: S3_V06S0203 F7
|
|
arc: V01S0000 F7
|
|
word: SLICED.K1.INIT 1010000000000000
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000111
|
|
word: SLICEA.K0.INIT 0000000000001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R12C23:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: A1 H02E0501
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 S1_V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 H01E0101
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q1
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0110110011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R13C10:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R13C15:PLC2
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C16:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R13C17:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R13C18:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: B1 Q1
|
|
arc: C1 H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00T0100
|
|
arc: E1_H01E0101 Q1
|
|
arc: F1 F1_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K1.INIT 0000111100001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R13C19:PLC2
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A1 V02N0501
|
|
arc: A3 V00B0000
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V02N0301
|
|
arc: A7 E1_H02W0701
|
|
arc: B1 S1_V02N0301
|
|
arc: B3 S1_V02N0101
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: C1 V02N0601
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0001
|
|
arc: C7 V02S0001
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H00R0000
|
|
arc: D3 H02E0201
|
|
arc: D4 V02N0601
|
|
arc: D5 V00B0000
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0301 F1
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: LSR1 V00B0100
|
|
arc: M0 H02E0601
|
|
arc: M1 H00L0100
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 Q4
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 0110110011001100
|
|
word: SLICED.K1.INIT 1010101011111010
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R13C20:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: S3_V06S0003 H01E0001
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 H00L0000
|
|
arc: A1 H00L0000
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 S1_V02N0101
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: C3 V02N0401
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 S1_V02N0201
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0000
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R13C21:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0701
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: C1 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 S1_V02N0201
|
|
arc: C7 S1_V02N0201
|
|
arc: D0 V02S0001
|
|
arc: D1 S1_V02N0001
|
|
arc: D2 V02S0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: D6 V00B0000
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: N1_V02N0101 F3
|
|
word: SLICED.K1.INIT 0000000000001111
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 0000000000001111
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 0000000001010101
|
|
word: SLICEA.K1.INIT 1000000100000101
|
|
word: SLICEA.K0.INIT 0000000000110011
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R13C22:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0301
|
|
arc: A3 S1_V02N0501
|
|
arc: B3 W1_H02E0101
|
|
arc: C3 H02E0601
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 H01E0101
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0111111111111111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R13C23:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: A1 V02S0501
|
|
arc: B1 V02S0101
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02S0201
|
|
arc: D4 H00R0100
|
|
arc: D5 H00R0100
|
|
arc: D6 H00R0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H00R0100 Q7
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q7
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M3 H02E0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0701 Q7
|
|
word: SLICEB.K0.INIT 1111000011110000
|
|
word: SLICEB.K1.INIT 1111000011110000
|
|
word: SLICEC.K0.INIT 1111111100000000
|
|
word: SLICEC.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 1111111100000000
|
|
word: SLICED.K1.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 0111100011110000
|
|
word: SLICEA.K0.INIT 1111000011110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R13C24:PLC2
|
|
arc: W1_H02W0001 H01E0001
|
|
|
|
.tile R13C28:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R13C34:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R13C40:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R13C46:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R13C4:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R13C52:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R13C58:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R13C64:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile R13C70:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R13C76:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R13C82:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R13C88:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R14C18:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: V00T0100 H02W0101
|
|
arc: B1 Q1
|
|
arc: C0 N1_V01N0001
|
|
arc: C1 N1_V01N0001
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00T0100
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
word: SLICEA.K1.INIT 0011110011001100
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R14C19:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A1 V01N0101
|
|
arc: B1 V01N0001
|
|
arc: C1 V02N0601
|
|
arc: D1 N1_V01S0000
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H01E0001
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0100
|
|
arc: V01S0000 F3
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R14C20:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A1 V02N0501
|
|
arc: B1 W1_H02E0301
|
|
arc: C1 H02E0601
|
|
arc: D1 V02N0201
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R14C21:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: B1 V01N0001
|
|
arc: C1 V02N0601
|
|
arc: D1 S1_V02N0201
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: M2 H02E0601
|
|
arc: M3 H00L0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M6 H02E0401
|
|
arc: N1_V01N0001 F3
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R14C22:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: V00T0000 H02E0201
|
|
arc: A1 V01N0101
|
|
arc: B0 H02W0101
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0101
|
|
arc: B3 H02W0101
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 V02N0601
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: D1 H02W0001
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0000
|
|
arc: N1_V02N0301 F1
|
|
word: SLICEB.K1.INIT 0000001100000011
|
|
word: SLICEB.K0.INIT 0000001100000011
|
|
word: SLICEA.K1.INIT 1000000000010011
|
|
word: SLICEA.K0.INIT 0000001100000011
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R14C23:PLC2
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: B0 H01W0100
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 0011110011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R15C16:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R15C19:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A0 F7
|
|
arc: A3 N1_V02S0701
|
|
arc: C0 E1_H01W0000
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D3 V01S0100
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0301 Q3
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 0101111110100000
|
|
word: SLICEB.K1.INIT 0101010110101010
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R15C20:PLC2
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: B1 Q1
|
|
arc: C0 H00L0000
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V01S0100
|
|
arc: D2 Q2
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: V01S0100 Q2
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0011110011001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R15C21:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A0 E1_H01E0001
|
|
arc: A2 F5
|
|
arc: A4 F5
|
|
arc: A7 H00L0000
|
|
arc: B0 V01N0001
|
|
arc: B5 H02E0101
|
|
arc: B7 H02E0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C5 W1_H02E0401
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 Q2
|
|
arc: D4 H01W0000
|
|
arc: D5 H02E0201
|
|
arc: D6 H01W0000
|
|
arc: D7 H02E0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 F6
|
|
arc: V01S0000 F4
|
|
word: SLICEC.K0.INIT 1010101000000000
|
|
word: SLICEA.K0.INIT 0000111100001000
|
|
word: SLICED.K1.INIT 1000000100000101
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 0101010110101010
|
|
word: SLICEC.K1.INIT 1100000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R15C22:PLC2
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: V00T0000 H02W0001
|
|
arc: B0 H02E0101
|
|
arc: C0 H00L0000
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEA.K0.INIT 0011110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R15C23:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: C0 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R16C20:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
|
|
.tile R16C21:PLC2
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R16C23:PLC2
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
|
|
.tile R16C88:PLC2
|
|
arc: E1_H02E0501 V06S0303
|
|
|
|
.tile R18C16:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R18C19:PLC2
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 V02N0601
|
|
arc: C2 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 F0
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H02E0201 F2
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0201 F2
|
|
arc: S3_V06S0003 F0
|
|
arc: V00T0100 F1
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEB.K0.INIT 0000000011110000
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 1111000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R18C20:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: A0 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: B0 V01N0001
|
|
arc: B1 V01N0001
|
|
arc: B2 V02N0101
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0100
|
|
arc: C2 H00L0100
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00B0100
|
|
arc: D2 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F2
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V00T0000 Q0
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0111111110000000
|
|
word: SLICEA.K1.INIT 0011110011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R18C22:PLC2
|
|
arc: S3_V06S0003 H06E0003
|
|
|
|
.tile R19C15:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R19C18:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R19C19:PLC2
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: B1 Q1
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V02S0001
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q1
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEA.K1.INIT 0011001111001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C20:PLC2
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C21:PLC2
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
|
|
.tile R19C22:PLC2
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
|
|
.tile R19C23:PLC2
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
|
|
.tile R19C88:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R20C19:PLC2
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
|
|
.tile R20C20:PLC2
|
|
arc: N1_V02N0201 V01N0001
|
|
|
|
.tile R21C14:PLC2
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
|
|
.tile R21C16:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S3_V06S0103 H06W0103
|
|
|
|
.tile R21C19:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R21C20:PLC2
|
|
arc: A3 H02W0501
|
|
arc: B0 N1_V02S0101
|
|
arc: B3 N1_V02S0101
|
|
arc: C0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D3 V01S0100
|
|
arc: E1_H01E0101 F3
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F3
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F3
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEA.K0.INIT 0000110011111100
|
|
word: SLICEB.K1.INIT 1010101011101110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R21C21:PLC2
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
|
|
.tile R21C23:PLC2
|
|
arc: N1_V02N0301 H06E0003
|
|
|
|
.tile R23C20:PLC2
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
|
|
.tile R24C14:PLC2
|
|
arc: S1_V02S0601 E3_H06W0303
|
|
|
|
.tile R24C16:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R24C17:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0301 H06W0003
|
|
arc: S1_V02S0501 H06W0303
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 H06W0303
|
|
|
|
.tile R24C18:PLC2
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: B0 H02W0301
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R24C19:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R24C20:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00L0000 H02E0001
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W3_H06W0003 V06S0003
|
|
arc: A0 H00L0000
|
|
arc: B0 V01N0001
|
|
arc: C0 V02N0401
|
|
arc: C6 V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D6 H02E0001
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0601 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F6
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0401 F6
|
|
arc: S3_V06S0303 F6
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEA.K0.INIT 0010001000100000
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
|
|
.tile R24C21:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: B0 H02W0301
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0000110011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C22:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: B0 H02W0301
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0011000011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C23:PLC2
|
|
arc: W1_H02W0301 V01N0101
|
|
|
|
.tile R25C14:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
|
|
.tile R25C15:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R25C16:PLC2
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: A1 F5
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B5 V01S0000
|
|
arc: C0 V02N0401
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 V02S0001
|
|
arc: D5 V02N0401
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 0011110000000000
|
|
word: SLICEA.K1.INIT 0110011000000000
|
|
word: SLICEC.K1.INIT 1100110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R25C17:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0100 V02S0501
|
|
arc: V00B0100 V02S0301
|
|
arc: A0 H00L0000
|
|
arc: B0 E1_H02W0301
|
|
arc: C0 E1_H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0010001000100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C18:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: A0 H00L0100
|
|
arc: B0 H02W0101
|
|
arc: C0 V02N0601
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0003 Q0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000101000001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C19:PLC2
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 V02S0401
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A1 S1_V02N0501
|
|
arc: B1 V02S0301
|
|
arc: C1 S1_V02N0401
|
|
arc: D1 W1_H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0000
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R25C20:PLC2
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A1 V01N0101
|
|
arc: B1 V02N0101
|
|
arc: C1 V02N0401
|
|
arc: D1 N1_V01S0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H02W0001
|
|
arc: M6 V00B0100
|
|
arc: N1_V01N0001 F3
|
|
arc: S1_V02S0101 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R25C21:PLC2
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: A1 V02N0501
|
|
arc: B1 V02N0101
|
|
arc: C1 V02N0601
|
|
arc: D1 S1_V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: W1_H02W0301 F3
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R25C22:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0100 V02N0301
|
|
arc: A1 V01N0101
|
|
arc: B1 E1_H01W0100
|
|
arc: C1 S1_V02N0401
|
|
arc: D1 N1_V01S0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0100
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0101 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R25C23:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: A0 H00L0000
|
|
arc: A2 F5
|
|
arc: B0 H02E0301
|
|
arc: B2 S1_V02N0101
|
|
arc: C0 H02E0601
|
|
arc: C5 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 H02E0001
|
|
arc: D5 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 F2
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
word: SLICEB.K0.INIT 1000100000000000
|
|
word: SLICEA.K0.INIT 0100100010001000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R25C24:PLC2
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
|
|
.tile R25C88:PLC2
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R26C14:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
|
|
.tile R26C15:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: B0 E1_H02W0101
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R26C16:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0100 V02S0301
|
|
arc: A1 V02N0701
|
|
arc: A5 V02S0301
|
|
arc: A6 V02S0301
|
|
arc: A7 V02S0301
|
|
arc: B1 V02S0301
|
|
arc: C1 N1_V01S0100
|
|
arc: C4 V00B0100
|
|
arc: D0 V00B0100
|
|
arc: D1 V02S0001
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 E1_H02W0401
|
|
arc: S1_V02S0101 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0100 F3
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 0110110011001100
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 1010101010101010
|
|
word: SLICED.K0.INIT 1010101010101010
|
|
word: SLICED.K1.INIT 1010101010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R26C17:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A1 H02E0501
|
|
arc: B1 V00B0000
|
|
arc: C1 N1_V02S0601
|
|
arc: D0 W1_H02E0001
|
|
arc: D1 W1_H02E0001
|
|
arc: D2 W1_H02E0001
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 W1_H02E0001
|
|
arc: D7 W1_H02E0001
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0000
|
|
arc: M2 H02E0601
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M6 H02E0401
|
|
arc: S1_V02S0101 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0101 F3
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 0111111110000000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 1111111100000000
|
|
word: SLICEC.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 1111111100000000
|
|
word: SLICED.K1.INIT 1111111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R26C18:PLC2
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A1 W1_H02E0701
|
|
arc: B1 V02S0301
|
|
arc: C1 N1_V01S0100
|
|
arc: D0 V02N0001
|
|
arc: D1 V02S0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 F1
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: S1_V02S0301 F1
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0000 F1
|
|
arc: W1_H02W0301 F1
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 0110101010101010
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R26C19:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: A1 V02N0701
|
|
arc: B1 E1_H01W0100
|
|
arc: C1 V02N0401
|
|
arc: D1 S1_V02N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: N1_V01N0001 F3
|
|
arc: S1_V02S0101 F3
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R26C20:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: A1 F7
|
|
arc: A3 F7
|
|
arc: B0 F3
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: B6 F3
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 H00L0000
|
|
arc: C6 E1_H01E0101
|
|
arc: C7 V02S0001
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 V00T0100
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 F6
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q0
|
|
word: SLICEB.K0.INIT 0011000011000000
|
|
word: SLICED.K0.INIT 1100000011000000
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
word: SLICEA.K0.INIT 0011110000000000
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 0110011000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C21:PLC2
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A2 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 S1_V02N0301
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0001
|
|
arc: D3 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0000
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R26C22:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H02W0501
|
|
arc: B0 V01N0001
|
|
arc: B1 N1_V02S0301
|
|
arc: C0 N1_V01S0100
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V01S0100
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0301 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: S1_V02S0301 Q1
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 0000111000000000
|
|
word: SLICEA.K1.INIT 0100010010001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C23:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A1 H01E0001
|
|
arc: A6 V02N0101
|
|
arc: B1 V02N0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C1 N1_V01S0100
|
|
arc: C6 H01E0001
|
|
arc: D1 H02E0001
|
|
arc: D6 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: W1_H02W0101 F3
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
|
|
.tile R26C2:PLC2
|
|
arc: E1_H01E0101 F2
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 F2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R26C3:PLC2
|
|
arc: W1_H02W0501 H01E0101
|
|
|
|
.tile R27C14:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
|
|
.tile R27C15:PLC2
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: B0 H02W0101
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R27C16:PLC2
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: A7 N1_V01S0100
|
|
arc: B7 S1_V02N0501
|
|
arc: C7 E1_H02W0601
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D7 V02S0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR0 V00B0100
|
|
arc: M0 V00T0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0203 Q7
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 1111111111111111
|
|
word: SLICEC.K1.INIT 1111111111111111
|
|
word: SLICED.K0.INIT 1111111111111111
|
|
word: SLICED.K1.INIT 1111111111111110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C17:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A2 V02S0701
|
|
arc: B2 V02S0301
|
|
arc: C2 E1_H01W0000
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 N1_V01S0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0100 F1
|
|
arc: LSR0 V00T0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H01W0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 1111111111101111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C18:PLC2
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0501
|
|
arc: B1 N1_V02S0301
|
|
arc: B2 N1_V02S0301
|
|
arc: C1 V02S0601
|
|
arc: C2 V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 N1_V02S0001
|
|
arc: E3_H06E0203 Q7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0301 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C19:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: A1 S1_V02N0501
|
|
arc: B1 V02N0301
|
|
arc: C1 V02S0601
|
|
arc: D1 H00R0000
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R27C20:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0501
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: D1 V02S0201
|
|
arc: D2 V02S0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00B0000
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R27C21:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A1 H02E0701
|
|
arc: B1 V01N0001
|
|
arc: C1 H02E0601
|
|
arc: D1 V02S0201
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0100
|
|
arc: N1_V01N0001 F3
|
|
arc: W1_H02W0101 F3
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R27C22:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A1 N1_V02S0701
|
|
arc: B1 H02W0101
|
|
arc: C1 N1_V01S0100
|
|
arc: D1 V02S0201
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0000
|
|
arc: N1_V01N0001 F3
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R27C23:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: A0 H02E0701
|
|
arc: A1 N1_V02S0501
|
|
arc: B1 H02E0301
|
|
arc: C0 V02N0401
|
|
arc: C1 H00L0100
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K1.INIT 0111100000000000
|
|
word: SLICEA.K0.INIT 0101101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R27C24:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0001 H01E0001
|
|
|
|
.tile R27C29:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R27C30:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C35:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R27C36:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C41:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C42:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C47:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C48:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C53:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C54:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R27C59:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C60:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R27C65:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C66:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R27C71:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C72:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R27C77:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C78:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R27C83:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R27C84:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C87:PLC2
|
|
arc: S1_V02S0701 H06E0203
|
|
|
|
.tile R27C88:PLC2
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
|
|
.tile R28C15:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R28C16:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: S1_V02S0001 H06W0003
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: A6 N1_V02S0301
|
|
arc: B6 H02W0101
|
|
arc: C6 V00B0100
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 E1_H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0100 Q7
|
|
arc: LSR1 H02E0301
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H02W0201
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 E1_H02W0401
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111111011111111
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C17:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: H00L0100 H02E0301
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: A1 S1_V02N0701
|
|
arc: B1 S1_V02N0301
|
|
arc: B5 S1_V02N0501
|
|
arc: B7 S1_V02N0501
|
|
arc: C1 W1_H02E0401
|
|
arc: C4 V00B0100
|
|
arc: C6 V00B0100
|
|
arc: D0 V00B0100
|
|
arc: D1 N1_V02S0001
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: N1_V02N0301 F3
|
|
arc: S1_V02S0101 F3
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 0110110011001100
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 1100110011001100
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 1100110011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R28C18:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: H00L0100 S1_V02N0101
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A6 N1_V02S0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C6 N1_V02S0201
|
|
arc: D6 V02S0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H01E0001
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00T0100
|
|
arc: N1_V02N0101 F3
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111111111111011
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R28C19:PLC2
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 E1_H02W0701
|
|
arc: B1 H02E0301
|
|
arc: C1 H02E0401
|
|
arc: D1 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0000
|
|
arc: S1_V02S0301 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: W3_H06W0003 F3
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C20:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: V00B0000 V02N0201
|
|
arc: A1 V01N0101
|
|
arc: B1 S1_V02N0101
|
|
arc: C1 H02E0601
|
|
arc: D1 W1_H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R28C21:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H00L0000
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 N1_V02S0001
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q1
|
|
word: SLICEA.K0.INIT 0110101000000000
|
|
word: SLICEA.K1.INIT 0011110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C22:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: V00B0000 V02N0001
|
|
arc: A1 V02S0501
|
|
arc: B1 N1_V02S0301
|
|
arc: C1 H02W0401
|
|
arc: D1 N1_V02S0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0000
|
|
arc: M5 W1_H02E0001
|
|
arc: M6 V00B0000
|
|
arc: N1_V01N0001 F3
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R28C23:PLC2
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
|
|
.tile R28C3:PLC2
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R28C87:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
|
|
.tile R28C9:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C10:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C15:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0601 E3_H06W0303
|
|
|
|
.tile R29C16:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: V00B0000 V02S0001
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
arc: A1 V01N0101
|
|
arc: A7 H00R0000
|
|
arc: B1 S1_V02N0301
|
|
arc: B7 H02E0301
|
|
arc: C1 V02N0401
|
|
arc: C3 V02N0601
|
|
arc: C7 V01N0101
|
|
arc: D1 H02E0001
|
|
arc: D3 S1_V02N0001
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0501 F7
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H00L0000
|
|
arc: M2 H02E0601
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0501 F7
|
|
arc: V01S0000 F7
|
|
word: SLICED.K1.INIT 0110101010101010
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0010000100000011
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R29C17:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: A6 E1_H02W0701
|
|
arc: B6 H02W0301
|
|
arc: C6 H02E0401
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 V02S0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111111111111011
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C18:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: A6 N1_V02S0101
|
|
arc: B6 W1_H02E0301
|
|
arc: C6 V00B0100
|
|
arc: D6 H02E0001
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M3 H00L0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0100
|
|
arc: M6 H02E0401
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111111111111101
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R29C19:PLC2
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 V02N0701
|
|
arc: B0 V02N0301
|
|
arc: B2 V02N0101
|
|
arc: C0 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H01W0000 F1
|
|
arc: LSR0 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
word: SLICEA.K0.INIT 1000001000001010
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000110000001100
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R29C20:PLC2
|
|
arc: H00R0000 V02N0601
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: A1 F7
|
|
arc: A2 V00T0000
|
|
arc: B1 V02N0301
|
|
arc: B2 F3
|
|
arc: B3 V02S0101
|
|
arc: B7 V00T0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 H00L0100
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 S1_V02N0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
arc: S1_V02S0001 Q0
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEB.K0.INIT 0110011000000000
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 1100000011000000
|
|
word: SLICEA.K1.INIT 0111100000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C21:PLC2
|
|
arc: H00R0100 V02N0501
|
|
arc: V00T0000 V02N0401
|
|
arc: A0 V01N0101
|
|
arc: A2 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: A4 E1_H01W0000
|
|
arc: B0 V02N0101
|
|
arc: B1 V01N0001
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 V02N0701
|
|
arc: B6 V02N0701
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 E1_H01W0000
|
|
arc: C6 H01E0001
|
|
arc: D0 H02E0001
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D6 V02N0601
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0401 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F6
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: W3_H06W0203 F4
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K0.INIT 0110011010101010
|
|
word: SLICED.K0.INIT 0000000011111100
|
|
word: SLICEA.K0.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 1100000000000000
|
|
word: SLICEB.K0.INIT 1000000000000000
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C22:PLC2
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0100 V02N0301
|
|
arc: C0 H02E0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R29C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R29C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C37:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C43:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C49:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C4:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R29C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R29C61:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R29C67:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R29C73:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R29C79:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R29C85:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
|
|
.tile R29C86:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R2C15:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R2C20:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: H00R0100 E1_H02W0701
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0100 H02W0101
|
|
arc: A0 E1_H02W0501
|
|
arc: A2 E1_H02W0501
|
|
arc: B0 V02N0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 V02N0301
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 E1_H02W0301
|
|
arc: C0 V02N0401
|
|
arc: C2 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0201
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR0 V00T0100
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0701 Q7
|
|
word: SLICEA.K0.INIT 0101010110001010
|
|
word: SLICEA.K1.INIT 0011001100000000
|
|
word: SLICEB.K0.INIT 0000000011101111
|
|
word: SLICEB.K1.INIT 0000000011001100
|
|
word: SLICEC.K0.INIT 0011110000111100
|
|
word: SLICEC.K1.INIT 0011110000111100
|
|
word: SLICED.K0.INIT 0000111100001111
|
|
word: SLICED.K1.INIT 0000111100001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R2C21:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: A0 V02N0501
|
|
arc: A1 H02W0501
|
|
arc: A2 V02N0501
|
|
arc: A3 H02W0501
|
|
arc: B0 H02W0101
|
|
arc: B2 H02W0301
|
|
arc: B4 H02W0101
|
|
arc: B5 H02W0301
|
|
arc: C0 E1_H02W0401
|
|
arc: C2 E1_H02W0401
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D5 H02E0201
|
|
arc: D6 H02E0201
|
|
arc: D7 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR1 V00B0100
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: W3_H06W0203 Q7
|
|
word: SLICEA.K0.INIT 0011001101001100
|
|
word: SLICEA.K1.INIT 0101010100000000
|
|
word: SLICEB.K0.INIT 0000000011011111
|
|
word: SLICEB.K1.INIT 0000000010101010
|
|
word: SLICEC.K0.INIT 0011001111001100
|
|
word: SLICEC.K1.INIT 0011001111001100
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
word: SLICED.K1.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R2C22:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: W1_H02W0701 E1_H02W0601
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 E1_H02W0101
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0000
|
|
arc: M6 E1_H02W0401
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000110011
|
|
word: SLICEA.K1.INIT 0000000000110011
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R2C23:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0501 V01N0101
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0501
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 H01E0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A0 H02E0701
|
|
arc: A2 V02N0701
|
|
arc: B0 V01N0001
|
|
arc: B1 H02E0301
|
|
arc: B2 V02N0301
|
|
arc: B3 H02E0101
|
|
arc: B5 H02E0101
|
|
arc: C0 H00L0000
|
|
arc: C2 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0201
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V02N0201
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0201
|
|
arc: D4 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
word: SLICEA.K0.INIT 0101101001010010
|
|
word: SLICEA.K1.INIT 0011001100000000
|
|
word: SLICEB.K0.INIT 0000000011111101
|
|
word: SLICEB.K1.INIT 0000000011001100
|
|
word: SLICEC.K0.INIT 0000111111110000
|
|
word: SLICEC.K1.INIT 0011110000111100
|
|
word: SLICED.K0.INIT 0000111100001111
|
|
word: SLICED.K1.INIT 0000111100001111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R2C24:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 W1_H02E0301
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 V06N0103
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0401 V06N0203
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: B1 W1_H02E0301
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C4 S1_V02N0201
|
|
arc: CE1 H02E0101
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V02N0001
|
|
arc: D4 H02E0001
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 F4
|
|
arc: LSR0 V00B0100
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0000
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: V00T0000 F0
|
|
arc: V01S0000 F4
|
|
arc: W1_H02W0601 F4
|
|
word: SLICEA.K0.INIT 0101010110100101
|
|
word: SLICEA.K1.INIT 0010010001100101
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R2C25:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A2 V01N0101
|
|
arc: B0 V02N0301
|
|
arc: B2 V02N0301
|
|
arc: B3 V01N0001
|
|
arc: C0 V02N0401
|
|
arc: C2 V02N0601
|
|
arc: C4 V02N0001
|
|
arc: C5 V02N0001
|
|
arc: D0 H02E0201
|
|
arc: D1 V02N0001
|
|
arc: D2 H02E0201
|
|
arc: D3 V02N0001
|
|
arc: D4 V01N0001
|
|
arc: D5 V01N0001
|
|
arc: D6 V01N0001
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
word: SLICEA.K0.INIT 0110001001100110
|
|
word: SLICEA.K1.INIT 0000000010101010
|
|
word: SLICEB.K0.INIT 0101010001010101
|
|
word: SLICEB.K1.INIT 0011001100000000
|
|
word: SLICEC.K0.INIT 0000111111110000
|
|
word: SLICEC.K1.INIT 0000111111110000
|
|
word: SLICED.K0.INIT 0000000011111111
|
|
word: SLICED.K1.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
|
|
.tile R2C26:PLC2
|
|
arc: W1_H02W0001 H01E0001
|
|
|
|
.tile R2C30:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R2C36:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R2C3:PLC2
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R2C42:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
|
|
.tile R2C48:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R2C49:PLC2
|
|
arc: N1_V02N0701 H01E0101
|
|
|
|
.tile R2C50:PLC2
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
|
|
.tile R2C9:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R30C16:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: H00R0000 H02W0601
|
|
arc: V00B0100 V02S0101
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: B0 H02W0101
|
|
arc: B4 V02S0501
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D4 V02N0401
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0601 Q4
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R30C17:PLC2
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: A6 V02S0101
|
|
arc: B6 S1_V02N0701
|
|
arc: C6 S1_V02N0001
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D6 H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00B0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0100
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S3_V06S0203 Q7
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1111111111111111
|
|
word: SLICEB.K1.INIT 1111111111111111
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111111011111111
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 1111111111111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C18:PLC2
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 V02N0201
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: A0 H00L0000
|
|
arc: B0 S1_V02N0301
|
|
arc: C0 W1_H02E0401
|
|
arc: C2 W1_H02E0401
|
|
arc: D0 H02W0001
|
|
arc: D2 H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: N1_V02N0101 F1
|
|
word: SLICEA.K0.INIT 1000011100000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000111100000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R30C19:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A0 V02S0501
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 0101000010100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R30C20:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W3_H06W0303 N3_V06S0303
|
|
arc: A1 H00R0000
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 H02W0101
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 N1_V01S0100
|
|
arc: C7 H02W0601
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 H02W0201
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 F7
|
|
arc: M0 V00T0000
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
word: SLICEA.K1.INIT 1110000000000000
|
|
word: SLICED.K1.INIT 0000111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R30C21:PLC2
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: W1_H02W0501 E1_H01W0100
|
|
arc: A2 V00B0000
|
|
arc: A5 V00B0000
|
|
arc: B0 W1_H02E0301
|
|
arc: B2 H00L0000
|
|
arc: B4 H01E0101
|
|
arc: B5 H00L0000
|
|
arc: C1 V02N0401
|
|
arc: C2 H00L0100
|
|
arc: C5 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D1 H02W0001
|
|
arc: D2 H02W0201
|
|
arc: D4 H02W0001
|
|
arc: D5 H02W0201
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q1
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEA.K1.INIT 0000111100000000
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 0011011000111100
|
|
word: SLICEC.K0.INIT 1100110000000000
|
|
word: SLICEC.K1.INIT 1100100011000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R30C22:PLC2
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: C0 N1_V01N0001
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R31C16:PLC2
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
|
|
.tile R31C17:PLC2
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
|
|
.tile R31C18:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: A0 E1_H02W0501
|
|
arc: B0 V01N0001
|
|
arc: C0 V02S0401
|
|
arc: C2 V02S0401
|
|
arc: D0 V02S0201
|
|
arc: D2 V00B0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: N1_V02N0301 F1
|
|
word: SLICEA.K0.INIT 0100000100000101
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R31C19:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
arc: A0 V02S0501
|
|
arc: B0 H02E0301
|
|
arc: C0 V02S0401
|
|
arc: C2 V02S0401
|
|
arc: D0 V02S0001
|
|
arc: D2 V00T0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: N1_V01N0001 F1
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000001111
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0100000100000101
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R31C20:PLC2
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: A1 H00L0000
|
|
arc: B1 V02S0301
|
|
arc: C1 V02S0401
|
|
arc: C3 V02S0601
|
|
arc: C7 E1_H01E0101
|
|
arc: D1 N1_V02S0201
|
|
arc: D3 E1_H02W0201
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: M0 V00T0100
|
|
arc: V00T0100 F3
|
|
arc: W1_H02W0201 F0
|
|
arc: W1_H02W0501 F7
|
|
word: SLICED.K1.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 0000100000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R31C21:PLC2
|
|
arc: N1_V02N0401 H01E0001
|
|
|
|
.tile R31C22:PLC2
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
|
|
.tile R31C3:PLC2
|
|
arc: W1_H02W0501 V06S0303
|
|
|
|
.tile R32C17:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R32C18:PLC2
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
|
|
.tile R36C17:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R3C16:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R3C19:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
|
|
.tile R3C20:PLC2
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H06W0203
|
|
|
|
.tile R3C21:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 H02W0601
|
|
arc: A0 V02N0701
|
|
arc: A7 Q7
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 V02N0401
|
|
arc: C4 V00B0100
|
|
arc: C5 V00B0100
|
|
arc: C6 V00B0100
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M0 H02W0601
|
|
arc: M1 H00R0000
|
|
arc: M2 H02W0601
|
|
arc: M3 E1_H02W0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0101 F3
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q7
|
|
word: SLICED.K1.INIT 1010101010101010
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 1111000011110000
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEA.K0.INIT 1111111000000001
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R3C22:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: A3 V00B0000
|
|
arc: B0 V00T0000
|
|
arc: B3 Q3
|
|
arc: C1 S1_V02N0401
|
|
arc: C4 Q4
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 H02E0001
|
|
arc: D3 H02W0201
|
|
arc: D4 H02W0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F1
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0000111111110000
|
|
word: SLICEA.K0.INIT 0011001111001100
|
|
word: SLICEB.K1.INIT 1001100111001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R3C23:PLC2
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 H00L0100
|
|
arc: A1 V02N0701
|
|
arc: A3 H02W0701
|
|
arc: A6 F5
|
|
arc: A7 F5
|
|
arc: B0 V00T0000
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: B5 F1
|
|
arc: B6 V02N0501
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 H00L0000
|
|
arc: C2 H00L0100
|
|
arc: C3 E1_H01W0000
|
|
arc: C5 E1_H02W0601
|
|
arc: C6 E1_H02W0401
|
|
arc: C7 E1_H02W0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D1 V01S0100
|
|
arc: D2 V00T0100
|
|
arc: D5 F0
|
|
arc: D6 E1_H01W0100
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F6
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0601 F6
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
arc: W3_H06W0003 F3
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEB.K1.INIT 1100100111001001
|
|
word: SLICEA.K0.INIT 1100100111001100
|
|
word: SLICEA.K1.INIT 0101010110101010
|
|
word: SLICED.K1.INIT 0000000000000010
|
|
word: SLICED.K0.INIT 0000001000000000
|
|
word: SLICEC.K1.INIT 0000000000110000
|
|
word: SLICEB.K0.INIT 1100001111001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
|
|
.tile R3C24:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A1 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: A7 V00T0100
|
|
arc: B1 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B7 H02E0301
|
|
arc: C0 H00R0100
|
|
arc: C1 H00R0100
|
|
arc: C3 E1_H01W0000
|
|
arc: C7 V00B0100
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V01S0100
|
|
arc: D3 V01S0100
|
|
arc: D5 H00R0100
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F2
|
|
arc: LSR1 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F1
|
|
arc: V00B0100 Q5
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0301 F1
|
|
arc: W1_H02W0701 Q5
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K1.INIT 1010101010101001
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 0000000011111111
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1111000000001111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R3C25:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: C0 W1_H02E0401
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0201
|
|
arc: D1 H01E0101
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 F1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K1.INIT 0011001111001100
|
|
word: SLICEA.K0.INIT 1100001111001100
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R3C29:PLC2
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
|
|
.tile R42C17:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R48C17:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R4C21:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: A2 F7
|
|
arc: A3 F7
|
|
arc: A4 V00B0000
|
|
arc: A6 V02S0301
|
|
arc: A7 H00R0000
|
|
arc: B4 V00B0100
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 V02S0701
|
|
arc: C2 H00R0100
|
|
arc: C3 H00R0100
|
|
arc: C4 F6
|
|
arc: C5 F6
|
|
arc: C6 V02S0201
|
|
arc: C7 V01N0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V02S0201
|
|
arc: D3 V02S0201
|
|
arc: D4 V02N0401
|
|
arc: D5 H00R0100
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 E1_H02W0501
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 F6
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0001000000000000
|
|
word: SLICEB.K0.INIT 0000000000001010
|
|
word: SLICEC.K1.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0000101000000000
|
|
word: SLICED.K0.INIT 0000010000000100
|
|
word: SLICEC.K0.INIT 1001101010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R4C22:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 H02E0701
|
|
arc: B0 V02S0101
|
|
arc: C0 H02E0601
|
|
arc: D0 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0000
|
|
arc: S1_V02S0101 F3
|
|
arc: V01S0000 F3
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R4C23:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A2 V00T0000
|
|
arc: B2 E1_H02W0101
|
|
arc: C2 E1_H01W0000
|
|
arc: D2 N1_V01S0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: N1_V01N0001 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0301 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R4C24:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: A0 F7
|
|
arc: A1 F7
|
|
arc: A2 V00T0000
|
|
arc: A5 V02S0101
|
|
arc: A7 F5
|
|
arc: B1 Q1
|
|
arc: B2 V02S0101
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 H02E0301
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H00L0000
|
|
arc: C5 V00T0000
|
|
arc: C7 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V01S0100
|
|
arc: D2 N1_V01S0000
|
|
arc: D5 E1_H01W0100
|
|
arc: D7 H02E0001
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 F0
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: V00T0000 Q2
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 F0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 1111010100001010
|
|
word: SLICED.K1.INIT 0000000000000010
|
|
word: SLICEA.K1.INIT 1100110011000110
|
|
word: SLICEC.K1.INIT 0000000000000100
|
|
word: SLICEB.K0.INIT 1010100110101010
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R4C25:PLC2
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: V00T0100 V02N0701
|
|
arc: A4 N1_V01N0101
|
|
arc: B0 V02S0301
|
|
arc: B1 Q1
|
|
arc: B4 H01E0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C4 V00T0000
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00B0100
|
|
arc: D4 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F4
|
|
arc: N1_V01N0101 Q1
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q1
|
|
word: SLICEA.K0.INIT 1111001100001100
|
|
word: SLICEA.K1.INIT 0011001111001100
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R4C31:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
|
|
.tile R4C41:PLC2
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R54C17:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R5C20:PLC2
|
|
arc: A3 E1_H01E0001
|
|
arc: B3 Q3
|
|
arc: C2 H00L0000
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 Q2
|
|
arc: D3 V01S0100
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0110011011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R5C21:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: A0 F5
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 V00T0000
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 V00T0100
|
|
arc: B1 H02E0101
|
|
arc: B3 V02N0101
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H02E0101
|
|
arc: C1 H00L0000
|
|
arc: C2 N1_V01S0100
|
|
arc: C4 V00T0000
|
|
arc: C5 H01E0001
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 H02E0001
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 V02N0201
|
|
arc: D4 V00B0000
|
|
arc: D5 H02E0201
|
|
arc: D6 V00B0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0401 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0101 F3
|
|
word: SLICEC.K0.INIT 1111110100000010
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0110101010101010
|
|
word: SLICEA.K0.INIT 0101010110101010
|
|
word: SLICEB.K1.INIT 0000000011001100
|
|
word: SLICED.K0.INIT 0000000000001111
|
|
word: SLICEB.K0.INIT 1010101001011010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R5C22:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: A1 H00L0100
|
|
arc: A3 H00L0100
|
|
arc: A4 V02S0101
|
|
arc: A7 S1_V02N0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 H00L0000
|
|
arc: C0 H00L0000
|
|
arc: C1 F4
|
|
arc: C3 H00L0000
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 E1_H02W0001
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0601 F4
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F3
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F4
|
|
arc: V00B0100 F7
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEA.K1.INIT 1010101001011010
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0010001000100010
|
|
word: SLICED.K1.INIT 1010101011111010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R5C23:PLC2
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 H01E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: A2 H01E0001
|
|
arc: B2 E1_H01W0100
|
|
arc: C2 E1_H01W0000
|
|
arc: D2 H02W0001
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00T0000
|
|
arc: N3_V06N0003 F3
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R5C24:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: A2 F7
|
|
arc: A3 H00L0100
|
|
arc: A7 E1_H01W0000
|
|
arc: B1 Q1
|
|
arc: B2 H02E0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B7 V01S0000
|
|
arc: C0 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C3 W1_H02E0601
|
|
arc: C7 W1_H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 H01E0101
|
|
arc: D2 Q2
|
|
arc: D3 H02E0201
|
|
arc: D7 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q2
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 Q1
|
|
word: SLICEB.K1.INIT 1010101010011010
|
|
word: SLICEB.K0.INIT 1111110111001100
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0011001111001100
|
|
word: SLICED.K1.INIT 0000000000010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R5C25:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R5C29:PLC2
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: A3 V00B0000
|
|
arc: B3 H00L0000
|
|
arc: C0 E1_H02W0601
|
|
arc: C3 E1_H01W0000
|
|
arc: CE0 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 H00R0000
|
|
arc: D3 E1_H02W0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 H02W0501
|
|
arc: M2 E1_H02W0601
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00B0000 Q6
|
|
arc: V00T0000 F2
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q0
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 0110101010101010
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R5C30:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00L0100 V02N0101
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 F5
|
|
arc: C0 H00L0000
|
|
arc: C5 H01E0001
|
|
arc: CE0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D5 V02N0601
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 0101101011110000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R5C31:PLC2
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: C0 H00L0000
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0201 Q0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R60C17:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R66C17:PLC2
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
|
|
.tile R68C17:PLC2
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
|
|
.tile R68C18:PLC2
|
|
arc: S1_V02S0501 H02E0501
|
|
|
|
.tile R6C21:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: A0 V02S0701
|
|
arc: C6 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0201 F0
|
|
arc: N3_V06N0003 F0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00B0000 F6
|
|
word: SLICED.K0.INIT 1111000011111111
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R6C22:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: V00T0000 H02E0201
|
|
arc: B0 H01W0100
|
|
arc: C0 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0003 Q0
|
|
word: SLICEA.K0.INIT 0011000011111100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R6C24:PLC2
|
|
arc: E1_H02E0501 V01N0101
|
|
|
|
.tile R6C25:PLC2
|
|
arc: A0 H00L0100
|
|
arc: A4 V02N0301
|
|
arc: B0 V00T0000
|
|
arc: B1 V00T0000
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C2 F4
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V01S0100
|
|
arc: D2 Q2
|
|
arc: D4 S1_V02N0401
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0201 Q2
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
word: SLICEA.K0.INIT 0111111110000000
|
|
word: SLICEA.K1.INIT 0011111111000000
|
|
word: SLICEC.K0.INIT 1010101000000000
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R6C26:PLC2
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00B0100 V02N0301
|
|
arc: A1 H01E0001
|
|
arc: B1 H02E0101
|
|
arc: C1 V02N0401
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R6C27:PLC2
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: V00T0000 V02N0601
|
|
arc: A1 H00L0000
|
|
arc: A2 E1_H02W0701
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0301
|
|
arc: C1 H02W0601
|
|
arc: C2 H02W0401
|
|
arc: D1 H02W0001
|
|
arc: D2 H02W0001
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R6C28:PLC2
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: A4 F7
|
|
arc: B1 W1_H02E0301
|
|
arc: B3 H00R0000
|
|
arc: B4 H00R0000
|
|
arc: B6 W1_H02E0301
|
|
arc: C0 F6
|
|
arc: C1 V02N0401
|
|
arc: C3 H00L0100
|
|
arc: C4 V00T0000
|
|
arc: C7 F6
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V02N0001
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D6 V02N0601
|
|
arc: D7 H01W0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICED.K0.INIT 1100110000000000
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0011001100110000
|
|
word: SLICEB.K0.INIT 0101010110101010
|
|
word: SLICEB.K1.INIT 0111100011110000
|
|
word: SLICEC.K0.INIT 0110110001101100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R6C29:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A0 V01N0101
|
|
arc: A1 V02N0701
|
|
arc: B0 V02N0301
|
|
arc: B1 V01N0001
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 E1_H01W0000
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
word: SLICEA.K0.INIT 0000111100001101
|
|
word: SLICEA.K1.INIT 0000111100001011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R6C30:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0100 S1_V02N0301
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: B1 V01N0001
|
|
arc: B2 V02N0101
|
|
arc: C1 N1_V01S0100
|
|
arc: C4 V01N0101
|
|
arc: C5 V01N0101
|
|
arc: C6 V01N0101
|
|
arc: C7 V01N0101
|
|
arc: D1 H02E0201
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0000
|
|
arc: S1_V02S0101 F3
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K0.INIT 1010101010101010
|
|
word: SLICEA.K1.INIT 0110101010101010
|
|
word: SLICEB.K0.INIT 1100110011001100
|
|
word: SLICEB.K1.INIT 1010101010101010
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 1111000011110000
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 1111000011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R6C31:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 V02N0501
|
|
arc: B0 S1_V02N0301
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEA.K0.INIT 0000000011101111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R6C35:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R6C41:PLC2
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
|
|
.tile R7C13:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R7C15:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R7C16:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C18:PLC2
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R7C19:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R7C21:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W3_H06W0103 N3_V06S0103
|
|
|
|
.tile R7C22:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C24:PLC2
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: B5 W1_H02E0301
|
|
arc: C5 V02N0001
|
|
arc: D5 V02N0401
|
|
arc: E1_H02E0501 F5
|
|
arc: E3_H06E0303 F5
|
|
arc: F5 F5_SLICE
|
|
arc: N1_V01N0101 F5
|
|
arc: S1_V02S0501 F5
|
|
word: SLICEC.K1.INIT 1111111100001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
|
|
.tile R7C25:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02N0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: A1 H00L0000
|
|
arc: B1 E1_H02W0301
|
|
arc: C1 N1_V01S0100
|
|
arc: D1 N1_V01S0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0100
|
|
arc: M5 E1_H02W0001
|
|
arc: M6 V00T0100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R7C26:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00T0100 H02W0301
|
|
arc: A0 V02S0501
|
|
arc: A1 H02E0701
|
|
arc: A2 V02S0501
|
|
arc: A3 E1_H02W0501
|
|
arc: B0 H02E0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: C0 V02S0401
|
|
arc: C1 V02S0401
|
|
arc: C2 V02S0401
|
|
arc: C3 V02S0401
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 H02E0001
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 H02E0201
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R7C27:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 V00T0000
|
|
arc: A4 V02S0301
|
|
arc: B0 H01W0100
|
|
arc: B1 V00T0000
|
|
arc: B3 Q3
|
|
arc: C0 V02N0601
|
|
arc: C1 V02N0401
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 H02E0001
|
|
arc: D2 H02E0001
|
|
arc: D3 V02N0001
|
|
arc: D4 V00B0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0601 Q4
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 Q1
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEC.K0.INIT 0101010110101010
|
|
word: SLICEA.K0.INIT 0011110011001100
|
|
word: SLICEB.K0.INIT 0101010110101010
|
|
word: SLICEB.K1.INIT 0011001111001100
|
|
word: SLICEA.K1.INIT 0000111000001010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R7C28:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: A1 H00L0000
|
|
arc: B1 V02S0301
|
|
arc: C1 V02S0601
|
|
arc: D1 V02S0201
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0301 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 H00L0100
|
|
arc: M2 H02E0601
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 H02E0401
|
|
arc: M5 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R7C29:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: A1 V02S0501
|
|
arc: A2 V02S0701
|
|
arc: B1 V00T0000
|
|
arc: B2 H00R0000
|
|
arc: C1 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: D1 H02W0201
|
|
arc: D2 H02W0201
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0101 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M1 H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00B0000
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R7C30:PLC2
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: A1 E1_H01E0001
|
|
arc: B1 V00T0000
|
|
arc: B4 H00R0000
|
|
arc: C1 H02E0601
|
|
arc: C4 S1_V02N0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 N1_V02S0201
|
|
arc: D2 V01S0100
|
|
arc: D3 V01S0100
|
|
arc: D4 V01N0001
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F1
|
|
arc: LSR0 H02E0501
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0100
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0101 Q3
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEC.K0.INIT 0000000011111100
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 0110101010101010
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R7C31:PLC2
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: A1 S1_V02N0501
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0101
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000111100000011
|
|
word: SLICEA.K1.INIT 0000111100001011
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R7C33:PLC2
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
|
|
.tile R7C37:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R7C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R7C49:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R7C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R7C61:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R7C64:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R7C67:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R7C73:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R7C79:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R7C7:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R7C85:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R7C87:PLC2
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
|
|
.tile R7C88:PLC2
|
|
arc: S3_V06S0103 H06E0103
|
|
|
|
.tile R8C24:PLC2
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: V00B0000 V02S0201
|
|
arc: A0 E1_H01E0001
|
|
arc: B0 V02S0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 0100010011101110
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R8C25:PLC2
|
|
arc: H00L0100 V02N0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: V00B0000 V02N0201
|
|
arc: A0 V02N0501
|
|
arc: B0 V02N0301
|
|
arc: C0 E1_H02W0601
|
|
arc: D0 E1_H02W0201
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00B0000
|
|
arc: N1_V02N0101 F3
|
|
word: SLICEA.K0.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R8C26:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: A1 V02S0501
|
|
arc: B1 V02S0101
|
|
arc: C1 V02S0601
|
|
arc: D1 E1_H02W0001
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 E1_H02W0601
|
|
arc: M1 H00R0100
|
|
arc: M2 E1_H02W0601
|
|
arc: M3 H00L0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H00R0100
|
|
arc: M6 E1_H02W0401
|
|
arc: N1_V02N0301 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R8C27:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 H02W0001
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0601 E1_H01W0000
|
|
arc: A0 N1_V02S0701
|
|
arc: A1 H00L0000
|
|
arc: A2 N1_V02S0701
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 V02S0301
|
|
arc: A5 V02S0301
|
|
arc: A6 V02S0301
|
|
arc: A7 V02S0301
|
|
arc: B0 V02S0101
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0101
|
|
arc: B4 V00B0100
|
|
arc: B5 V00B0100
|
|
arc: B6 V00B0100
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 H00L0100
|
|
arc: C2 N1_V01S0100
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V02S0001
|
|
arc: C5 V02S0001
|
|
arc: C6 V02S0001
|
|
arc: C7 V02S0201
|
|
arc: D0 V02S0001
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 V02S0001
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 V00B0000
|
|
arc: D5 V00B0000
|
|
arc: D6 V00B0000
|
|
arc: D7 H00L0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0000
|
|
arc: M3 H02E0201
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0000
|
|
arc: N1_V01N0001 F3
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R8C28:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: B0 F3
|
|
arc: B3 V01N0001
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D3 W1_H02E0201
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 F7
|
|
arc: E3_H06E0003 F0
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 F3
|
|
arc: LSR0 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 1100110000000000
|
|
word: SLICEA.K0.INIT 0011001111001100
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R8C29:PLC2
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: V00B0000 V02N0201
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0101
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0601
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 E1_H02W0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 H02W0601
|
|
arc: M1 H02E0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0000
|
|
arc: N1_V02N0101 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R8C30:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00L0100 V02N0101
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A1 V01N0101
|
|
arc: B1 V02N0301
|
|
arc: C1 E1_H01W0000
|
|
arc: D1 N1_V01S0000
|
|
arc: E1_H01E0001 F3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0000
|
|
arc: M3 W1_H02E0201
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00B0000
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V02N0301 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R8C31:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: W1_H02W0401 V01N0001
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: B0 V00T0000
|
|
arc: C0 V02N0601
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 0011110011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R8C3:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R9C16:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R9C20:PLC2
|
|
arc: S1_V02S0401 H06W0203
|
|
|
|
.tile R9C22:PLC2
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R9C23:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R9C24:PLC2
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: S1_V02S0201 N1_V01S0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D2 N1_V01S0000
|
|
arc: E1_H02E0001 F0
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 F0
|
|
arc: V00T0000 F2
|
|
word: SLICEB.K0.INIT 1111000011111111
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C25:PLC2
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: A0 H00L0100
|
|
arc: A4 E1_H01W0000
|
|
arc: A6 H00L0000
|
|
arc: B0 H01W0100
|
|
arc: B1 Q1
|
|
arc: B4 H00L0000
|
|
arc: B6 V01S0000
|
|
arc: C0 H02W0401
|
|
arc: C1 H02W0401
|
|
arc: C2 F6
|
|
arc: C3 H00L0000
|
|
arc: C4 V00T0000
|
|
arc: C6 H02W0401
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0201
|
|
arc: D2 Q2
|
|
arc: D3 V00T0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D6 H02W0201
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 F6
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 H02E0501
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0201 Q2
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q1
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0110110011001100
|
|
word: SLICEA.K1.INIT 0011110011001100
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEC.K0.INIT 0000001000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R9C26:PLC2
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: V00T0000 H02E0001
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: A3 V00B0000
|
|
arc: A4 V00B0000
|
|
arc: B3 H02E0101
|
|
arc: B4 H02E0101
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 W1_H02E0601
|
|
arc: C3 H00L0000
|
|
arc: C4 V00T0000
|
|
arc: C5 E1_H01E0101
|
|
arc: CE0 H00L0100
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 W1_H02E0001
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D5 H00R0100
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0101 F1
|
|
arc: E3_H06E0203 F4
|
|
arc: E3_H06E0303 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q5
|
|
arc: LSR1 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0501 Q5
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0000000011110000
|
|
word: SLICEC.K0.INIT 1010101010101001
|
|
word: SLICEB.K1.INIT 0000000000000010
|
|
word: SLICEC.K1.INIT 0000111111110000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C27:PLC2
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C28:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: C0 W1_H02E0401
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C29:PLC2
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00T0100 H02W0301
|
|
arc: A1 H00L0100
|
|
arc: B1 E1_H01W0100
|
|
arc: C1 E1_H02W0601
|
|
arc: D1 H02W0201
|
|
arc: E1_H01E0001 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R9C30:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A2 V00B0000
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: C0 F4
|
|
arc: C2 F4
|
|
arc: C4 E1_H01E0101
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V00B0100
|
|
arc: D2 Q2
|
|
arc: D4 H00L0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0101 Q1
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0301 Q1
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0111111110000000
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0011001111001100
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R9C31:PLC2
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A1 E1_H01E0001
|
|
arc: B1 V00T0000
|
|
arc: C1 N1_V01S0100
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 H02E0001
|
|
arc: E1_H01E0001 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 H02E0501
|
|
arc: M0 H01E0001
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q3
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0101 Q3
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 0110101010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
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enum: SLICEA.A0MUX 1
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enum: SLICEA.B0MUX 1
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enum: SLICEA.C0MUX 1
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enum: SLICEA.MODE LOGIC
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enum: SLICEA.CCU2.INJECT1_1 _NONE_
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enum: SLICEB.GSR DISABLED
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enum: SLICEB.REG1.SD 0
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enum: SLICEB.REG1.REGSET RESET
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enum: SLICEB.REG1.LSRMODE LSR
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enum: SLICEB.CEMUX CE
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enum: LSR0.SRMODE LSR_OVER_CE
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enum: LSR0.LSRMUX LSR
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enum: CLK0.CLKMUX CLK
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.tile R9C32:PLC2
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arc: H01W0100 W3_H06E0303
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.tile TAP_R11C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R11C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R12C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R12C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R13C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R13C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R14C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R14C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R15C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R15C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R16C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R18C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R19C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R21C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R24C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R24C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R25C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R25C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R26C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R26C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R27C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R27C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R28C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R29C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R29C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R2C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R2C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R30C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R30C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R3C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R3C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R4C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R4C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R5C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R5C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R6C13:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R6C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R7C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R8C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R9C31:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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arc: R_HPBX0000 G_VPTX0000
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