micheleandClaude Sonnet 5
63cac6a7e5
Implements optimization #2 from the final benchmark campaign's own recommendation, on top of DEC-0015's word-level burst rewrite: a new shared activation_cache.v module fetches a given activation (X) vector from PSRAM once instead of once per neuron sharing it - the exact redundant traffic pattern the dense-layer workloads in this project's benchmark suite exhibit. Each memory_manager's own prefetch_engine now fetches WEIGHTS only; the activation half is requested from the shared cache instead (single-tag, tile-granular, N_SLOTS request ports, its own real word-level PSRAM backend via a new dedicated arbiter port). dataflow_core.v/slot_mem_arbiter.v/neural_multiprocessor.v widened to N_SLOTS+1 ports to arbitrate the cache's traffic alongside each slot's weight traffic. Two real bugs found and fixed during implementation (ERR-0010): a target-bank/pending-bank race in memory_manager.v's activation-cache wiring (the same bug class ERR-0006 already fixed once for pf_target_bank - a later handoff's queued request can overwrite which bank an earlier, still-in-flight request's ack applies to), and a repeat of ERR-0009's N_SLOTS=1 zero-width replication bug in activation_cache.v itself. Real, measured results: the full final-benchmark campaign (24/24 workload/config combinations) re-verified bit-exact. D-Stress cycles fall a further 1.66-2.00x on top of DEC-0015 (~4x combined vs the original byte-level baseline). But the cache's real Fmax cost is much steeper than DEC-0015's own: N_SLOTS=2 (the recommended default, DEC-0014) drops from 133.58 to 87.72 MHz (-34%, margin over 80MHz shrinks from +67% to +9.7%), and N_SLOTS=4 drops to 65.01 MHz - now FAILING the 80MHz target it previously passed. Combined real wall-clock speedup vs the original baseline: N=1 3.86x, N=2 2.45x (both real net wins); N=4 is a real regression once its own now-failing Fmax is honestly used, though N=4 was never the recommended configuration. N_SLOTS=2 remains the recommended default (DEC-0014 unaffected) with a thinner but still real Fmax margin. Cache hit-detection pipelining is flagged as concrete follow-up work if N_SLOTS>2 is ever needed with the cache active - not attempted this round. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0016)/ experiments (EXP-0016)/errors (ERR-0010)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
144 lines
7.8 KiB
Plaintext
144 lines
7.8 KiB
Plaintext
# V2 timing log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
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nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
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--lpf-allow-unconstrained
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Fmax: 183.12 MHz -- PASS at 80 MHz (real place&route measurement)
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Critical path: job_ready -> TRELLIS_IO output pad (i.e. the design's
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own logic is NOT the bottleneck at this Fmax -- an unconstrained
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output pin dominates; a real system-level Fmax will differ once
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this signal is consumed on-chip instead of driven to a pad in
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isolation). Log: hardware/v2/synthesis/neural_processor_p8/nextpnr.log
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WNS/TNS: not reported by this nextpnr version in this invocation.
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[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
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Same command as above, ACC_WIDTH=24 build.
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Fmax: 176.21 MHz -- PASS at 80 MHz (real place&route measurement)
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Delta vs ACC_WIDTH=32: -6.91 MHz (-3.8%) despite FEWER resources --
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attributed to placement noise, not a real architectural effect
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(no seed sweep run to confirm either way -- see experiments.log
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EXP-0002 and benchmark.log). Log: hardware/v2/synthesis/
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neural_processor_p8_acc24/nextpnr.log
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[2026-09-05] EXP-0003 -- N_PROCESSORS sweep (P_IN=8), real nextpnr-ecp5
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--45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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N=1: Fmax=159.11 MHz PASS MULT18X18D 8/72 (11%)
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N=2: Fmax=149.59 MHz PASS MULT18X18D 16/72 (22%)
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N=4: Fmax=151.01 MHz PASS MULT18X18D 32/72 (44%)
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N=8: Fmax=134.70 MHz PASS MULT18X18D 64/72 (88%)
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TRELLIS_IO stays at 18/245 (7%) throughout (harness has only
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clk/rst/seed/checksum as real pins, by design -- see ERR-0005).
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See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource
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that will first prevent scaling N_PROCESSORS further at P_IN=8.
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[2026-09-05] EXP-0004 -- default-depth buffer configs, real nextpnr-ecp5
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activation_buffer (D=4096): Fmax=325.20 MHz PASS
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weight_buffer (D=512): Fmax=339.67 MHz PASS
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result_buffer (D=4096): Fmax=325.20 MHz PASS
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All far above the 80MHz target -- buffers are not a timing concern in
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isolation at these depths.
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[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (via
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harness_memory_manager.v, see errors.log ERR-0005 for why a harness
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was needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8
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--freq 80 --lpf-allow-unconstrained
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Fmax: 165.86 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0006 -- neural_director (via harness_neural_director.v,
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see errors.log ERR-0005 for why), real nextpnr-ecp5 --45k --package
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CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 250.50 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, standalone,
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no harness needed), real nextpnr-ecp5 --45k --package CABGA381
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--speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 155.30 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0008 -- dataflow_core (via harness_dataflow_core.v,
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see errors.log ERR-0005 for why a harness was needed), real
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nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
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--lpf-allow-unconstrained
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N_SLOTS=2: Fmax = 165.15 MHz -- PASS at 80MHz (real place&route)
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N_SLOTS=4: Fmax = 133.19 MHz -- PASS at 80MHz (real place&route)
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Fmax drops as N_SLOTS grows (more concurrent memory_manager+
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neural_processor instances competing for the same routing fabric
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around the shared neural_director/dependency_manager hub) -- both
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configs still clear the 80MHz target with real margin.
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[2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real
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standalone synthesis, no harness needed), real nextpnr-ecp5 --45k
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--package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 142.45 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0011 -- dataflow_core N_SLOTS=8 (via
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harness_dataflow_core.v), real nextpnr-ecp5 --45k --package CABGA381
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--speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 92.63 MHz -- PASS at 80MHz (real place&route measurement), but
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with a much thinner margin than N_SLOTS=2 (165.15 MHz) or N_SLOTS=4
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(133.19 MHz) -- Fmax falls monotonically with N_SLOTS (165.15 ->
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133.19 -> 92.63 MHz for N_SLOTS=2/4/8) as routing congestion around
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the shared neural_director/dependency_manager hub grows, while DSP
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usage (88.9% at N_SLOTS=8) approaches its hard ceiling at the same
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time -- see decisions.log DEC-0012.
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[2026-09-05] EXP-0012 -- ACC_WIDTH 24 vs 32 real placement-seed sweep
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(M10, "pipeline" axis, resolving EXP-0002's single-seed
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inconclusiveness), 5 additional real nextpnr-ecp5 seeds (1-5) plus the
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original default-seed run (EXP-0001/EXP-0002), same synthesized
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netlists (hardware/v2/synthesis/neural_processor_p8/top.json and
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neural_processor_p8_acc24/top.json), --45k --package CABGA381 --speed
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8 --freq 80 --lpf-allow-unconstrained
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ACC_WIDTH=32: seeds [default,1,2,3,4,5] -> [183.12, 164.85, 174.25,
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168.83, 183.96, 145.73] MHz. n=6, mean=170.12 MHz, min=145.73 MHz,
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max=183.96 MHz, stdev=14.16 MHz.
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ACC_WIDTH=24: seeds [default,1,2,3,4,5] -> [176.21, 183.72, 180.57,
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183.08, 185.49, 175.16] MHz. n=6, mean=180.71 MHz, min=175.16 MHz,
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max=185.49 MHz, stdev=4.21 MHz.
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Conclusion: over 6 real placement seeds, ACC_WIDTH=24 has a HIGHER
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mean Fmax (+10.6 MHz, +6.2%) AND a much lower seed-to-seed variance
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(stdev 4.21 vs 14.16 MHz, ~3.4x tighter) than ACC_WIDTH=32 --
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EXP-0002's single-seed result (176.21 < 183.12, i.e. ACC=24 looked
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WORSE) was placement-seed noise, not a real trend. See decisions.log
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DEC-0013.
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[2026-09-05] EXP-0014 -- neural_multiprocessor N_SLOTS=1 and N_SLOTS=4
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(final benchmark campaign), real nextpnr-ecp5 --45k --package CABGA381
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--speed 8 --freq 80 --lpf-allow-unconstrained
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N_SLOTS=1: Fmax = 152.46 MHz -- PASS at 80MHz
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N_SLOTS=4: Fmax = 113.38 MHz -- PASS at 80MHz
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(N_SLOTS=2 reference, EXP-0009: 142.45 MHz)
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Full real N_SLOTS sweep for the complete system (dataflow_core + real
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V1 PSRAM chain + slot_mem_arbiter): 1 -> 152.46 MHz, 2 -> 142.45 MHz,
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4 -> 113.38 MHz. Fmax falls monotonically as N_SLOTS grows (more
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routing congestion around the shared director/dependency_manager/
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arbiter hub), exactly the same trend already observed for
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dataflow_core alone (M7/M10, EXP-0008/EXP-0011) but now measured for
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the REAL FULL SYSTEM including the real PSRAM backend.
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[2026-09-05] EXP-0015 -- neural_multiprocessor N_SLOTS=1/2/4 after the
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word-level burst-read rewrite (DEC-0015), real nextpnr-ecp5 --45k
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--package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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N_SLOTS=1: Fmax = 152.44 MHz -- PASS at 80MHz (was 152.46 MHz, unchanged)
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N_SLOTS=2: Fmax = 133.58 MHz -- PASS at 80MHz (was 142.45 MHz, -6.2%)
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N_SLOTS=4: Fmax = 112.07 MHz -- PASS at 80MHz (was 113.38 MHz, -1.2%)
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Small, real Fmax cost from widening the shared arbiter/backend to
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16-bit + lb_n/ub_n (extra routing), overwhelmingly outweighed by the
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real cycle-count reduction (EXP-0015 in experiments.log/benchmark.log):
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D-Stress real wall-clock improves 2.24-2.37x at every N_SLOTS.
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[2026-09-05] EXP-0016 -- neural_multiprocessor N_SLOTS=1/2/4 after
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adding activation_cache.v (DEC-0016), real nextpnr-ecp5 --45k
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--package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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N_SLOTS=1: Fmax = 131.79 MHz -- PASS at 80MHz (was 152.44 MHz, -13.5%)
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N_SLOTS=2: Fmax = 87.72 MHz -- PASS at 80MHz (was 133.58 MHz, -34.3%)
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N_SLOTS=4: Fmax = 65.01 MHz -- FAILS at 80MHz (was 112.07 MHz, -42.0%)
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Real, substantial Fmax cost from the shared activation_cache -- a
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single central resource with N_SLOTS request ports, a broadcast-
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capable hit-check evaluated every cycle for every port, and a shared
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tile_store array. Cost grows much faster with N_SLOTS than
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DEC-0015's own arbiter widening did. N_SLOTS=4 is no longer a passing
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80MHz design point with the cache active -- see decisions.log
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DEC-0016 for the full analysis and why N_SLOTS=2 (the recommended
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default, DEC-0014) is unaffected in its own recommendation.
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