micheleandClaude Sonnet 5
a2bd60e305
Implements the rest of the SPI interface (docs §8.1) on top of spi_slave.v from the previous commit: - rtl/spi_engine.v: opcode FSM + register bank, all 8 opcodes (NOP, WRITE_RAM, READ_RAM, RESET, SET_BASE, START, STATUS, READ_OUTPUT, READ_CONFIG). tx_byte is driven combinationally from live state (not reactively on tx_byte_req), applying the prefetch-vs-consume contract documented on spi_slave.v. STATUS.done is a sticky, clear-on-read latch. RAM master port uses the same byte-level convention as neuron_memory.v's external mem_* port. - rtl/mem_arbiter.v: fixed-priority (neuron_memory > spi_engine) grant-and-forward arbiter sharing one byte-level memory port between spi_engine's WRITE_RAM/READ_RAM and neuron_memory's own X/W/bias reads during a run. - rtl/spi_neuron_top.v: full integration -- spi_slave -> spi_engine -> mem_arbiter -> a single shared int8_memory_access -> memory_interface -> psram_controller -> PSRAM pins. neuron_memory's rst is global rst OR'd with the RESET opcode's soft-reset pulse. The host has no direct electrical path to the RAM, only through this chain. Testing: - sim/spi_engine_tb.v: 10 tests (one per opcode + WRITE_RAM/READ_RAM, START idle-vs-busy, STATUS sticky/clear-on-read, extra-MOSI-bytes- ignored, back-to-back transactions) against a synthetic 2-cycle- latency RAM model, isolating the opcode FSM from PSRAM timing. Found and fixed two testbench-only bugs (RTL needed no change): the same delta-zero clock-edge race as spi_slave_tb.v (blocking `nm_done=1` landing on the same sim time as a posedge -- fixed via negedge-based pulsing) and a missing RAM sentinel initialization. - sim/spi_neuron_top_tb.v: end-to-end test against the **real** psram_model.v (not a mock) -- RESET/READ_CONFIG/WRITE_RAM/ READ_RAM/SET_BASE/START/STATUS/READ_OUTPUT all driven purely over simulated SPI. 3/3 scenarios (sum, saturation, ReLU) pass on the first attempt; confirms the arbiter and shared byte<->word bridge are correct against real PSRAM timing, not just a synthetic mock. Real-toolchain verification (Yosys + nextpnr-ecp5 + ecppack): spi_slave.v and spi_engine.v synthesize clean and comfortably clear 80 MHz in isolation (403 MHz / 191 MHz, no DSP usage). The full spi_neuron_top.v integration, however, does NOT meet 80 MHz (~52-56 MHz depending on PARALLEL) -- the critical path is entirely inside neuron_parallel.v's existing saturation comparator (no contribution from the new SPI/arbiter logic), but its routed delay is ~57% worse than in the isolated benchmark due to placement/ routing congestion once SPI + PSRAM logic shares the fabric with it, not resource exhaustion (2% DSP usage). Documented as a Phase 4/7 finding in docs/FPGA-NeuralNetwork-Engine.md -- a floorplanning/ pipelining problem for Phase 7, not a functional-correctness issue (verified independently in simulation against real PSRAM timing). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
148 lines
4.1 KiB
Verilog
148 lines
4.1 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// MEM_ARBITER
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//
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// Arbitrates a single shared byte-level memory master port (feeding
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// a shared int8_memory_access -> memory_interface -> psram_controller
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// chain) between two byte-level requesters:
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//
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// Port A: spi_engine.v (WRITE_RAM / READ_RAM opcodes)
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// Port B: neuron_memory.v (its own X/W/bias reads during a run)
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//
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// Fixed priority B > A when both request on the same idle cycle
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// (an in-progress inference is treated as more time-critical than a
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// newly-arriving SPI RAM access). Once a port is granted, the
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// arbiter holds ownership until that single transaction's m_ready
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// pulse, then releases -- both A and B already issue `req` as a
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// clean one-cycle pulse (matching int8_memory_access's own
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// contract), so a simple grant-and-forward design is sufficient;
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// no request queuing/pipelining is needed.
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// ================================================================
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module mem_arbiter #(
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parameter ADDR_WIDTH = 22
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)(
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input wire clk,
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input wire rst,
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// ------------------------------------------------------------
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// Port A - spi_engine
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// ------------------------------------------------------------
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input wire a_req,
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input wire a_wr,
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input wire [ADDR_WIDTH-1:0] a_addr,
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input wire signed [7:0] a_wdata,
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output reg signed [7:0] a_rdata,
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output reg a_ready,
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// ------------------------------------------------------------
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// Port B - neuron_memory
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// ------------------------------------------------------------
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input wire b_req,
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input wire b_wr,
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input wire [ADDR_WIDTH-1:0] b_addr,
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input wire signed [7:0] b_wdata,
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output reg signed [7:0] b_rdata,
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output reg b_ready,
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// ------------------------------------------------------------
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// Shared master port
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// ------------------------------------------------------------
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output reg m_req,
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output reg m_wr,
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output reg [ADDR_WIDTH-1:0] m_addr,
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output reg signed [7:0] m_wdata,
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input wire signed [7:0] m_rdata,
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input wire m_ready
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);
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localparam SEL_NONE = 2'd0;
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localparam SEL_A = 2'd1;
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localparam SEL_B = 2'd2;
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reg [1:0] owner;
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always @(posedge clk) begin
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if (rst) begin
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owner <= SEL_NONE;
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m_req <= 1'b0;
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m_wr <= 1'b0;
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m_addr <= {ADDR_WIDTH{1'b0}};
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m_wdata <= 8'sd0;
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a_rdata <= 8'sd0;
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a_ready <= 1'b0;
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b_rdata <= 8'sd0;
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b_ready <= 1'b0;
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end else begin
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m_req <= 1'b0;
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a_ready <= 1'b0;
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b_ready <= 1'b0;
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case (owner)
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SEL_NONE: begin
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if (b_req) begin
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owner <= SEL_B;
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m_req <= 1'b1;
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m_wr <= b_wr;
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m_addr <= b_addr;
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m_wdata <= b_wdata;
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end else if (a_req) begin
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owner <= SEL_A;
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m_req <= 1'b1;
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m_wr <= a_wr;
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m_addr <= a_addr;
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m_wdata <= a_wdata;
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end
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end
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SEL_A: begin
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if (m_ready) begin
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a_rdata <= m_rdata;
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a_ready <= 1'b1;
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owner <= SEL_NONE;
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end
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end
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SEL_B: begin
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if (m_ready) begin
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b_rdata <= m_rdata;
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b_ready <= 1'b1;
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owner <= SEL_NONE;
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end
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end
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default: begin
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owner <= SEL_NONE;
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end
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endcase
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end
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end
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endmodule
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