micheleandClaude Sonnet 5
6caea54b8e
Replaced three uses of the SystemVerilog '0 self-sizing literal with explicit-width zero-fill so the file synthesizes under Vivado's synth_design (which has no -sv equivalent in this flow), needed while adding this module to the real in-context P&R project. Re-running its isolated regression after that edit surfaced 3/8 failures. Root-caused via git stash (reproduces on the untouched committed file, not caused by this edit) and a DUT-internal $display: tb_neural_director_packed.v's own submit_job task drove DUT inputs with blocking assignment across two separate @(posedge clk) waits, racing the DUT's own always block under Icarus and causing a spurious duplicate enqueue. Fixed by switching to nonblocking assignment (race-free by construction). neural_director_packed.v itself was correct all along - 8/8 tests pass after the testbench fix. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
326 lines
16 KiB
Verilog
326 lines
16 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// Isolated correctness test for neural_director_packed.v's own
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// scheduling/pairing logic -- mirrors hardware/v2/sim/tb_neural_
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// director.v's own scope decision (DEC-0007): each slot gets a
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// lightweight BEHAVIORAL stub (fixed-latency job_start->job_done,
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// scoreboard of what it received) instead of a real packed core +
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// memory path -- neural_processor_packed.v's own compute correctness
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// is already verified (EXP-0059/0062); THIS test isolates whether
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// the Director pairs/dispatches/tracks completion correctly, per
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// this project's own "one variable at a time" discipline.
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//
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// Coverage:
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// 1) matched-w_base pairs dispatch correctly (x_base_a/b, w_base,
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// n_tiles, result_addr_a/b, node_id_a/b all land on the right
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// slot, right fields).
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// 2) MISMATCHED w_base between consecutive jobs: Director must
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// stall (not mis-pair, not error) until a job arrives that
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// matches the still-head-of-queue job.
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// 3) more pairs submitted than slots: third pair waits in queue
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// until a slot frees.
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// 4) backpressure: queue fills, job_in_ready deasserts, recovers.
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// ============================================================
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module tb;
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localparam ADDR_WIDTH = 26;
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localparam N_SLOTS = 2;
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localparam QUEUE_DEPTH = 8;
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reg clk, rst;
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initial begin clk = 0; forever #5 clk = ~clk; end
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reg job_in_valid;
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wire job_in_ready;
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reg [ADDR_WIDTH-1:0] job_in_x_base, job_in_w_base, job_in_result_addr;
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reg [15:0] job_in_n_tiles, job_in_node_id;
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wire [N_SLOTS-1:0] slot_job_start;
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wire [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base_a, slot_x_base_b, slot_w_base;
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wire [ADDR_WIDTH*N_SLOTS-1:0] slot_result_addr_a, slot_result_addr_b;
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wire [16*N_SLOTS-1:0] slot_n_tiles, slot_node_id_a, slot_node_id_b;
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reg [N_SLOTS-1:0] slot_job_done;
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wire job_out_done;
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wire [$clog2(N_SLOTS)-1:0] job_out_slot;
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wire [3:0] dir_state;
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wire dir_error;
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neural_director_packed #(
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.ADDR_WIDTH(ADDR_WIDTH), .N_SLOTS(N_SLOTS), .QUEUE_DEPTH(QUEUE_DEPTH)
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) u_dir (
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.clk(clk), .rst(rst),
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.job_in_valid(job_in_valid), .job_in_ready(job_in_ready),
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.job_in_x_base(job_in_x_base), .job_in_w_base(job_in_w_base),
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.job_in_n_tiles(job_in_n_tiles), .job_in_result_addr(job_in_result_addr),
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.job_in_node_id(job_in_node_id),
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.slot_job_start(slot_job_start),
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.slot_x_base_a(slot_x_base_a), .slot_x_base_b(slot_x_base_b),
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.slot_w_base(slot_w_base), .slot_n_tiles(slot_n_tiles),
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.slot_result_addr_a(slot_result_addr_a), .slot_result_addr_b(slot_result_addr_b),
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.slot_node_id_a(slot_node_id_a), .slot_node_id_b(slot_node_id_b),
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.slot_job_done(slot_job_done),
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.job_out_done(job_out_done), .job_out_slot(job_out_slot),
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.dir_state(dir_state), .dir_error(dir_error)
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);
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// ---- behavioral slot stubs: fixed 6-cycle latency job_start ->
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// job_done, scoreboard of last-received fields per slot ----
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reg [ADDR_WIDTH-1:0] scb_xa [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] scb_xb [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] scb_w [0:N_SLOTS-1];
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reg [15:0] scb_nt [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] scb_ra [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] scb_rb [0:N_SLOTS-1];
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reg [15:0] scb_na [0:N_SLOTS-1];
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reg [15:0] scb_nb [0:N_SLOTS-1];
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reg [3:0] stub_cnt [0:N_SLOTS-1];
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reg stub_busy [0:N_SLOTS-1];
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integer si;
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always @(posedge clk) begin
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if (rst) begin
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for (si = 0; si < N_SLOTS; si = si + 1) begin
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stub_busy[si] <= 1'b0;
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stub_cnt[si] <= 4'd0;
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end
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slot_job_done <= {N_SLOTS{1'b0}};
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end else begin
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slot_job_done <= {N_SLOTS{1'b0}};
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for (si = 0; si < N_SLOTS; si = si + 1) begin
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if (slot_job_start[si]) begin
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scb_xa[si] <= slot_x_base_a[si*ADDR_WIDTH +: ADDR_WIDTH];
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scb_xb[si] <= slot_x_base_b[si*ADDR_WIDTH +: ADDR_WIDTH];
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scb_w[si] <= slot_w_base[si*ADDR_WIDTH +: ADDR_WIDTH];
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scb_nt[si] <= slot_n_tiles[si*16 +: 16];
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scb_ra[si] <= slot_result_addr_a[si*ADDR_WIDTH +: ADDR_WIDTH];
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scb_rb[si] <= slot_result_addr_b[si*ADDR_WIDTH +: ADDR_WIDTH];
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scb_na[si] <= slot_node_id_a[si*16 +: 16];
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scb_nb[si] <= slot_node_id_b[si*16 +: 16];
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stub_busy[si] <= 1'b1;
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stub_cnt[si] <= 4'd0;
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end else if (stub_busy[si]) begin
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if (stub_cnt[si] == 4'd15) begin
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slot_job_done[si] <= 1'b1;
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stub_busy[si] <= 1'b0;
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end else begin
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stub_cnt[si] <= stub_cnt[si] + 1'b1;
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end
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end
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end
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end
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end
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integer errors, tests;
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// Drives DUT inputs with NONBLOCKING assignment (<=), not blocking
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// (=). Root-caused this session: the previous blocking-assignment
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// version raced neural_director_packed.v's own posedge-triggered
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// always block -- Icarus does not consistently order "testbench
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// process resumes from @(posedge clk) and executes a blocking
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// write" against "DUT's always @(posedge clk) block reads that
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// same signal" when both wake on the SAME edge, and the ordering
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// was observed to differ between the SET edge and the CLEAR edge
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// within the same task call (confirmed via a DUT-internal $display
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// showing job_in_valid sampled as 1 on TWO consecutive edges from
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// a single submit_job call, both times with the FIRST job's stale
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// x_base -- a spurious duplicate enqueue, not a Director bug: the
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// committed neural_director_packed.v was re-verified bit-identical
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// via the same test with this fix applied). Nonblocking assignment
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// removes the race entirely: NBA updates land strictly after the
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// Active region where the DUT's own always block runs, so the DUT
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// always samples the OLD value at the driving edge and the NEW
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// value only from the NEXT edge onward -- deterministic by the
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// language, not by scheduler luck.
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task automatic submit_job(
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input [ADDR_WIDTH-1:0] xb, input [ADDR_WIDTH-1:0] wb,
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input [15:0] nt, input [ADDR_WIDTH-1:0] resaddr, input [15:0] nid
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);
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begin
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@(posedge clk);
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job_in_x_base <= xb; job_in_w_base <= wb; job_in_n_tiles <= nt;
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job_in_result_addr <= resaddr; job_in_node_id <= nid;
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job_in_valid <= 1'b1;
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@(posedge clk);
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while (!job_in_ready) @(posedge clk);
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job_in_valid <= 1'b0;
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@(posedge clk);
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end
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endtask
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task automatic check_scb(
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input integer slot, input [ADDR_WIDTH-1:0] xa, input [ADDR_WIDTH-1:0] xb,
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input [ADDR_WIDTH-1:0] w, input [15:0] nt,
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input [ADDR_WIDTH-1:0] ra, input [ADDR_WIDTH-1:0] rb,
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input [15:0] na, input [15:0] nb
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);
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begin
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tests = tests + 1;
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if (scb_xa[slot] !== xa || scb_xb[slot] !== xb || scb_w[slot] !== w ||
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scb_nt[slot] !== nt || scb_ra[slot] !== ra || scb_rb[slot] !== rb ||
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scb_na[slot] !== na || scb_nb[slot] !== nb) begin
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$display("FAIL slot %0d scoreboard: xa=%0d(exp %0d) xb=%0d(exp %0d) w=%0d(exp %0d) nt=%0d(exp %0d) ra=%0d(exp %0d) rb=%0d(exp %0d) na=%0d(exp %0d) nb=%0d(exp %0d)",
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slot, scb_xa[slot], xa, scb_xb[slot], xb, scb_w[slot], w, scb_nt[slot], nt,
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scb_ra[slot], ra, scb_rb[slot], rb, scb_na[slot], na, scb_nb[slot], nb);
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errors = errors + 1;
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end else begin
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$display("PASS slot %0d scoreboard: pair (node %0d,%0d) w_base=%0d correctly dispatched", slot, na, nb, w);
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end
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end
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endtask
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integer wd;
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initial begin
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errors = 0; tests = 0;
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rst = 1; job_in_valid = 0; job_in_x_base = 0; job_in_w_base = 0;
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job_in_n_tiles = 0; job_in_result_addr = 0; job_in_node_id = 0;
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repeat(4) @(posedge clk);
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rst = 0;
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@(posedge clk);
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$display("=== TEST 1: matched-w_base pair, single dispatch ===");
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submit_job(26'h1000, 26'h2000, 16'd16, 26'h5000, 16'd1); // pos A
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submit_job(26'h1100, 26'h2000, 16'd16, 26'h5001, 16'd2); // pos B, SAME w_base -> pairs with A
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wd = 0; while (!slot_job_start[0] && !slot_job_start[1] && wd < 100) begin @(posedge clk); wd = wd + 1; end
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@(posedge clk);
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if (slot_job_start[0] || u_dir.slot_busy[0])
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check_scb(0, 26'h1000, 26'h1100, 26'h2000, 16'd16, 26'h5000, 26'h5001, 16'd1, 16'd2);
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else
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check_scb(1, 26'h1000, 26'h1100, 26'h2000, 16'd16, 26'h5000, 26'h5001, 16'd1, 16'd2);
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wd = 0; while (!job_out_done && wd < 100) begin @(posedge clk); wd = wd + 1; end
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if (!job_out_done) begin $display("FAIL: TEST1 pair never completed"); errors = errors + 1; end
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$display("=== TEST 2: MISMATCHED w_base -- Director must stall, not mis-pair ===");
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repeat(3) @(posedge clk);
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submit_job(26'h3000, 26'h4000, 16'd8, 26'h5002, 16'd10); // w_base=0x4000
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submit_job(26'h3100, 26'h4100, 16'd8, 26'h5003, 16'd11); // DIFFERENT w_base=0x4100 -- must NOT pair with the above
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repeat(20) @(posedge clk);
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tests = tests + 1;
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if (u_dir.q_count < 2) begin
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$display("FAIL TEST2: mismatched-w_base jobs were dispatched (q_count=%0d, expected 2 still queued)", u_dir.q_count);
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errors = errors + 1;
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end else begin
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$display("PASS TEST2: mismatched-w_base pair correctly NOT dispatched, both still queued (q_count=%0d)", u_dir.q_count);
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end
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// now submit a job that DOES match the second one (0x4100) --
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// Director should still be stuck on the FIRST two (head pair,
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// 0x4000/0x4100 mismatch) since pairing only ever looks at
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// q_head/q_head+1, confirming it doesn't skip ahead either.
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submit_job(26'h3200, 26'h4100, 16'd8, 26'h5004, 16'd12);
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repeat(20) @(posedge clk);
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tests = tests + 1;
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if (u_dir.q_count < 3) begin
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$display("FAIL TEST2b: Director skipped ahead past the mismatched head pair (q_count=%0d, expected 3 still queued)", u_dir.q_count);
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errors = errors + 1;
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end else begin
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$display("PASS TEST2b: Director correctly did NOT skip ahead past the still-mismatched head pair (q_count=%0d)", u_dir.q_count);
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end
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$display("=== TEST 3: two full pairs dispatch to both slots, third pair waits ===");
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repeat(20) @(posedge clk); // let TEST2's stalled pair finish draining first isn't needed -- fresh w_base below won't match TEST2's stuck head, so submit a THIRD job matching 0x4100 is already queued; just proceed with a fresh w_base group not colliding with TEST2's stuck entries by construction (TEST2's own pair will eventually complete once we feed it a match -- but we deliberately do NOT, to keep proving the stall holds; instead reset here for a clean TEST3)
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rst = 1; repeat(3) @(posedge clk); rst = 0; @(posedge clk);
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// check "both slots busy, third pair still queued" RIGHT AFTER
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// the first two pairs are submitted -- before submitting the
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// third, so the stub's own fixed completion latency (6 cycles)
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// cannot race ahead of this check regardless of how long
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// submit_job's own handshake takes.
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submit_job(26'hA000, 26'hB000, 16'd4, 26'h6000, 16'd20);
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submit_job(26'hA100, 26'hB000, 16'd4, 26'h6001, 16'd21); // pairs with above -> slot X
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submit_job(26'hA200, 26'hB100, 16'd4, 26'h6002, 16'd22);
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submit_job(26'hA300, 26'hB100, 16'd4, 26'h6003, 16'd23); // pairs with above -> slot Y (both slots now busy)
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repeat(4) @(posedge clk); // settle: DIR_SCAN_READY/DIR_ALLOCATE take a couple cycles per
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// dispatch, and submit_job's own return doesn't guarantee the
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// Director's own (independent) FSM has caught up yet
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tests = tests + 1;
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if (!(u_dir.slot_busy[0] && u_dir.slot_busy[1])) begin
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$display("FAIL TEST3: both slots should be busy after 2 pairs dispatched (slot_busy=%b)", u_dir.slot_busy);
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errors = errors + 1;
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end else begin
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$display("PASS TEST3: both slots busy after dispatching 2 pairs (slot_busy=%b)", u_dir.slot_busy);
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end
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submit_job(26'hA400, 26'hB200, 16'd4, 26'h6004, 16'd24);
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submit_job(26'hA500, 26'hB200, 16'd4, 26'h6005, 16'd25); // pairs, but must WAIT (no free slot)
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tests = tests + 1;
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if (u_dir.q_count < 2) begin
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$display("FAIL TEST3: third pair should still be queued while both slots are busy (q_count=%0d)", u_dir.q_count);
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errors = errors + 1;
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end else begin
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$display("PASS TEST3: third pair correctly waiting while both slots busy (q_count=%0d)", u_dir.q_count);
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end
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wd = 0;
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begin : test3_drain
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integer completions;
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completions = 0;
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while (completions < 3 && wd < 200) begin
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@(posedge clk);
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wd = wd + 1;
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if (job_out_done) completions = completions + 1;
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end
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tests = tests + 1;
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if (completions < 3) begin
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$display("FAIL TEST3: only %0d/3 pairs completed within watchdog", completions);
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errors = errors + 1;
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end else begin
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$display("PASS TEST3: all 3 pairs completed (third one dispatched once a slot freed)");
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end
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end
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$display("=== TEST 4: backpressure -- queue fills past capacity, job_in_ready deasserts and recovers ===");
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rst = 1; repeat(3) @(posedge clk); rst = 0; @(posedge clk);
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// occupy BOTH slots first (different w_base than the flood
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// below, and the stub's own long fixed latency, 16 cycles)
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// keeps them busy for the whole push phase, so the flood
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// below genuinely tests the QUEUE filling, not a queue that
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// keeps draining as fast as it fills.
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submit_job(26'hE000, 26'hF000, 16'd4, 26'h7800, 16'd40);
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submit_job(26'hE100, 26'hF000, 16'd4, 26'h7801, 16'd41);
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submit_job(26'hE200, 26'hF100, 16'd4, 26'h7802, 16'd42);
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submit_job(26'hE300, 26'hF100, 16'd4, 26'h7803, 16'd43);
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begin : test4_fill
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integer j;
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j = 0;
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while (job_in_ready && j < QUEUE_DEPTH + 2) begin
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@(posedge clk);
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job_in_x_base = 26'hC000;
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job_in_w_base = 26'hD000; // same w_base every push -> always pairs, but both real slots stay busy so nothing drains
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job_in_n_tiles = 16'd4;
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job_in_result_addr = 26'h7000;
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job_in_node_id = 16'd50 + j[15:0];
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job_in_valid = 1'b1;
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@(posedge clk);
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job_in_valid = 1'b0;
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j = j + 1;
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end
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tests = tests + 1;
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if (j > QUEUE_DEPTH) begin
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$display("FAIL TEST4: job_in_ready never deasserted after %0d pushes (QUEUE_DEPTH=%0d)", j, QUEUE_DEPTH);
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errors = errors + 1;
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end else begin
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$display("PASS TEST4: job_in_ready correctly deasserted after %0d queued jobs (QUEUE_DEPTH=%0d)", j, QUEUE_DEPTH);
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end
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end
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job_in_valid = 1'b0;
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wd = 0; while (!job_in_ready && wd < 500) begin @(posedge clk); wd = wd + 1; end
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tests = tests + 1;
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if (!job_in_ready) begin
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$display("FAIL TEST4: job_in_ready never recovered within watchdog");
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errors = errors + 1;
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end else begin
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$display("PASS TEST4: job_in_ready recovered once slots/queue drained");
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end
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$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
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if (errors == 0) $display("ALL TESTS PASSED (tb_neural_director_packed)");
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$finish;
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end
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endmodule
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