micheleandClaude Sonnet 5
97a21be240
Adds FPGA-exclusive access to the onboard W25Q128JV SPI NOR flash for weights/bias/network persistence, layered as spi_flash_master (raw SPI, USRMCLK-driven) -> flash_copy_engine (flash<->PSRAM streaming, erase- before-write, Page Program loop) -> flash_slot_manager (16-slot catalog with CRC32), exposed via 8 new SPI opcodes (0x40-0x47). Fixes two pre-existing bugs found during bring-up: a psram_controller.v request lost during power-up, and a one-cycle-pulse race in the PSRAM arbiter request handshake. Full simulation + real Yosys/nextpnr-ecp5 synthesis verification (0 errors, Fmax 66.68MHz) in WORKLOG.md and docs/FPGA-Neural-Flash-Subsystem-Verification.md. Also updates docs/pinout to reflect the 56-signal real .lpf (3 new flash pins) and documents the WRITE_RAM/READ_RAM host backpressure risk found while testing this subsystem. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
113 lines
4.8 KiB
Python
113 lines
4.8 KiB
Python
#!/usr/bin/env python3
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"""
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Generates synth/ecp5/spi_neuron_top.lpf (LOCATE/IOBUF constraints) for
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spi_neuron_top's SPI + PSRAM ports on the real LFE5U-45F-8BG381C part,
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using Project Trellis's own device database as the source of ball/bank/
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dual-function data (the same data nextpnr-ecp5 itself uses) -- not
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invented numbers.
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Requires prjtrellis installed (Homebrew: `brew install prjtrellis`) and
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its iodb.json for LFE5U-45F. See docs/FPGA-Neural-Hardware-Design.md §7
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for the full placement rationale (bank/die-edge geometry, why banks 2+3
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hold the PSRAM bus and bank 7 holds SPI/clock/reset).
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Re-run this whenever the port list of rtl/spi_neuron_top.v's top-level
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SPI/PSRAM interface changes (ADDR_WIDTH, MEM_DATA_WIDTH, etc.) -- it does
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NOT try to read the RTL; the port list/widths are hardcoded below and
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must be kept in sync by hand.
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"""
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import json
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import re
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import glob
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import sys
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CLK_BALL = "H5" # GR_PCLK7_0, bank 7 -- dedicated global clock pad
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ADDR_BITS = 23 # ADDR_WIDTH (byte address); only [21:0] carry real address, see §3
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DATA_BITS = 16 # MEM_DATA_WIDTH
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def find_iodb():
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candidates = glob.glob(
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"/opt/homebrew/Cellar/prjtrellis/*/share/trellis/database/ECP5/LFE5U-45F/iodb.json"
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) + glob.glob(
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"/usr/share/trellis/database/ECP5/LFE5U-45F/iodb.json"
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)
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if not candidates:
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sys.exit("prjtrellis iodb.json not found -- install prjtrellis (brew install prjtrellis)")
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return candidates[0]
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def load_balls(iodb_path, package="CABGA381"):
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d = json.load(open(iodb_path))
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pkg = d["packages"][package]
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meta_idx = {}
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for m in d["pio_metadata"]:
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meta_idx.setdefault((m["col"], m["row"], m["pio"]), []).append(m)
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out = {}
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for ball, info in pkg.items():
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key = (info["col"], info["row"], info["pio"])
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metas = meta_idx.get(key, [])
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bank = metas[0]["bank"] if metas else None
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funcs = sorted(set(m.get("function", "") for m in metas if m.get("function")))
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out[ball] = dict(col=info["col"], row=info["row"], bank=bank, funcs=funcs)
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return out
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def bank_balls(rows, bank, exclude=()):
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items = [(b, v) for b, v in rows.items() if v["bank"] == bank and b not in exclude]
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plain = sorted((x for x in items if not x[1]["funcs"]), key=lambda x: (x[1]["row"], x[1]["col"], x[0]))
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special = sorted((x for x in items if x[1]["funcs"]), key=lambda x: (x[1]["row"], x[1]["col"], x[0]))
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return plain + special
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def assign(rows):
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psram_pool = bank_balls(rows, 2) + bank_balls(rows, 3)
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ctrl_pool = bank_balls(rows, 7, exclude={CLK_BALL})
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a = {}
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for i, (ball, _) in enumerate(psram_pool[0:ADDR_BITS - 1]):
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a[f"psram_a[{i}]"] = ball
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for i, (ball, _) in enumerate(psram_pool[ADDR_BITS - 1:ADDR_BITS - 1 + DATA_BITS]):
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a[f"psram_dq[{i}]"] = ball
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ctrl_names = ["psram_ce_n", "psram_oe_n", "psram_we_n", "psram_lb_n", "psram_ub_n", "psram_zz_n"]
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for name, (ball, _) in zip(ctrl_names, psram_pool[ADDR_BITS - 1 + DATA_BITS:ADDR_BITS - 1 + DATA_BITS + 6]):
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a[name] = ball
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a[f"psram_a[{ADDR_BITS - 1}]"] = psram_pool[ADDR_BITS - 1 + DATA_BITS + 6][0] # always-0 spare bit
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# Application SPI + reset + host attention pins (irq_n/data_ready_n,
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# added 2026-09-03), all in bank 7 alongside clk -- kept away from
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# the PSRAM bus (banks 2+3) per the same "opposite edges" rationale
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# as the SPI signals. flash_mosi/flash_miso/flash_cs_n (added
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# 2026-09-04, flash-subsystem F5) join the same pool for the same
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# reason -- this is the APPLICATION-side master toward the
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# boot/persistence flash (rtl/spi_flash_master.v), physically
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# distinct pins from both the host SPI above and the dedicated
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# config-SPI pins (never touched by user logic, see
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# docs/FPGA-Neural-Hardware-Design.md §6). No flash_sclk pin here:
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# that clock is generated internally via the USRMCLK primitive
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# (see rtl/spi_flash_master.v's header for the full ECP5
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# rationale), not a normal constrainable I/O.
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spi_names = ["sclk", "mosi", "miso", "cs_n", "rst", "irq_n", "data_ready_n",
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"flash_mosi", "flash_miso", "flash_cs_n"]
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for name, (ball, _) in zip(spi_names, ctrl_pool[0:10]):
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a[name] = ball
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a["clk"] = CLK_BALL
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return a
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def write_lpf(assignment, path):
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lines = ["BLOCK ASYNCPATHS;", "BLOCK RESETPATHS;", ""]
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for sig, ball in sorted(assignment.items()):
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lines.append(f'LOCATE COMP "{sig}" SITE "{ball}";')
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lines.append(f'IOBUF PORT "{sig}" IO_TYPE=LVCMOS33;')
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lines.append("")
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open(path, "w").write("\n".join(lines))
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if __name__ == "__main__":
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out_path = sys.argv[1] if len(sys.argv) > 1 else "synth/ecp5/spi_neuron_top.lpf"
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rows = load_balls(find_iodb())
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assignment = assign(rows)
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write_lpf(assignment, out_path)
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print(f"wrote {len(assignment)} signal constraints to {out_path}")
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