micheleandClaude Sonnet 5
97a21be240
Adds FPGA-exclusive access to the onboard W25Q128JV SPI NOR flash for weights/bias/network persistence, layered as spi_flash_master (raw SPI, USRMCLK-driven) -> flash_copy_engine (flash<->PSRAM streaming, erase- before-write, Page Program loop) -> flash_slot_manager (16-slot catalog with CRC32), exposed via 8 new SPI opcodes (0x40-0x47). Fixes two pre-existing bugs found during bring-up: a psram_controller.v request lost during power-up, and a one-cycle-pulse race in the PSRAM arbiter request handshake. Full simulation + real Yosys/nextpnr-ecp5 synthesis verification (0 errors, Fmax 66.68MHz) in WORKLOG.md and docs/FPGA-Neural-Flash-Subsystem-Verification.md. Also updates docs/pinout to reflect the 56-signal real .lpf (3 new flash pins) and documents the WRITE_RAM/READ_RAM host backpressure risk found while testing this subsystem. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
7548 lines
158 KiB
Plaintext
7548 lines
158 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R17C89:CIB_LR
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arc: W3_H06W0303 JQ5
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.tile CIB_R19C1:CIB_LR
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arc: E3_H06E0303 S3_V06N0303
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.tile CIB_R19C89:CIB_LR
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arc: W3_H06W0303 JF5
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.tile CIB_R1C27:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C29:CIB
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arc: E3_H06E0003 JQ0
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.tile CIB_R1C30:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C31:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C32:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C33:CIB
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arc: JA0 S1_V02N0501
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arc: S3_V06S0003 W3_H06E0003
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arc: S3_V06S0103 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C34:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C35:CIB
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arc: S1_V02S0001 W3_H06E0003
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arc: S3_V06S0003 E3_H06W0003
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arc: S3_V06S0103 E3_H06W0103
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.tile CIB_R1C36:CIB
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arc: E1_H01E0001 E3_H06W0003
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arc: S1_V02S0001 JQ0
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arc: S3_V06S0003 E1_H01W0000
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arc: S3_V06S0103 E3_H06W0103
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arc: S3_V06S0203 E3_H06W0203
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.tile CIB_R1C37:CIB
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arc: H01W0000 JQ0
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arc: S1_V02S0201 E3_H06W0103
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arc: S3_V06S0003 H06W0003
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arc: S3_V06S0103 H06W0103
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arc: S3_V06S0203 H01E0001
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.tile CIB_R1C38:CIB
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0103 E3_H06W0103
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.tile CIB_R1C39:CIB
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arc: S3_V06S0103 E3_H06W0103
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C40:CIB
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arc: S3_V06S0003 H06W0003
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arc: S3_V06S0203 H06W0203
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arc: W3_H06W0003 E3_H06W0303
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C41:CIB
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R1C42:CIB
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arc: JA0 S1_V02N0701
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arc: W3_H06W0003 E1_H01W0000
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0103
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enum: CIB.JB0MUX 0
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.tile CIB_R1C43:CIB
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arc: H01W0000 JQ0
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arc: W3_H06W0003 E1_H01W0000
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arc: W3_H06W0103 E3_H06W0003
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arc: W3_H06W0203 E3_H06W0203
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.tile CIB_R1C44:CIB
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arc: H01W0000 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C45:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C46:CIB
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arc: W3_H06W0003 E3_H06W0003
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R1C47:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C48:CIB
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arc: JD7 E1_H02W0001
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R1C49:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0203 E3_H06W0203
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.tile CIB_R1C50:CIB
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arc: W1_H02W0001 E3_H06W0003
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C51:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C52:CIB
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arc: W3_H06W0003 JQ0
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arc: W3_H06W0303 E1_H01W0100
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.tile CIB_R1C53:CIB
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arc: H01W0100 JQ0
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C54:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C55:CIB
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arc: W3_H06W0203 E1_H01W0000
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.tile CIB_R1C56:CIB
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arc: H01W0000 JQ0
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arc: W3_H06W0003 E1_H01W0000
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.tile CIB_R1C57:CIB
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arc: H01W0000 JQ0
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.tile CIB_R1C59:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R20C1:CIB_LR
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arc: E1_H01E0001 JQ5
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arc: E1_H02E0701 S1_V02N0701
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arc: E3_H06E0303 JF5
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.tile CIB_R20C89:CIB_LR
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arc: H01W0000 JQ5
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arc: W3_H06W0303 JF5
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.tile CIB_R22C13:CIB_DSP
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arc: E3_H06E0103 W3_H06E0003
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.tile CIB_R22C19:CIB_DSP
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arc: E3_H06E0103 W3_H06E0103
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.tile CIB_R22C1:CIB_LR_S
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arc: E3_H06E0303 JF5
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arc: N1_V02N0701 JQ5
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.tile CIB_R22C25:CIB_DSP
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arc: E3_H06E0203 W3_H06E0103
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.tile CIB_R22C31:CIB_DSP
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arc: E3_H06E0203 W3_H06E0203
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arc: S1_V02S0001 H02W0001
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.tile CIB_R22C32:CIB_DSP
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arc: W1_H02W0001 S3_V06N0003
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.tile CIB_R22C33:CIB_DSP
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arc: N1_V02N0201 S1_V02N0201
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arc: S1_V02S0401 E1_H02W0401
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.tile CIB_R22C34:CIB_DSP
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arc: N1_V02N0001 E1_H01W0000
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arc: N1_V02N0201 S1_V02N0201
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arc: N1_V02N0701 S1_V02N0701
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arc: S1_V02S0101 N1_V01S0100
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arc: S1_V02S0301 N1_V02S0301
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arc: S1_V02S0601 E3_H06W0303
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.tile CIB_R22C35:CIB_DSP
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arc: E1_H02E0001 S3_V06N0003
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arc: H01W0000 E3_H06W0103
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arc: N1_V02N0001 S3_V06N0003
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arc: N1_V02N0201 N1_V01S0000
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arc: N1_V02N0301 S3_V06N0003
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arc: S1_V02S0301 N1_V02S0201
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arc: W1_H02W0401 V06S0203
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.tile CIB_R22C36:CIB_DSP
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arc: N1_V02N0001 H02E0001
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arc: N1_V02N0201 S1_V02N0201
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arc: N1_V02N0301 S1_V02N0301
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.tile CIB_R22C37:CIB_DSP
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arc: E1_H01E0101 W3_H06E0203
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arc: E1_H02E0301 S1_V02N0301
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arc: N1_V02N0101 S1_V02N0001
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arc: N1_V02N0201 S1_V02N0201
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arc: N1_V02N0401 V01N0001
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arc: N1_V02N0501 H02W0501
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arc: N1_V02N0601 S1_V02N0601
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arc: N1_V02N0701 S1_V02N0601
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arc: S1_V02S0701 S3_V06N0203
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.tile CIB_R22C38:CIB_DSP
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arc: N1_V02N0101 S1_V02N0101
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arc: N1_V02N0201 S1_V02N0201
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arc: N1_V02N0301 H02E0301
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arc: N1_V02N0401 S3_V06N0203
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arc: N1_V02N0501 H01E0101
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arc: N1_V02N0601 S3_V06N0303
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arc: W1_H02W0501 S3_V06N0303
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.tile CIB_R22C39:CIB_DSP
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arc: N1_V02N0001 V01N0001
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arc: N1_V02N0201 S1_V02N0701
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arc: N1_V02N0401 S1_V02N0401
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arc: N1_V02N0601 V01N0001
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arc: S1_V02S0101 V01N0101
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arc: S1_V02S0701 N1_V02S0701
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.tile CIB_R22C40:CIB_DSP
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arc: N1_V02N0501 S1_V02N0501
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R22C41:CIB_DSP
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R22C46:CIB_DSP
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R22C47:CIB_DSP
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R22C52:CIB_DSP
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arc: W3_H06W0303 E3_H06W0203
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.tile CIB_R22C53:CIB_DSP
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R22C58:CIB_DSP
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arc: W3_H06W0203 E3_H06W0103
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.tile CIB_R22C59:CIB_DSP
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R22C64:CIB_DSP
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arc: W3_H06W0103 E3_H06W0103
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.tile CIB_R22C65:CIB_DSP
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R22C70:CIB_DSP
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arc: W3_H06W0103 E3_H06W0003
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.tile CIB_R22C71:CIB_DSP
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R22C76:CIB_DSP
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arc: W3_H06W0003 E3_H06W0303
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.tile CIB_R22C77:CIB_DSP
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R22C7:CIB_DSP
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arc: E3_H06E0003 W3_H06E0303
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.tile CIB_R22C82:CIB_DSP
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arc: W3_H06W0303 E3_H06W0303
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.tile CIB_R22C83:CIB_DSP
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arc: W3_H06W0003 E3_H06W0303
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.tile CIB_R22C88:CIB_DSP
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arc: W3_H06W0303 E1_H01W0100
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.tile CIB_R22C89:CIB_LR_S
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arc: H01W0100 JQ5
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arc: W3_H06W0303 JF5
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.tile CIB_R23C1:CIB_LR
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arc: E1_H01E0101 JQ5
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arc: E3_H06E0003 S3_V06N0003
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arc: E3_H06E0303 JF5
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arc: S1_V02S0701 E3_H06W0203
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.tile CIB_R23C89:CIB_LR
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arc: JA3 W1_H02E0501
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arc: V01S0100 S3_V06N0303
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R24C1:CIB_LR
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arc: S1_V02S0701 E3_H06W0203
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.tile CIB_R24C89:CIB_LR
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arc: S1_V02S0401 W1_H02E0401
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arc: S1_V02S0701 H06E0203
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arc: W3_H06W0103 N1_V01S0100
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.tile CIB_R25C1:CIB_LR
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arc: E3_H06E0103 V01N0101
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arc: E3_H06E0303 S3_V06N0303
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arc: JA3 N1_V02S0701
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arc: N3_V06N0303 JF5
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arc: S3_V06S0103 H06W0103
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enum: CIB.JB3MUX 0
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.tile CIB_R25C89:CIB_LR
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arc: JA3 V02S0701
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R26C1:CIB_LR
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arc: E1_H02E0501 S1_V02N0501
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arc: E3_H06E0303 JF5
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arc: N1_V01N0101 JQ5
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arc: S1_V02S0701 N1_V02S0701
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.tile CIB_R26C89:CIB_LR
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arc: H01W0100 JQ5
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arc: JA0 H01E0001
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arc: S1_V02S0501 N1_V02S0401
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arc: S1_V02S0701 W1_H02E0701
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arc: W3_H06W0303 S3_V06N0303
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enum: CIB.JB0MUX 0
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.tile CIB_R28C1:CIB_LR
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arc: E3_H06E0103 V01N0101
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arc: E3_H06E0303 S3_V06N0303
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arc: JA0 N1_V02S0701
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arc: N1_V02N0501 JQ5
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enum: CIB.JB0MUX 0
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.tile CIB_R28C89:CIB_LR
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arc: JA0 N1_V02S0701
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arc: JA3 N1_V02S0501
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arc: W3_H06W0303 S3_V06N0303
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enum: CIB.JB3MUX 0
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enum: CIB.JB0MUX 0
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.tile CIB_R29C1:CIB_LR
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arc: E3_H06E0303 JQ5
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arc: N1_V01N0101 JF5
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arc: N3_V06N0003 S3_V06N0303
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.tile CIB_R29C89:CIB_LR
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arc: N3_V06N0303 JF5
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arc: W3_H06W0303 JQ5
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.tile CIB_R30C1:CIB_LR
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arc: S1_V02S0501 E3_H06W0303
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arc: S1_V02S0701 E1_H02W0701
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.tile CIB_R31C1:CIB_LR
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arc: E3_H06E0303 S3_V06N0303
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arc: JA3 V02S0501
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arc: N3_V06N0303 JF5
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arc: S1_V02S0701 E1_H02W0701
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arc: S3_V06S0203 N3_V06S0103
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enum: CIB.JB3MUX 0
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.tile CIB_R31C89:CIB_LR
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arc: JA3 W1_H02E0701
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R32C1:CIB_LR
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arc: JA0 N1_V02S0701
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arc: JA3 V02S0701
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enum: CIB.JB3MUX 0
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enum: CIB.JB0MUX 0
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.tile CIB_R32C89:CIB_LR
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arc: H01W0000 JQ5
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arc: N3_V06N0303 JF5
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arc: W3_H06W0303 V06N0303
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.tile CIB_R34C1:CIB_LR_S
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arc: E3_H06E0303 JF5
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arc: N3_V06N0303 JQ5
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.tile CIB_R34C32:CIB_EBR
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arc: N3_V06N0303 S3_V06N0203
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.tile CIB_R34C33:CIB_EBR
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arc: N3_V06N0003 S3_V06N0303
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.tile CIB_R34C34:CIB_EBR
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arc: N3_V06N0303 S3_V06N0303
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.tile CIB_R34C35:CIB_EBR
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arc: N3_V06N0003 E3_H06W0003
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arc: N3_V06N0303 S3_V06N0303
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.tile CIB_R34C36:CIB_EBR
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arc: N3_V06N0303 S3_V06N0303
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.tile CIB_R34C38:CIB_EBR
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arc: N3_V06N0103 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0103
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.tile CIB_R34C41:CIB_EBR
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arc: W3_H06W0003 E3_H06W0303
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.tile CIB_R34C47:CIB_EBR
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arc: W3_H06W0303 E3_H06W0203
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.tile CIB_R34C53:CIB_EBR
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|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile CIB_R34C59:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R34C65:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R34C71:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile CIB_R34C77:CIB_EBR
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile CIB_R34C7:CIB_EBR
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile CIB_R34C83:CIB_EBR
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile CIB_R34C89:CIB_LR_S
|
|
arc: N3_V06N0303 JF5
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R35C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R35C89:CIB_LR
|
|
arc: N3_V06N0303 JF5
|
|
|
|
.tile CIB_R37C1:CIB_LR
|
|
arc: E3_H06E0303 JF5
|
|
arc: N3_V06N0303 JQ5
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile CIB_R37C89:CIB_LR
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R43C1:CIB_LR
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R46C32:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R46C33:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C34:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R46C35:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R46C36:CIB_DSP
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile CIB_R46C38:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R49C1:CIB_LR
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R55C1:CIB_LR
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R58C32:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C33:CIB_EBR
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile CIB_R58C34:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C35:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile CIB_R58C36:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R58C38:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R5C1:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R5C89:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R61C1:CIB_LR
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R67C1:CIB_LR
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile CIB_R70C11:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C13:CIB
|
|
arc: JA0 N1_V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C14:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C15:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C16:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C17:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C18:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C1:CIB_LR_S
|
|
arc: E1_H02E0501 V06S0303
|
|
|
|
.tile CIB_R70C20:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C21:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C22:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C23:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C24:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C26:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C27:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C28:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C29:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C30:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C32:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C33:CIB
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C34:CIB
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C35:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile CIB_R70C36:CIB
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C38:CIB
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile CIB_R70C3:CIB_PLL3
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C42:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C43:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C45:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C5:CIB
|
|
arc: JA4 W1_H02E0501
|
|
arc: JB4 N1_V02S0501
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile MIB_R0C27:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C29:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C30:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C31:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C32:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C33:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C34:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C36:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C37:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C38:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C44:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C45:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C47:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C48:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C49:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C50:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C51:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C52:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C53:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C54:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C56:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C57:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C59:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C50:EBR_SPINE_UR0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R17C90:PICR0_DQS2
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R18C90:PICR1_DQS3
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R19C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C27:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C29:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C30:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C31:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C32:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C33:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C34:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C36:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C37:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C38:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C44:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C45:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C47:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C48:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C49:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C50:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C51:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C52:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C53:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C54:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C56:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C57:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C59:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R20C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R21C90:PICR1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R22C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R22C90:MIB_CIB_LR_A
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R24C90:PICR1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R25C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R25C90:PICR2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C90:PICR0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C0:PICL1_DQS0
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R27C90:PICR1_DQS0
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R28C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C0:PICL0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R29C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C0:PICL1_DQS3
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R31C0:PICL2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R33C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R34C90:MIB_CIB_LR_A
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R36C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R36C90:PICR1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R37C0:PICL2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R37C90:PICR2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R71C11:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C13:PICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C14:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C15:PICB0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C16:PICB1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile MIB_R71C7:EFB3_PICB1
|
|
enum: CCLK.MODE USRMCLK
|
|
|
|
.tile R11C33:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R13C30:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C31:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C32:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C33:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C34:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C35:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C36:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R13C37:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R13C38:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C39:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R13C40:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C42:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R14C37:PLC2
|
|
arc: S3_V06S0303 N1_V01S0100
|
|
|
|
.tile R14C65:PLC2
|
|
word: SLICED.K0.INIT 1111111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R15C35:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R15C36:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
|
|
.tile R15C37:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R17C33:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R17C36:PLC2
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
|
|
.tile R17C38:PLC2
|
|
arc: S3_V06S0303 H06W0303
|
|
|
|
.tile R17C41:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R17C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R17C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R17C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R17C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R17C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R17C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R17C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R18C34:PLC2
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R18C36:PLC2
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
|
|
.tile R19C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R19C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R19C30:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R19C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile R19C32:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
|
|
.tile R19C33:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R19C34:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: C0 N1_V01S0100
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R19C35:PLC2
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
|
|
.tile R19C36:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: H00R0000 V02S0401
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02E0501
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R19C37:PLC2
|
|
arc: H00R0000 H02E0401
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: A3 V02N0501
|
|
arc: C0 V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D3 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 1010101000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R19C38:PLC2
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R19C39:PLC2
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
|
|
.tile R19C40:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
|
|
.tile R19C41:PLC2
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
|
|
.tile R19C42:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R19C47:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R19C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R19C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R19C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R19C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R19C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R20C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R20C14:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C15:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R20C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C20:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R20C21:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R20C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C26:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R20C27:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R20C2:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
|
|
.tile R20C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R20C32:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R20C33:PLC2
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
|
|
.tile R20C34:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: B1 V02N0301
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 S1_V02N0001
|
|
arc: F1 F1_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0301 Q1
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R20C35:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: B0 S1_V02N0301
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M1 W1_H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0201 Q0
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R20C36:PLC2
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0401 S3_V06N0203
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0100 H02E0101
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: B7 N1_V01S0000
|
|
arc: C1 E1_H01W0000
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 H01E0101
|
|
arc: D5 H01W0000
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 Q7
|
|
arc: LSR0 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S3_V06S0003 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1111000011110000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111111100000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1100110011001100
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R20C37:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00T0000 H02W0001
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A0 S1_V02N0501
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0000
|
|
arc: B3 V02S0101
|
|
arc: B4 H02E0301
|
|
arc: B5 F3
|
|
arc: C3 H00L0000
|
|
arc: C4 V02S0201
|
|
arc: C5 F4
|
|
arc: CE0 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 W1_H02E0001
|
|
arc: D5 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S3_V06S0303 F5
|
|
word: SLICEC.K0.INIT 0000001100010001
|
|
word: SLICEB.K1.INIT 1111010111011101
|
|
word: SLICEC.K1.INIT 0000110000000000
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R20C38:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: S1_V02S0001 S3_V06N0003
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: C0 S1_V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0601 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: LSR0 H02W0501
|
|
arc: M1 H00R0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R20C39:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 V01N0101
|
|
arc: A4 V00T0000
|
|
arc: A7 Q7
|
|
arc: B1 V01N0001
|
|
arc: B4 H02E0301
|
|
arc: C1 F4
|
|
arc: C4 H02E0601
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: D1 S1_V02N0001
|
|
arc: D4 V02N0601
|
|
arc: D7 S1_V02N0601
|
|
arc: E1_H01E0101 F0
|
|
arc: F0 F5A_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 E1_H02W0501
|
|
arc: M0 V00B0100
|
|
arc: M2 V00B0000
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q7
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 0000000010101010
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 0111111100000000
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R20C3:PLC2
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
|
|
.tile R20C40:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: S3_V06S0303 H01E0101
|
|
|
|
.tile R20C41:PLC2
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
|
|
.tile R20C46:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C47:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C52:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C58:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C64:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R20C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C70:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R20C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R20C76:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R20C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R20C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R20C82:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R20C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R20C88:PLC2
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R20C8:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R20C9:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R21C31:PLC2
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
|
|
.tile R21C32:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
|
|
.tile R21C33:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00R0000 H02E0401
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 S1_V02N0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C34:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: A0 H02E0701
|
|
arc: B2 H02W0301
|
|
arc: C0 H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: D2 N1_V02S0201
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0001 Q0
|
|
arc: V01S0100 Q2
|
|
word: SLICEA.K0.INIT 1111101000001010
|
|
word: SLICEB.K0.INIT 1100110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
|
|
.tile R21C35:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00R0000 H02E0401
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A4 V02S0301
|
|
arc: B1 N1_V02S0101
|
|
arc: B4 N1_V01S0000
|
|
arc: C4 Q4
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V02N0001
|
|
arc: D4 H00R0100
|
|
arc: E1_H01E0001 F4
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00R0100 Q7
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M4 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0101 Q1
|
|
word: SLICEC.K0.INIT 0000000100100011
|
|
word: SLICEA.K1.INIT 1100110000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
|
|
.tile R21C36:PLC2
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: H00R0100 V02S0701
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: W1_H02W0701 V06N0203
|
|
arc: A5 F7
|
|
arc: A7 E1_H01W0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B7 V01S0000
|
|
arc: C0 S1_V02N0601
|
|
arc: C2 H02W0401
|
|
arc: C5 H01E0001
|
|
arc: C7 V02S0001
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 V02N0001
|
|
arc: D5 V02S0401
|
|
arc: D7 H02E0001
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 H02E0501
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 Q7
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICED.K1.INIT 1100111110101111
|
|
word: SLICEC.K1.INIT 0000000011111101
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R21C37:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: A5 S1_V02N0101
|
|
arc: B5 V00B0100
|
|
arc: B7 S1_V02N0501
|
|
arc: C0 S1_V02N0601
|
|
arc: C2 V02N0401
|
|
arc: C5 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 V00T0100
|
|
arc: D5 E1_H01W0100
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: LSR0 W1_H02E0501
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M5 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0303 F5
|
|
arc: V00B0100 Q7
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K1.INIT 1100110000000000
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 1011000010111011
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R21C38:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 S1_V02N0501
|
|
arc: A2 H01E0001
|
|
arc: A5 Q5
|
|
arc: A6 V02N0101
|
|
arc: B2 V02N0301
|
|
arc: B6 V00B0000
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 N1_V01S0100
|
|
arc: C6 V02S0001
|
|
arc: CE0 V02N0201
|
|
arc: CE2 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 H02E0001
|
|
arc: D5 W1_H02E0201
|
|
arc: D6 V02S0601
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q4
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M2 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 F2
|
|
arc: S3_V06S0303 Q5
|
|
arc: V00B0100 F5
|
|
word: SLICEC.K1.INIT 0101010100000000
|
|
word: SLICEB.K0.INIT 1000010010100101
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 1010000010100000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R21C39:PLC2
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00T0100 H02W0301
|
|
arc: A1 F7
|
|
arc: A3 S1_V02N0701
|
|
arc: A7 H02E0701
|
|
arc: B1 F3
|
|
arc: B3 W1_H02E0301
|
|
arc: B7 V00T0000
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 S1_V02N0401
|
|
arc: C7 S1_V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D3 H02E0001
|
|
arc: D7 S1_V02N0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR0 H02W0501
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V01N0101 F7
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0201 F0
|
|
arc: S3_V06S0003 F0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 0111111100000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R21C40:PLC2
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R23C11:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R23C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R23C14:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R23C15:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R23C17:PLC2
|
|
arc: E3_H06E0003 F0
|
|
arc: F0 F0_SLICE
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
|
|
.tile R23C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R23C20:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R23C21:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C23:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R23C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R23C26:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R23C27:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R23C29:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R23C2:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R23C31:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: H00R0100 V02N0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: C0 H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R23C32:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: S1_V02S0001 E1_H02W0001
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
arc: B0 E1_H01W0100
|
|
arc: C0 H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1111110000110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C33:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02S0401
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0501 E3_H06W0303
|
|
arc: V00B0000 H02W0601
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: A2 F7
|
|
arc: A3 H01E0001
|
|
arc: A4 V02N0101
|
|
arc: A7 N1_V01N0101
|
|
arc: B0 H01W0100
|
|
arc: B2 H01W0100
|
|
arc: B3 V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B6 F3
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 H02W0601
|
|
arc: C2 V02N0601
|
|
arc: C3 E1_H02W0401
|
|
arc: C4 E1_H02W0401
|
|
arc: C6 V01N0101
|
|
arc: C7 V02N0001
|
|
arc: CE0 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D2 V01S0100
|
|
arc: D3 N1_V02S0001
|
|
arc: D4 H02W0001
|
|
arc: D6 V02N0601
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M4 V00T0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0203 Q4
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F4
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEB.K1.INIT 1110000000100000
|
|
word: SLICED.K1.INIT 1010110000000000
|
|
word: SLICEC.K0.INIT 0000110100001000
|
|
word: SLICEB.K0.INIT 1100110010001100
|
|
word: SLICED.K0.INIT 0000000000000011
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C34:PLC2
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
arc: W1_H02W0601 V02S0601
|
|
arc: A6 V02N0101
|
|
arc: A7 V02N0101
|
|
arc: B6 V00T0000
|
|
arc: C4 V02N0001
|
|
arc: C5 V02N0001
|
|
arc: C6 V02N0001
|
|
arc: C7 V02N0001
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V02N0401
|
|
arc: D6 H02W0001
|
|
arc: D7 V02N0601
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: V01S0000 F3
|
|
word: SLICEA.K0.INIT 1111111100000000
|
|
word: SLICEA.K1.INIT 1111111100000000
|
|
word: SLICEB.K0.INIT 1111111100000000
|
|
word: SLICEB.K1.INIT 1111111100000000
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
word: SLICED.K0.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 1010000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R23C35:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 W3_H06E0003
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A3 S1_V02N0701
|
|
arc: A5 V02N0301
|
|
arc: B1 Q1
|
|
arc: B3 V02S0301
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 E1_H02W0101
|
|
arc: C0 E1_H01W0000
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 V00T0000
|
|
arc: CE0 H00R0000
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0001
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 S1_V02N0401
|
|
arc: D5 H02W0001
|
|
arc: D6 E1_H01W0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F3
|
|
arc: LSR0 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0601 F4
|
|
word: SLICEA.K1.INIT 0011001100000000
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICEC.K0.INIT 0011000000110011
|
|
word: SLICEC.K1.INIT 0010001100000000
|
|
word: SLICEB.K1.INIT 0000000100001011
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C36:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0601 H06W0303
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0001 V06S0003
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A3 H02W0701
|
|
arc: A4 V02N0101
|
|
arc: A7 H00R0000
|
|
arc: B0 H02E0301
|
|
arc: B2 H02E0101
|
|
arc: B5 H01E0101
|
|
arc: B6 V00B0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0601 F4
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 F7
|
|
arc: S1_V02S0501 F7
|
|
arc: S1_V02S0601 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F4
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R23C37:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 N1_V02S0701
|
|
arc: A0 V01N0101
|
|
arc: A3 V00B0000
|
|
arc: A6 V02N0301
|
|
arc: B1 V01N0001
|
|
arc: B2 E1_H01W0100
|
|
arc: B4 H00L0000
|
|
arc: B5 H00R0000
|
|
arc: B7 V00T0000
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0601 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F7
|
|
arc: LSR1 W1_H02E0501
|
|
arc: M2 H02W0601
|
|
arc: M3 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 F2
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0401 F6
|
|
arc: V01S0000 F7
|
|
arc: V01S0100 Q3
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEA.K0.INIT 1010101010100000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEC.K0.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C38:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0601 N3_V06S0303
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: A1 W1_H02E0701
|
|
arc: A4 H02W0501
|
|
arc: A5 H02E0501
|
|
arc: A6 H00L0000
|
|
arc: B0 V01N0001
|
|
arc: B5 H02W0101
|
|
arc: B6 V02N0501
|
|
arc: C5 H02E0401
|
|
arc: C6 N1_V02S0201
|
|
arc: C7 H01E0001
|
|
arc: CE0 W1_H02E0101
|
|
arc: CE1 W1_H02E0101
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02E0001
|
|
arc: D5 H02E0201
|
|
arc: D6 N1_V02S0601
|
|
arc: D7 N1_V02S0601
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0701 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M0 V00B0000
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0401 F6
|
|
arc: S1_V02S0701 F5
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 F0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEC.K1.INIT 1001000000001001
|
|
word: SLICED.K1.INIT 1111000000001111
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 1101110100001101
|
|
word: SLICEC.K0.INIT 1010101000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R23C39:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 H02E0101
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A4 F5
|
|
arc: A7 H00L0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V00T0000
|
|
arc: B4 V02S0701
|
|
arc: B5 V02N0501
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 W1_H02E0601
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 V02N0001
|
|
arc: C7 F4
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 N1_V02S0001
|
|
arc: D5 V01N0001
|
|
arc: D7 S1_V02N0401
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F5
|
|
arc: H01W0100 F7
|
|
arc: LSR0 E1_H02W0501
|
|
arc: M0 H01E0001
|
|
arc: M1 H00R0100
|
|
arc: M2 V00T0100
|
|
arc: M4 V00B0100
|
|
arc: M6 H02E0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0601 Q6
|
|
arc: S1_V02S0301 F1
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 F5
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 F5
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0501 F5
|
|
arc: W3_H06W0303 F5
|
|
word: SLICEC.K0.INIT 0010101000101010
|
|
word: SLICED.K1.INIT 0000100000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0010000000000010
|
|
word: SLICEA.K1.INIT 1000001000000000
|
|
word: SLICEC.K1.INIT 0000001100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C40:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 V02N0701
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0501
|
|
arc: A2 H02E0701
|
|
arc: A3 H02E0501
|
|
arc: A7 H00L0000
|
|
arc: B1 V02N0101
|
|
arc: B5 H02W0101
|
|
arc: B7 H02E0301
|
|
arc: C1 N1_V01N0001
|
|
arc: C7 V01N0101
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0201
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D5 V00B0000
|
|
arc: D7 H02E0201
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 H02W0501
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M4 V00T0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 F7
|
|
arc: S1_V02S0101 F1
|
|
arc: S1_V02S0501 F5
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 F7
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEA.K0.INIT 1010101011111111
|
|
word: SLICEA.K1.INIT 1000111110101111
|
|
word: SLICED.K1.INIT 1111010011110110
|
|
word: SLICEB.K0.INIT 1010101011111111
|
|
word: SLICEB.K1.INIT 1010101011111111
|
|
word: SLICEC.K1.INIT 0011001111001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R23C41:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R23C42:PLC2
|
|
arc: A0 V02N0701
|
|
arc: A5 V02N0101
|
|
arc: C0 W1_H02E0401
|
|
arc: C5 E1_H01E0101
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0101 F0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0100 F5
|
|
arc: LSR1 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 0000000010100000
|
|
word: SLICEC.K1.INIT 1111000010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C47:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R23C48:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R23C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R23C54:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R23C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R23C5:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R23C60:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R23C65:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R23C66:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R23C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R23C72:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R23C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R23C78:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
|
|
.tile R23C79:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
|
|
.tile R23C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R23C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R23C85:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
|
|
.tile R23C87:PLC2
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
|
|
.tile R23C8:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: H01W0000 E3_H06W0103
|
|
|
|
.tile R24C13:PLC2
|
|
arc: S3_V06S0203 H06W0203
|
|
|
|
.tile R24C14:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R24C15:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R24C16:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R24C20:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R24C21:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R24C22:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R24C26:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R24C27:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R24C28:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R24C30:PLC2
|
|
arc: E1_H01E0101 E3_H06W0203
|
|
|
|
.tile R24C31:PLC2
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: B0 V02N0101
|
|
arc: C0 V02S0601
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C32:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0401 E3_H06W0203
|
|
arc: H00L0000 H02E0001
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: V00B0100 H02W0501
|
|
arc: B0 V02N0301
|
|
arc: C0 H00L0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M5 H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: W3_H06W0303 Q5
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C33:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A1 H00L0000
|
|
arc: A5 S1_V02N0101
|
|
arc: B1 H02W0301
|
|
arc: B3 H02W0301
|
|
arc: B5 H01E0101
|
|
arc: C0 V02N0401
|
|
arc: C1 V02N0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C5 S1_V02N0001
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 V02N0201
|
|
arc: D5 W1_H02E0001
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H01E0101 F0
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0100 F3
|
|
arc: H01W0000 F0
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M0 V00T0100
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0201 F0
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0301 F3
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 F0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEB.K1.INIT 1100000011000000
|
|
word: SLICEC.K1.INIT 0101010000000100
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
word: SLICEA.K1.INIT 0000110000001000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C34:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0101 E3_H06W0103
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S1_V02S0201 E3_H06W0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 H01E0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 F5
|
|
arc: A2 F7
|
|
arc: A3 S1_V02N0501
|
|
arc: A4 V02N0301
|
|
arc: A5 H02W0701
|
|
arc: A6 E1_H01W0000
|
|
arc: A7 N1_V02S0301
|
|
arc: B0 V02S0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 N1_V02S0101
|
|
arc: B3 E1_H02W0101
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 H02W0101
|
|
arc: B6 V00T0000
|
|
arc: B7 E1_H02W0301
|
|
arc: C0 H02E0601
|
|
arc: C1 H00L0100
|
|
arc: C2 F4
|
|
arc: C3 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: C5 V02N0001
|
|
arc: C6 E1_H02W0601
|
|
arc: C7 S1_V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 V02S0001
|
|
arc: D2 S1_V02N0001
|
|
arc: D3 S1_V02N0201
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 E1_H01W0100
|
|
arc: D6 S1_V02N0401
|
|
arc: D7 H00R0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 F3
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0301 F1
|
|
arc: V00T0000 F2
|
|
arc: V01S0100 F6
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEC.K1.INIT 0000111101110111
|
|
word: SLICEB.K1.INIT 1110010011111111
|
|
word: SLICEC.K0.INIT 0000000001000111
|
|
word: SLICED.K1.INIT 0011001100100011
|
|
word: SLICEA.K0.INIT 1111111101110101
|
|
word: SLICEB.K0.INIT 0000100000001010
|
|
word: SLICED.K0.INIT 0000110100001100
|
|
word: SLICEA.K1.INIT 0000000000110000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
|
|
.tile R24C35:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0701 H06W0203
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 E1_H02W0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A1 S1_V02N0501
|
|
arc: A3 H00L0100
|
|
arc: A4 V02S0101
|
|
arc: A6 E1_H02W0701
|
|
arc: B1 V02N0101
|
|
arc: B2 H02E0101
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 N1_V01S0000
|
|
arc: B6 E1_H02W0101
|
|
arc: B7 F3
|
|
arc: C0 H02W0401
|
|
arc: C1 V02S0401
|
|
arc: C2 H02E0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 V00T0000
|
|
arc: C6 V01N0101
|
|
arc: C7 F4
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 V02N0001
|
|
arc: D2 H02E0001
|
|
arc: D3 V02S0201
|
|
arc: D4 E1_H02W0201
|
|
arc: D6 V02S0601
|
|
arc: D7 V00B0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F1
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V00T0000 Q0
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0401 F6
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000110000000000
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
word: SLICED.K0.INIT 1010000010000000
|
|
word: SLICEA.K1.INIT 0000000101000101
|
|
word: SLICEB.K1.INIT 1111001101010001
|
|
word: SLICEC.K0.INIT 1001000000001001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C36:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A3 H02E0701
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 V00T0100
|
|
arc: A7 E1_H02W0701
|
|
arc: B3 Q3
|
|
arc: B5 V02S0701
|
|
arc: B6 V02S0501
|
|
arc: B7 S1_V02N0701
|
|
arc: C0 V02S0601
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 E1_H02W0601
|
|
arc: C5 E1_H02W0401
|
|
arc: C6 V02N0201
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H02W0001
|
|
arc: D3 V02S0201
|
|
arc: D5 V02S0601
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F7
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0601 F6
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F7
|
|
arc: H01W0100 Q3
|
|
arc: LSR1 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0101 F7
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N3_V06N0203 F7
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0501 F7
|
|
arc: S3_V06S0203 F7
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0701 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1101110100001101
|
|
word: SLICED.K1.INIT 0100010001000100
|
|
word: SLICED.K0.INIT 1001000000001001
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R24C37:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0601 E1_H01W0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V02S0101
|
|
arc: B0 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B4 H01E0101
|
|
arc: B5 V02S0701
|
|
arc: B7 N1_V02S0701
|
|
arc: C1 V02S0401
|
|
arc: C3 V02S0601
|
|
arc: C4 V02N0001
|
|
arc: C5 V00T0000
|
|
arc: C7 H02E0401
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V00B0100
|
|
arc: D2 V02S0001
|
|
arc: D3 V02S0201
|
|
arc: D4 E1_H02W0001
|
|
arc: D5 S1_V02N0401
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0401 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 F4
|
|
arc: LSR0 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0601 F4
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0701 F7
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0601 F4
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 1000001001000001
|
|
word: SLICEC.K1.INIT 1101000011011101
|
|
word: SLICED.K1.INIT 0000111100001100
|
|
word: SLICEB.K0.INIT 1010101000000000
|
|
word: SLICEC.K0.INIT 0000000011101100
|
|
word: SLICEA.K0.INIT 1100110000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R24C38:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0101 V02S0101
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: A1 H02E0701
|
|
arc: A3 V02S0501
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 E1_H01W0000
|
|
arc: A7 E1_H01W0000
|
|
arc: B1 E1_H02W0301
|
|
arc: B3 H02W0301
|
|
arc: C1 V02S0601
|
|
arc: C3 N1_V01S0100
|
|
arc: C5 V00T0000
|
|
arc: C7 V00T0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 W1_H02E0001
|
|
arc: D3 H02E0001
|
|
arc: D4 H00R0100
|
|
arc: D5 E1_H02W0201
|
|
arc: D7 E1_H02W0201
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F0
|
|
arc: E1_H02E0201 F0
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0701 F7
|
|
arc: E3_H06E0203 F7
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F2
|
|
arc: H01W0100 F7
|
|
arc: LSR1 V00B0100
|
|
arc: M0 W1_H02E0601
|
|
arc: M2 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0201 F0
|
|
arc: S1_V02S0501 F5
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0701 F7
|
|
word: SLICEC.K0.INIT 1010101000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1000001001000001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1000001001000001
|
|
word: SLICEC.K1.INIT 0000000001010000
|
|
word: SLICED.K1.INIT 1111111111111010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R24C39:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E3_H06E0103 W1_H02E0201
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: V00T0000 W1_H02E0201
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 V02S0701
|
|
arc: A1 F7
|
|
arc: A2 V02S0501
|
|
arc: A3 V02S0501
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 H02E0701
|
|
arc: A6 V02S0301
|
|
arc: A7 E1_H01W0000
|
|
arc: B1 N1_V02S0101
|
|
arc: B6 W1_H02E0101
|
|
arc: B7 V00B0000
|
|
arc: C0 S1_V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: C2 S1_V02N0401
|
|
arc: C3 S1_V02N0401
|
|
arc: C4 Q4
|
|
arc: C5 V00T0000
|
|
arc: C7 V02S0201
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 H01E0101
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V02N0601
|
|
arc: D6 H02E0001
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 E1_H02W0501
|
|
arc: M0 H01E0001
|
|
arc: M1 H00R0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q4
|
|
arc: S1_V02S0401 F6
|
|
arc: V00B0000 Q4
|
|
arc: V00B0100 F7
|
|
arc: V00T0100 F1
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F4
|
|
arc: W1_H02W0401 F4
|
|
word: SLICED.K1.INIT 1001100101110101
|
|
word: SLICED.K0.INIT 1000100000000000
|
|
word: SLICEA.K0.INIT 1010000011111111
|
|
word: SLICEA.K1.INIT 1101110111010101
|
|
word: SLICEB.K0.INIT 1010000011111111
|
|
word: SLICEB.K1.INIT 1010000011111111
|
|
word: SLICEC.K0.INIT 0101000000000000
|
|
word: SLICEC.K1.INIT 1111101000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R24C3:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R24C40:PLC2
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0101 H02E0101
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: A0 W1_H02E0501
|
|
arc: A4 V00T0000
|
|
arc: A6 H00L0000
|
|
arc: B0 S1_V02N0101
|
|
arc: B4 H00L0000
|
|
arc: B6 V00T0000
|
|
arc: C0 F4
|
|
arc: C4 S1_V02N0001
|
|
arc: C6 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D4 V00B0000
|
|
arc: D6 S1_V02N0601
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 H02W0501
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111111100101111
|
|
word: SLICEC.K0.INIT 1011101011011101
|
|
word: SLICED.K0.INIT 0101110101011111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R24C41:PLC2
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R24C42:PLC2
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0701 H06E0203
|
|
|
|
.tile R24C44:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W1_H02W0401 W3_H06E0203
|
|
|
|
.tile R24C45:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R24C47:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R24C50:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R24C51:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R24C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R24C56:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R24C57:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R24C62:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R24C63:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R24C68:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R24C69:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R24C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R24C74:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R24C75:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R24C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R24C7:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R24C80:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R24C81:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R24C83:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R24C86:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R24C87:PLC2
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
|
|
.tile R24C8:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
|
|
.tile R24C9:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R25C10:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R25C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R25C15:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R25C16:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R25C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R25C21:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C22:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R25C27:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C28:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R25C30:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
|
|
.tile R25C31:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 H02E0101
|
|
|
|
.tile R25C32:PLC2
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02W0001
|
|
arc: B0 H02E0101
|
|
arc: C0 N1_V02S0401
|
|
arc: CE0 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C33:PLC2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: V00B0000 H02E0401
|
|
arc: W1_H02W0001 E1_H02W0501
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A0 N1_V02S0501
|
|
arc: C0 W1_H02E0601
|
|
arc: CE0 V02S0201
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 E1_H02W0501
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M2 V00B0000
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
arc: V00T0000 Q0
|
|
arc: W3_H06W0203 Q4
|
|
word: SLICEA.K0.INIT 1111101001010000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C34:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 E1_H02W0601
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: S1_V02S0001 H06E0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: C2 V02N0601
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 S1_V02N0001
|
|
arc: F2 F2_SLICE
|
|
arc: LSR0 H02W0501
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0201 Q2
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R25C35:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 V01N0101
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: V00B0000 V02N0201
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 V02S0701
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 E1_H01W0000
|
|
arc: A7 H02W0501
|
|
arc: B3 H02E0301
|
|
arc: B4 V02S0701
|
|
arc: B5 H00L0000
|
|
arc: B7 E1_H02W0301
|
|
arc: C2 V02N0401
|
|
arc: C3 H00R0100
|
|
arc: C4 V02S0001
|
|
arc: C5 H02W0401
|
|
arc: C7 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 E1_H02W0001
|
|
arc: D3 H02E0201
|
|
arc: D4 H02E0201
|
|
arc: D5 E1_H01W0100
|
|
arc: D7 F2
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0203 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0100 F7
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 F3
|
|
arc: W1_H02W0401 F4
|
|
word: SLICEC.K1.INIT 0000000000000100
|
|
word: SLICEC.K0.INIT 0001000000000000
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEB.K0.INIT 0000000001010000
|
|
word: SLICED.K1.INIT 0000100010001010
|
|
word: SLICEB.K1.INIT 0000010000000111
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R25C36:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0501 E1_H02W0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A2 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 H02E0301
|
|
arc: B3 Q3
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q4
|
|
arc: W1_H02W0401 Q4
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C37:PLC2
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A4 V00B0000
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B2 H00L0000
|
|
arc: B3 Q3
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 1100110011000000
|
|
word: SLICEB.K1.INIT 1100110011000000
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEC.K1.INIT 1010101010100000
|
|
word: SLICED.K0.INIT 1010101010100000
|
|
word: SLICED.K1.INIT 1010101010100000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R25C38:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A4 W1_H02E0501
|
|
arc: A5 H02E0501
|
|
arc: A6 H02E0701
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 V00T0000
|
|
arc: B1 Q1
|
|
arc: B4 H02E0301
|
|
arc: B5 H02E0101
|
|
arc: B6 V00T0000
|
|
arc: B7 V02S0701
|
|
arc: C4 W1_H02E0401
|
|
arc: C5 H02E0601
|
|
arc: C6 H02E0401
|
|
arc: C7 W1_H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H02E0001
|
|
arc: D5 W1_H02E0001
|
|
arc: D6 H00L0100
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0601 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0701 F7
|
|
arc: V00T0000 Q0
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 0000000000000001
|
|
word: SLICEC.K0.INIT 0000000000000001
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 1100110011000000
|
|
word: SLICEA.K1.INIT 1100110011000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R25C39:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0601 N1_V02S0601
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A1 N1_V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V00B0000
|
|
arc: A7 H02E0701
|
|
arc: B0 H02W0301
|
|
arc: B1 V02N0101
|
|
arc: B4 F1
|
|
arc: B7 H01E0101
|
|
arc: C0 H02W0401
|
|
arc: C1 N1_V01S0100
|
|
arc: C2 E1_H01W0000
|
|
arc: C3 F6
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 V02N0201
|
|
arc: C6 V02N0001
|
|
arc: C7 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 F2
|
|
arc: D2 V00B0100
|
|
arc: D3 V00T0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V02S0601
|
|
arc: D6 V01N0001
|
|
arc: D7 W1_H02E0201
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0001 F2
|
|
arc: E1_H02E0501 F7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 F7
|
|
arc: LSR0 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0001 F3
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0601 F4
|
|
arc: N1_V02N0701 F7
|
|
arc: S1_V02S0001 F2
|
|
arc: S1_V02S0401 F6
|
|
arc: V00B0000 F4
|
|
arc: V00B0100 F7
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F6
|
|
arc: W1_H02W0001 F2
|
|
arc: W3_H06W0103 F2
|
|
word: SLICED.K0.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 0000101000000000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
word: SLICEA.K1.INIT 1100111101000101
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICEC.K0.INIT 0000000000000100
|
|
word: SLICEA.K0.INIT 0011000011110000
|
|
word: SLICEC.K1.INIT 0000101000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C3:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R25C40:PLC2
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 H02E0501
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A0 H00R0000
|
|
arc: A5 V02S0101
|
|
arc: A6 V02N0301
|
|
arc: A7 W1_H02E0501
|
|
arc: B0 W1_H02E0301
|
|
arc: B5 N1_V01S0000
|
|
arc: C0 H02E0601
|
|
arc: C5 V02S0201
|
|
arc: C6 H01E0001
|
|
arc: C7 S1_V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D2 Q2
|
|
arc: D5 H02E0201
|
|
arc: D7 H02E0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 F7
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00B0000 F6
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 F5
|
|
arc: W1_H02W0001 F0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICED.K0.INIT 1010111110101111
|
|
word: SLICEB.K0.INIT 0000000011111111
|
|
word: SLICEA.K0.INIT 1000001001000001
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1111010000001100
|
|
word: SLICED.K1.INIT 0000101010101010
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R25C41:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R25C42:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: B0 H02E0301
|
|
arc: C0 W1_H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 W1_H02E0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K0.INIT 1100000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R25C48:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R25C4:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R25C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R25C54:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R25C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R25C60:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R25C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R25C66:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R25C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R25C72:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R25C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R25C78:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R25C7:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R25C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R25C84:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R25C87:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
|
|
.tile R25C9:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R26C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R26C15:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R26C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R26C21:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R26C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R26C27:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R26C31:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
|
|
.tile R26C33:PLC2
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0401 E3_H06W0203
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: A1 V01N0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 H01W0100
|
|
arc: C0 N1_V01N0001
|
|
arc: C2 S1_V02N0601
|
|
arc: C3 S1_V02N0601
|
|
arc: C4 V02N0001
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 W1_H02E0001
|
|
arc: D4 S1_V02N0601
|
|
arc: E1_H01E0001 F0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M0 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
word: SLICEA.K0.INIT 1111001100000000
|
|
word: SLICEA.K1.INIT 1011101100000000
|
|
word: SLICEC.K0.INIT 1111000000000000
|
|
word: SLICEB.K0.INIT 1100000011000000
|
|
word: SLICEB.K1.INIT 1111000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R26C34:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 H02W0601
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00T0000 H02W0001
|
|
arc: A1 V01N0101
|
|
arc: A3 V01N0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 H02E0301
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 S1_V02N0601
|
|
arc: C4 V00T0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 E1_H02W0201
|
|
arc: D2 E1_H02W0201
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 H02E0001
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 V01S0100
|
|
arc: M2 V00T0000
|
|
arc: V01S0100 F4
|
|
word: SLICEC.K0.INIT 1100111111000000
|
|
word: SLICEA.K0.INIT 0011000000110011
|
|
word: SLICEA.K1.INIT 0010001000110011
|
|
word: SLICEB.K0.INIT 0011000000000000
|
|
word: SLICEB.K1.INIT 0010001000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R26C35:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0601 E1_H02W0601
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02N0501
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0501
|
|
arc: A6 E1_H01W0000
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 S1_V02N0101
|
|
arc: B6 V00T0000
|
|
arc: C2 F6
|
|
arc: C6 S1_V02N0001
|
|
arc: C7 V00T0000
|
|
arc: CE0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D2 V01S0100
|
|
arc: D6 H02W0201
|
|
arc: D7 E1_H01W0100
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F7
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V00T0000 Q0
|
|
arc: V01S0100 F7
|
|
arc: W1_H02W0001 Q0
|
|
word: SLICEA.K0.INIT 0000000000110011
|
|
word: SLICED.K0.INIT 1010100010101010
|
|
word: SLICED.K1.INIT 1111000000000000
|
|
word: SLICEB.K1.INIT 1010101010101010
|
|
word: SLICEB.K0.INIT 0010101000001010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C36:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 H02W0001
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: A3 V00T0000
|
|
arc: A7 N1_V01N0101
|
|
arc: B1 H02W0301
|
|
arc: B7 H01E0101
|
|
arc: C0 H02E0401
|
|
arc: C3 H00L0100
|
|
arc: C7 S1_V02N0001
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D1 V00B0100
|
|
arc: D3 H02E0001
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0003 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: M5 W1_H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0303 Q5
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0001 Q0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 Q1
|
|
arc: W1_H02W0701 F7
|
|
word: SLICED.K1.INIT 0000000101000101
|
|
word: SLICEA.K1.INIT 0011001100000000
|
|
word: SLICEB.K1.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 0000000011110000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R26C37:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A2 F7
|
|
arc: A7 E1_H02W0501
|
|
arc: B0 F3
|
|
arc: B1 V01N0001
|
|
arc: B2 H02W0301
|
|
arc: B4 F1
|
|
arc: B5 V02N0701
|
|
arc: B7 E1_H02W0101
|
|
arc: C0 V02N0401
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 H02W0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C6 H02W0401
|
|
arc: C7 E1_H01E0101
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 V00B0100
|
|
arc: D2 V00T0100
|
|
arc: D3 V00B0100
|
|
arc: D4 H02E0001
|
|
arc: D5 H00L0100
|
|
arc: D7 E1_H02W0001
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0101 F3
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 F1
|
|
arc: H01W0000 Q5
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0501 Q5
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q4
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q5
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0301 F3
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 Q4
|
|
word: SLICEA.K1.INIT 0000110000001111
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICED.K1.INIT 0111011101110000
|
|
word: SLICED.K0.INIT 0000111100001111
|
|
word: SLICEB.K0.INIT 0000001000000000
|
|
word: SLICEC.K0.INIT 0011001100000000
|
|
word: SLICEA.K0.INIT 0011000000110000
|
|
word: SLICEC.K1.INIT 0000000011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
|
|
.tile R26C38:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
arc: V00T0000 H02E0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: W1_H02W0501 N1_V02S0501
|
|
arc: A1 W1_H02E0701
|
|
arc: A3 F7
|
|
arc: A5 H02E0501
|
|
arc: A7 V02S0101
|
|
arc: B1 V02N0301
|
|
arc: B3 Q3
|
|
arc: B5 F3
|
|
arc: B7 V00T0000
|
|
arc: C1 H02E0401
|
|
arc: C2 E1_H02W0401
|
|
arc: C3 H00L0000
|
|
arc: C5 V01N0101
|
|
arc: C7 V02N0001
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 H02W0201
|
|
arc: D2 V02S0001
|
|
arc: D3 F0
|
|
arc: D5 V02S0401
|
|
arc: D7 H02W0201
|
|
arc: E1_H01E0001 F4
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: M0 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0101 F2
|
|
arc: N1_V02N0001 F2
|
|
arc: N3_V06N0003 Q3
|
|
arc: W1_H02W0101 Q3
|
|
arc: W1_H02W0601 F4
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 1010111100100011
|
|
word: SLICED.K1.INIT 1011000010111011
|
|
word: SLICEB.K1.INIT 1000001000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000010000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R26C39:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A1 F7
|
|
arc: A4 H02E0501
|
|
arc: A5 W1_H02E0701
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 W1_H02E0301
|
|
arc: B7 N1_V01S0000
|
|
arc: C0 F4
|
|
arc: C1 F4
|
|
arc: C2 F4
|
|
arc: C3 F4
|
|
arc: C4 V02S0001
|
|
arc: C5 H02E0601
|
|
arc: C7 V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 H02E0201
|
|
arc: D2 V00B0100
|
|
arc: D3 V00B0100
|
|
arc: D4 V01N0001
|
|
arc: D5 W1_H02E0201
|
|
arc: D7 V02S0401
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 F5
|
|
arc: V00B0100 F7
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F7
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEA.K0.INIT 1111001111110000
|
|
word: SLICEA.K1.INIT 1111000011110010
|
|
word: SLICEB.K0.INIT 1111001111110000
|
|
word: SLICEB.K1.INIT 1111001111110000
|
|
word: SLICEC.K1.INIT 0000000000000101
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
word: SLICED.K1.INIT 1100000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
|
|
.tile R26C3:PLC2
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R26C40:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: B1 H02W0301
|
|
arc: C0 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 H01E0101
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F0
|
|
arc: LSR0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0001 F0
|
|
arc: V00T0100 F1
|
|
arc: W3_H06W0003 F0
|
|
word: SLICEA.K0.INIT 0000111100000000
|
|
word: SLICEA.K1.INIT 1100110011111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C41:PLC2
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
|
|
.tile R26C45:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R26C46:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C47:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R26C51:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C52:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R26C57:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C58:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R26C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R26C63:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C64:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R26C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R26C69:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R26C70:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R26C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R26C75:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R26C76:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R26C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R26C81:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C82:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R26C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R26C87:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R26C88:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R26C9:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R27C31:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
|
|
.tile R27C33:PLC2
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: C1 V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D1 N1_V01S0000
|
|
arc: F1 F1_SLICE
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0101 Q1
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R27C34:PLC2
|
|
arc: H00R0000 E1_H02W0401
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: W1_H02W0401 E1_H02W0401
|
|
arc: C0 H02W0601
|
|
arc: C1 H02W0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR0 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V01N0101 Q0
|
|
arc: V01S0000 Q1
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R27C35:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00B0000 E1_H02W0601
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: A3 V02S0701
|
|
arc: A4 V02S0301
|
|
arc: B0 N1_V02S0301
|
|
arc: B2 H00L0000
|
|
arc: B5 E1_H02W0301
|
|
arc: B6 V00B0000
|
|
arc: B7 V00T0000
|
|
arc: E1_H01E0001 F7
|
|
arc: E1_H01E0101 F4
|
|
arc: E1_H02E0401 F6
|
|
arc: E1_H02E0701 F5
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: N1_V01N0001 F3
|
|
word: SLICEC.K0.INIT 1010101010100000
|
|
word: SLICEB.K1.INIT 1010101010100000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
word: SLICED.K1.INIT 1100110011000000
|
|
word: SLICEC.K1.INIT 1100110011000000
|
|
word: SLICED.K0.INIT 1100110011000000
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R27C36:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: H00R0000 H02E0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: C2 H02E0601
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 N1_V02S0001
|
|
arc: E1_H02E0701 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0000 Q5
|
|
arc: LSR1 H02E0501
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 1111000000000000
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
|
|
.tile R27C37:PLC2
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0301 N1_V01S0100
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 H02E0701
|
|
arc: A1 H02E0701
|
|
arc: B0 H00R0100
|
|
arc: B1 N1_V02S0301
|
|
arc: C0 V02S0601
|
|
arc: C1 N1_V01S0100
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 V02S0201
|
|
arc: E3_H06E0103 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00T0000
|
|
arc: M1 H02E0001
|
|
arc: M2 V00T0000
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 F1
|
|
word: SLICEA.K0.INIT 0000100000000000
|
|
word: SLICEA.K1.INIT 0000000000001001
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R27C38:PLC2
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: C0 V02N0401
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R27C39:PLC2
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: A5 V02S0101
|
|
arc: C5 V00B0100
|
|
arc: F5 F5_SLICE
|
|
arc: N1_V02N0701 F5
|
|
word: SLICEC.K1.INIT 1111101011111010
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
|
|
.tile R27C40:PLC2
|
|
arc: N1_V02N0201 H06E0103
|
|
|
|
.tile R28C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R28C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R28C31:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
|
|
.tile R28C32:PLC2
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R28C33:PLC2
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R28C34:PLC2
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 H02W0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: C0 H02W0601
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R28C35:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: V00T0100 V02N0501
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
arc: W1_H02W0201 E3_H06W0103
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0601 S3_V06N0303
|
|
arc: C0 V02N0401
|
|
arc: C1 S1_V02N0601
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 V01S0100
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q1
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
word: SLICEA.K1.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
|
|
.tile R28C36:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: C0 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: LSR0 H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
word: SLICEA.K0.INIT 1111000000000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R28C37:PLC2
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R28C38:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R28C41:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C47:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R28C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R28C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R28C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R28C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R29C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R29C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R29C25:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R29C2:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R29C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
|
|
.tile R29C34:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: N1_V02N0501 H06E0303
|
|
|
|
.tile R29C35:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R29C36:PLC2
|
|
arc: N1_V02N0001 H02E0001
|
|
|
|
.tile R29C38:PLC2
|
|
arc: N1_V02N0001 H06W0003
|
|
|
|
.tile R29C41:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R29C47:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R29C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C65:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R29C71:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R29C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R29C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R30C13:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R30C14:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R30C15:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R30C21:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R30C27:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R30C33:PLC2
|
|
arc: W3_H06W0103 N3_V06S0103
|
|
|
|
.tile R30C34:PLC2
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
|
|
.tile R30C35:PLC2
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
|
|
.tile R30C36:PLC2
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R30C3:PLC2
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R30C7:PLC2
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
|
|
.tile R30C8:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R31C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R31C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R31C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R31C31:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R31C34:PLC2
|
|
arc: N1_V02N0401 H06E0203
|
|
|
|
.tile R31C35:PLC2
|
|
arc: N1_V02N0001 E3_H06W0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R31C3:PLC2
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R31C41:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C47:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R31C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R31C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R31C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R31C77:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R31C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R31C87:PLC2
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
|
|
.tile R32C33:PLC2
|
|
arc: N3_V06N0103 E1_H01W0100
|
|
|
|
.tile R32C34:PLC2
|
|
arc: H01W0100 E3_H06W0303
|
|
|
|
.tile R32C35:PLC2
|
|
arc: N1_V02N0601 E3_H06W0303
|
|
|
|
.tile R32C40:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C41:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C46:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C47:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C52:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C53:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R32C58:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C64:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R32C70:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R32C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C76:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R32C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R32C82:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R32C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C88:PLC2
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
|
|
.tile R35C2:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R35C7:PLC2
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R36C13:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R37C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R37C19:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R37C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R37C31:PLC2
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile R37C35:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
|
|
.tile R37C41:PLC2
|
|
arc: N3_V06N0203 E3_H06W0203
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R37C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R37C53:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R37C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R37C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R37C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R37C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R37C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R37C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R3C33:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R3C35:PLC2
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
|
|
.tile R3C36:PLC2
|
|
arc: S3_V06S0003 N1_V02S0001
|
|
|
|
.tile R3C37:PLC2
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
|
|
.tile R3C42:PLC2
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
|
|
.tile R40C32:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R40C33:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R40C34:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R40C35:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R40C36:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R40C38:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
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.tile R41C2:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile R42C13:PLC2
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arc: S3_V06S0203 N3_V06S0203
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.tile R47C2:PLC2
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arc: S3_V06S0203 N3_V06S0103
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.tile R48C13:PLC2
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arc: S3_V06S0303 N3_V06S0203
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.tile R52C32:PLC2
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arc: N3_V06N0203 S3_V06N0203
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.tile R52C33:PLC2
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arc: N3_V06N0303 S3_V06N0203
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.tile R52C34:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R52C35:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R52C36:PLC2
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arc: N3_V06N0203 S3_V06N0103
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.tile R52C38:PLC2
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arc: N3_V06N0003 S3_V06N0303
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arc: N3_V06N0203 S3_V06N0103
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.tile R53C2:PLC2
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arc: S3_V06S0303 N3_V06S0203
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.tile R54C13:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R59C2:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R5C42:PLC2
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arc: N1_V02N0601 S1_V02N0601
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.tile R60C13:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R64C32:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R64C33:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R64C34:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R64C35:PLC2
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arc: N3_V06N0103 S3_V06N0103
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.tile R64C36:PLC2
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arc: N3_V06N0003 S3_V06N0003
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.tile R64C38:PLC2
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arc: N3_V06N0103 S3_V06N0003
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arc: N3_V06N0203 S3_V06N0103
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.tile R65C2:PLC2
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arc: S3_V06S0303 N3_V06S0303
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.tile R66C13:PLC2
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arc: S1_V02S0601 N3_V06S0303
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.tile R68C13:PLC2
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arc: S1_V02S0701 N1_V02S0601
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.tile R68C2:PLC2
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arc: E3_H06E0303 V06S0303
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.tile R68C5:PLC2
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arc: S1_V02S0501 H06E0303
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.tile R7C30:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R7C31:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R7C32:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R7C33:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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.tile R7C34:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R7C35:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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.tile R7C36:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile R7C37:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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arc: S3_V06S0303 N3_V06S0203
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.tile R7C38:PLC2
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arc: S3_V06S0003 N3_V06S0003
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arc: S3_V06S0103 N3_V06S0103
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.tile R7C39:PLC2
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arc: S3_V06S0203 N3_V06S0103
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.tile R7C40:PLC2
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arc: S3_V06S0103 N3_V06S0003
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arc: S3_V06S0303 N3_V06S0203
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.tile R7C42:PLC2
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arc: N1_V02N0601 S3_V06N0303
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.tile R9C33:PLC2
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arc: N3_V06N0303 S1_V02N0501
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.tile R9C35:PLC2
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arc: S3_V06S0103 N3_V06S0003
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.tile R9C36:PLC2
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arc: S3_V06S0003 N3_V06S0003
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.tile R9C37:PLC2
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arc: S3_V06S0103 N3_V06S0103
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.tile TAP_R19C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R20C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R21C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R23C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R23C51:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R24C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R25C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R25C51:TAP_DRIVE
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arc: L_HPBX0000 G_VPTX0000
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.tile TAP_R26C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R27C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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.tile TAP_R28C31:TAP_DRIVE
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arc: R_HPBX0000 G_VPTX0000
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