micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
54 lines
2.2 KiB
Verilog
54 lines
2.2 KiB
Verilog
// ============================================================
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// Neural Memory System (NMS) -- Weight SRAM candidate W2 "packed":
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// same private-per-slot semantics as nms_weight_direct.v, but each
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// slot's P_IN*DATA_WIDTH-wide tile storage is decomposed into P_IN
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// separate, narrow (DATA_WIDTH=8-bit-wide) single-port memories (one
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// per MAC lane) instead of one wide 64-bit memory. Reassembly into the
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// full tile word is a static concatenation of P_IN registered
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// per-lane outputs -- no runtime mux, no real LUT cost expected there.
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// Exists to measure whether narrower-but-more-numerous memories pack
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// into fewer total DP16KD blocks than nms_weight_direct.v's wider-but-
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// fewer instances, per the user's own explicit ask (NMS spec S6) to
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// measure width/depth/packing real DP16KD cost rather than assume it.
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// ============================================================
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module nms_weight_packed #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter N_SLOTS = 4,
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parameter MAX_TILES = 16,
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parameter TIW = (MAX_TILES <= 1) ? 1 : $clog2(MAX_TILES)
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)(
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input clk,
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input rst,
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input [N_SLOTS-1:0] fill_we,
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input [N_SLOTS*TIW-1:0] fill_addr_flat,
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input [N_SLOTS*DATA_WIDTH*P_IN-1:0] fill_data_flat,
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input [N_SLOTS-1:0] rd_en,
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input [N_SLOTS*TIW-1:0] rd_addr_flat,
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output [N_SLOTS*DATA_WIDTH*P_IN-1:0] rd_data_flat
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);
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genvar g, p;
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generate
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for (g = 0; g < N_SLOTS; g = g + 1) begin : GEN_SLOT
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for (p = 0; p < P_IN; p = p + 1) begin : GEN_LANE
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reg [DATA_WIDTH-1:0] mem [0:MAX_TILES-1];
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reg [DATA_WIDTH-1:0] rd_data_reg;
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always @(posedge clk) begin
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if (fill_we[g])
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mem[fill_addr_flat[g*TIW +: TIW]] <=
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fill_data_flat[g*DATA_WIDTH*P_IN + p*DATA_WIDTH +: DATA_WIDTH];
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if (rd_en[g])
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rd_data_reg <= mem[rd_addr_flat[g*TIW +: TIW]];
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end
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assign rd_data_flat[g*DATA_WIDTH*P_IN + p*DATA_WIDTH +: DATA_WIDTH] = rd_data_reg;
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end
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end
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endgenerate
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endmodule
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