micheleandClaude Sonnet 5
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C.9 (pinout): certified citing this session's own F1-F7 work; also regenerated a real bitstream for the CURRENT full-system build (ecppack, 0 errors, real part header) rather than relying on an older pre-flash build's bitstream. C.10 (timing): certified citing Fmax re-measured at every structural change this session (54.58->75.30->73.88->66.68->67.91MHz), critical path re-verified identical at every re-synthesis. C.11 (toolchain): full RTL->Yosys->nextpnr-ecp5->ecppack flow re-run on the current build, 0 errors at every stage. Real-silicon behavior explicitly declared NOT certifiable (no physical hardware available). C.12 (netasm): certified citing 20/20 tests plus a real hardware round-trip already demonstrated earlier this session. C.13 (datasheet/RTL coherence): real, current discrepancy found and declared -- none of this campaign's 7 bugs (BUG-001-007) are yet mentioned in the datasheet or engine spec doc. Correct and expected (found after those docs were last updated), flagged as required follow-up after the campaign completes. C.14: page-mode PSRAM and the flash subsystem are actually COMPLETE, not "in progress" as the certification prompt assumed -- verified against real repo state. D (cross-cutting): CDC certified via C.7. Reset scheme found by exhaustive grep across all 20 RTL files to be synchronous-only everywhere (no posedge rst anywhere) -- a real fact, differs from the prompt's async-assert/sync-deassert phrasing, not a defect. FSM: the campaign's own BUG-002-007 ARE FSM defects, found and documented, but no exhaustive reachability analysis of every FSM was done (stated reserve). Width/overflow: 2 real cases found across the whole session. Lint: full-system Yosys check, one real warning (known PSRAM tristate), zero accidental latches confirmed signal-by-signal (25 explicit confirmations). Determinism: no real non-determinism found (the one apparent inconsistency, BUG-003, traced to genuinely different test stimuli between attempts, not unstable behavior for identical stimuli). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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C.14 — Lavori in corso (page-mode PSRAM, sottosistema flash)
Data: 2026-09-04.
Stato reale, non dichiarato
Entrambi gli elementi che il prompt di certificazione elenca come "lavori in corso" sono in realtà completi, verificato per lo stato reale della repo (non per quanto dichiarato):
- Page-mode PSRAM:
sim/psram_page_mode_tb.vesiste, copreACCESS_CYCLES,PAGE_CYCLES,tCEM(idle timeout e budget mid-burst), conpsram_model.vche fa$fatalsu violazione di timing reale. Rieseguito PASS in Fase 0 (§C.3). - Sottosistema flash:
rtl/spi_flash_master.v,flash_copy_engine.v,flash_slot_manager.vesistono, 8 opcode SPI (0x40-0x47) integrati inspi_neuron_top.v, bus SPI reso indipendente in Fase F7. 33 testbench del progetto includono 9 dedicati al sottosistema flash, tutti PASS in Fase 0.
Nessun residuo "in corso" trovato: non ci sono moduli RTL a metà, TODO irrisolti nel codice, o funzionalità dichiarate ma non implementate per questi due elementi.
Verdetto
CERTIFICATO come COMPLETO, non "in corso" — il prompt di certificazione descriveva questi elementi come potenzialmente incompleti, ma lo stato reale della repo (verificato, non assunto) li mostra completi e testati, coerentemente con quanto già stabilito nella documentazione. Nessuno scostamento trovato qui.