michele 1ddaa9adfd feat: real-toolchain Fmax check for Phase 5 spi_neuron_top ...

Yosys + nextpnr-ecp5 synthesis of the extended spi_neuron_top.v
(layer_sequencer + mux + arbiter Port C wired in), speed grade -8,
N_INPUTS=32/N_NEURONS=1: PARALLEL=8 -> 40.57 MHz FAIL, PARALLEL=2 ->
42.54 MHz FAIL. Both worse than Phase 4 alone (~52.58/~55.85 MHz for
the identical configs) -- the Phase 5 wiring cost real timing
headroom. Critical path also shifted from Phase 4's saturation-
comparator finding to neuron_memory's x_mem/w_mem LUT-RAM read-mux
tree feeding the accumulator. Full analysis and candidate next steps
(block RAM for x_mem/w_mem, pipelining, a seed sweep to separate
placement noise from a structural bottleneck) recorded under Phase 7
in docs/FPGA-NeuralNetwork-Engine.md.

2026-09-02 20:17:52 +02:00

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