micheleandClaude Sonnet 5
2e4cedc761
Implements M5: neural_director.v dispatches job descriptors to whichever of N_SLOTS (memory_manager, neural_processor) pairs is currently free (first-free scheduling per §9's initial policy), with a parametric-depth ready-queue FIFO for jobs arriving faster than slots can absorb them. Scope for this milestone (see decisions.log DEC-0007): a reduced 4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full 8-state baseline -- dependency tracking, the waiting queue, and wake-up are §10's explicit responsibility (Dependency Manager, M6, not yet built), and slot-completion detection runs as an always-active per-slot tracker rather than a dedicated FSM state, for the same reason DEC-0002 already gave for the Neural Processor's own FSM (gating concurrent per-unit progress behind one shared state kills throughput). Verified with Verilator (N_SLOTS=2, each slot backed by its own independent behavioral memory rather than sharing V1's real PSRAM -- M4 already proved that path for one slot; this milestone's own concern is scheduling across multiple slots): 4/4 tests pass -- 3 jobs submitted to 2 slots (first two dispatch immediately, third correctly queues until a slot frees), and a deliberate burst that forces the ready queue to genuinely fill and recover. Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real place&route (via a synthesis-only timing harness, same TRELLIS_IO pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
4195 lines
90 KiB
Plaintext
4195 lines
90 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R13C1:CIB_LR
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arc: E3_H06E0303 JQ5
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.tile CIB_R1C29:CIB
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C31:CIB
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arc: E1_H02E0501 V06N0303
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arc: S3_V06S0003 JQ0
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.tile CIB_R1C32:CIB
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arc: JA0 H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C33:CIB
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arc: S3_V06S0003 H06W0003
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.tile CIB_R1C36:CIB
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arc: W3_H06W0003 E3_H06W0003
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.tile CIB_R1C37:CIB
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arc: E3_H06E0303 S3_V06N0303
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.tile CIB_R1C41:CIB
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arc: E1_H02E0501 S1_V02N0501
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.tile CIB_R1C42:CIB
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arc: W3_H06W0003 JQ0
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.tile CIB_R1C43:CIB
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arc: E3_H06E0303 W3_H06E0303
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arc: JA0 W1_H02E0501
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enum: CIB.JB0MUX 0
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.tile CIB_R1C48:CIB
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arc: JD7 E1_H01W0100
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.tile CIB_R1C49:CIB
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arc: H01W0100 W3_H06E0303
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.tile CIB_R32C1:CIB_LR
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arc: E3_H06E0303 JQ5
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.tile CIB_R34C13:CIB_EBR
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arc: E3_H06E0303 W3_H06E0303
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.tile CIB_R34C19:CIB_EBR
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arc: E3_H06E0303 W3_H06E0303
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.tile CIB_R34C1:CIB_LR_S
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arc: E3_H06E0303 JQ5
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.tile CIB_R34C25:CIB_EBR
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arc: E3_H06E0303 W3_H06E0303
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.tile CIB_R34C26:CIB_EBR
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arc: N1_V02N0701 H06W0203
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.tile CIB_R34C27:CIB_EBR
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arc: S1_V02S0701 E1_H02W0701
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.tile CIB_R34C29:CIB_EBR
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arc: E1_H02E0401 V06S0203
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arc: E1_H02E0701 V06S0203
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arc: W1_H02W0701 V06S0203
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arc: W3_H06W0203 V06S0203
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.tile CIB_R34C30:CIB_EBR
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arc: N1_V02N0101 E1_H01W0100
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arc: N1_V02N0401 H02E0401
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arc: S1_V02S0701 H02E0701
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.tile CIB_R34C31:CIB_EBR
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arc: H01W0100 W3_H06E0303
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arc: N1_V02N0401 W1_H02E0401
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arc: S1_V02S0701 W1_H02E0701
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.tile CIB_R34C32:CIB_EBR
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arc: S1_V02S0101 N1_V01S0100
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arc: S3_V06S0303 N1_V01S0100
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.tile CIB_R34C7:CIB_EBR
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arc: E3_H06E0303 W3_H06E0303
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.tile CIB_R35C1:CIB_LR
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arc: JA0 E1_H02W0501
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arc: JA3 E1_H02W0701
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R37C1:CIB_LR
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arc: E3_H06E0303 JQ5
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.tile CIB_R38C1:CIB_LR
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arc: E3_H06E0303 JQ5
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arc: JA0 E1_H02W0501
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enum: CIB.JB0MUX 0
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.tile CIB_R38C89:CIB_LR
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arc: JA3 V02N0501
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arc: W3_H06W0303 JF5
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enum: CIB.JB3MUX 0
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.tile CIB_R39C89:CIB_LR
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arc: N1_V02N0501 H06E0303
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arc: S1_V02S0201 H06E0103
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arc: S1_V02S0701 H06E0203
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.tile CIB_R40C89:CIB_LR
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arc: JA0 V02S0701
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arc: JA3 V00B0000
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arc: V00B0000 V02S0201
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R5C1:CIB_PLL1
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R5C89:CIB_PLL1
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R70C3:CIB_PLL3
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R70C42:VCIB_DCU0
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C43:VCIB_DCUA
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C44:VCIB_DCUB
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C45:VCIB_DCUC
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C46:VCIB_DCUD
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enum: CIB.JA1MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C47:VCIB_DCUF
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C48:VCIB_DCU3
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C49:VCIB_DCU2
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C50:VCIB_DCUG
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C51:VCIB_DCUH
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C52:VCIB_DCUI
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C53:VCIB_DCU1
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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.tile CIB_R70C69:VCIB_DCU0
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C6:CIB_EFB0
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enum: CIB.JB3MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C70:VCIB_DCUA
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C71:VCIB_DCUB
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C72:VCIB_DCUC
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C73:VCIB_DCUD
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enum: CIB.JA1MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C74:VCIB_DCUF
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C75:VCIB_DCU3
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C76:VCIB_DCU2
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile MIB_R0C29:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C31:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C32:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C42:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C43:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C30:EBR_SPINE_UL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R12C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R13C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R17C0:PICL0_DQS2
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R18C0:PICL1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R1C29:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C31:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C32:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C42:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C43:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R35C0:PICL0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R36C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R37C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R38C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C0:PICL1_DQS0
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R39C90:PICR1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R40C90:PICR2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C30:EBR_SPINE_LL0
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R71C1:BANKREF6
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile MIB_R71C89:BANKREF3
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile R11C41:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R12C31:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R13C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R13C19:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R13C25:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R13C29:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C31:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C33:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R13C37:PLC2
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R13C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R17C41:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R18C31:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R19C29:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R19C31:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R19C33:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R23C41:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R24C31:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R25C29:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R25C31:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R25C33:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R29C41:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R30C31:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R31C29:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R31C31:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R31C33:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R32C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R32C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R32C25:PLC2
|
|
arc: S1_V02S0401 W3_H06E0203
|
|
|
|
.tile R32C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R33C25:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
|
|
.tile R33C26:PLC2
|
|
arc: A0 V02N0701
|
|
arc: C0 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 1111010110100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R33C27:PLC2
|
|
arc: S1_V02S0501 H01E0101
|
|
|
|
.tile R33C29:PLC2
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
|
|
.tile R33C30:PLC2
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: B0 V02N0101
|
|
arc: C0 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C31:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: B0 N1_V02S0101
|
|
arc: C0 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: E1_H02E0201 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R33C32:PLC2
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: B0 H02W0101
|
|
arc: C0 H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 1100111111000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
|
|
.tile R33C33:PLC2
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R35C15:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R35C21:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R35C26:PLC2
|
|
arc: E1_H02E0401 S1_V02N0401
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: V00B0100 H02W0701
|
|
arc: A2 V01N0101
|
|
arc: B2 S1_V02N0101
|
|
arc: C2 S1_V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 N1_V02S0001
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0001 F2
|
|
arc: F2 F2_SLICE
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: S1_V02S0201 Q2
|
|
word: SLICEB.K0.INIT 1111111111111110
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C27:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: H00L0000 H02E0001
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H00L0100
|
|
arc: A1 V02N0701
|
|
arc: A3 V00T0000
|
|
arc: A4 H02E0701
|
|
arc: A6 S1_V02N0301
|
|
arc: B0 F3
|
|
arc: B1 V02N0301
|
|
arc: B3 V01N0001
|
|
arc: B4 N1_V02S0501
|
|
arc: B6 V01S0000
|
|
arc: C0 V02N0401
|
|
arc: C1 F6
|
|
arc: C2 E1_H01W0000
|
|
arc: C4 H02E0401
|
|
arc: C6 V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 H00R0000
|
|
arc: D2 Q2
|
|
arc: D3 E1_H02W0001
|
|
arc: D4 V00B0000
|
|
arc: D6 H01W0000
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H02E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q4
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
word: SLICEB.K1.INIT 1001100101100110
|
|
word: SLICEA.K1.INIT 1001011001101001
|
|
word: SLICED.K0.INIT 0110100110010110
|
|
word: SLICEC.K0.INIT 0000000011110100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C28:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: A6 W1_H02E0701
|
|
arc: B1 Q1
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 F1
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 H02W0301
|
|
arc: C1 H00L0000
|
|
arc: C2 V02N0601
|
|
arc: C3 V02N0401
|
|
arc: C4 V00T0100
|
|
arc: C5 H01E0001
|
|
arc: C6 V02N0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 H02E0001
|
|
arc: D2 Q2
|
|
arc: D3 E1_H02W0201
|
|
arc: D4 H00R0100
|
|
arc: D5 H02E0001
|
|
arc: D6 H02E0201
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q4
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q4
|
|
arc: W1_H02W0001 Q2
|
|
arc: W1_H02W0101 Q3
|
|
word: SLICEB.K0.INIT 1111110000001100
|
|
word: SLICEB.K1.INIT 1100111111000000
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEA.K1.INIT 0011110011001100
|
|
word: SLICEC.K0.INIT 1100110011110000
|
|
word: SLICEC.K1.INIT 1111001111000000
|
|
word: SLICED.K0.INIT 0000000000110010
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R35C29:PLC2
|
|
arc: E1_H02E0101 H01E0101
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: H00R0100 H02E0501
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 E1_H01W0000
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: A0 V02N0701
|
|
arc: A1 V02N0501
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0701
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0301
|
|
arc: B0 H00R0100
|
|
arc: B1 H00R0100
|
|
arc: B2 H00R0100
|
|
arc: B3 H00R0100
|
|
arc: B4 E1_H02W0301
|
|
arc: B5 V00B0100
|
|
arc: C0 H02E0401
|
|
arc: C1 H02E0401
|
|
arc: C2 H02E0401
|
|
arc: C3 H02E0401
|
|
arc: C4 V00T0100
|
|
arc: C5 S1_V02N0201
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D4 E1_H02W0201
|
|
arc: D5 S1_V02N0401
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 F2
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK1
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0001 F0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0000 F1
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R35C30:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0303 E1_H01W0100
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: A0 E1_H02W0501
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0501
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 V02N0301
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 H02W0301
|
|
arc: B5 H02E0301
|
|
arc: B6 V00B0000
|
|
arc: C0 W1_H02E0601
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 W1_H02E0601
|
|
arc: C3 W1_H02E0601
|
|
arc: C4 V00T0000
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V02N0001
|
|
arc: CE3 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 H00R0000
|
|
arc: D3 H00R0000
|
|
arc: D4 H02W0201
|
|
arc: D5 E1_H02W0001
|
|
arc: D6 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 Q6
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0301 F3
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 F0
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0201 F2
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1100110011110000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R35C31:PLC2
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 H02W0101
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 E1_H01W0100
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A0 V02N0701
|
|
arc: A1 H02W0501
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 V02N0301
|
|
arc: A5 N1_V02S0101
|
|
arc: B0 W1_H02E0101
|
|
arc: B1 W1_H02E0101
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 E1_H02W0101
|
|
arc: B5 H00L0000
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C4 V00T0000
|
|
arc: C5 N1_V02S0001
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0201
|
|
arc: D4 H00L0100
|
|
arc: D5 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F1
|
|
arc: LSR1 V00B0100
|
|
arc: S1_V02S0001 F2
|
|
arc: S3_V06S0003 F3
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R35C32:PLC2
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: B0 H01W0100
|
|
arc: C0 H00L0100
|
|
arc: C2 H00L0100
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 V01S0100
|
|
arc: D2 Q2
|
|
arc: E1_H01E0101 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: S1_V02S0201 Q0
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q1
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEA.K0.INIT 0011111111000000
|
|
word: SLICEA.K1.INIT 0000000011111111
|
|
word: SLICEB.K0.INIT 0000111111110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C33:PLC2
|
|
arc: W1_H02W0101 H01E0101
|
|
|
|
.tile R35C35:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R35C3:PLC2
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
arc: W1_H02W0701 E3_H06W0203
|
|
|
|
.tile R35C41:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R35C9:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R36C26:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: A0 V02N0701
|
|
arc: C0 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: E1_H02E0201 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 1111010110100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R36C27:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: A0 V02N0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V01N0001 Q0
|
|
word: SLICEA.K0.INIT 0101010100000000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
|
|
.tile R36C28:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
arc: A2 V01N0101
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 E1_H02W0701
|
|
arc: B2 V01N0001
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 S1_V02N0701
|
|
arc: C2 H02E0601
|
|
arc: C3 H00L0000
|
|
arc: C4 V02N0201
|
|
arc: C5 H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V02N0001
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V02N0601
|
|
arc: E1_H02E0401 F4
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F3
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEB.K0.INIT 0010000000000000
|
|
word: SLICEC.K0.INIT 1001011001101001
|
|
word: SLICEC.K1.INIT 0110100110010110
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R36C29:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 H06W0303
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: V00B0000 H02W0401
|
|
arc: V00T0000 H02W0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 S1_V02N0301
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B4 V02S0701
|
|
arc: B5 H02E0101
|
|
arc: B6 N1_V01S0000
|
|
arc: C0 H02E0601
|
|
arc: C1 H02E0601
|
|
arc: C2 H02E0601
|
|
arc: C3 H02E0601
|
|
arc: C4 V00T0000
|
|
arc: C5 V02N0201
|
|
arc: C6 Q6
|
|
arc: CE3 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 H00R0000
|
|
arc: D3 H00R0000
|
|
arc: D4 H00L0100
|
|
arc: D5 V02N0401
|
|
arc: D6 S1_V02N0401
|
|
arc: E1_H01E0001 F2
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 H02W0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0701 F7
|
|
arc: S3_V06S0003 F3
|
|
arc: V01S0100 F0
|
|
arc: W1_H02W0401 Q6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1111000011001100
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R36C30:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 N1_V01S0100
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 Q1
|
|
arc: B2 S1_V02N0101
|
|
arc: B4 V02N0501
|
|
arc: B6 H01E0101
|
|
arc: B7 H02E0101
|
|
arc: C0 H00L0000
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 N1_V01N0001
|
|
arc: C3 V02N0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: D1 V00B0100
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 V02N0201
|
|
arc: D4 W1_H02E0201
|
|
arc: D6 V00B0000
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0301 F3
|
|
arc: E1_H02E0601 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0000 Q4
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0101 F3
|
|
arc: N1_V02N0401 Q4
|
|
arc: S1_V02S0301 F3
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0301 F3
|
|
arc: W1_H02W0601 Q4
|
|
arc: W1_H02W0701 Q7
|
|
arc: W3_H06W0003 Q0
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K1.INIT 0000111100000000
|
|
word: SLICED.K0.INIT 1110111001000100
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 1100110010101010
|
|
word: SLICEC.K0.INIT 0011001111001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
|
|
.tile R36C31:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0201 H02W0201
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 H06E0303
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: V00T0000 H02W0201
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
arc: W1_H02W0701 E1_H01W0100
|
|
arc: A0 V02N0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 V02N0701
|
|
arc: A3 V02N0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 H02E0701
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: B4 V02S0501
|
|
arc: B5 H02W0301
|
|
arc: B6 V00B0000
|
|
arc: C0 V02S0401
|
|
arc: C1 V02S0401
|
|
arc: C2 V02S0401
|
|
arc: C3 V02S0401
|
|
arc: C4 V00T0000
|
|
arc: C5 V02N0001
|
|
arc: C6 H02E0401
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 H00R0000
|
|
arc: D3 H00R0000
|
|
arc: D4 V02S0601
|
|
arc: D5 H02W0001
|
|
arc: D6 V02N0601
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 H02E0301
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0303 Q6
|
|
arc: S1_V02S0101 F3
|
|
arc: V00B0000 Q6
|
|
arc: V01S0000 F1
|
|
arc: W1_H02W0001 F0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1001011001101001
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R36C32:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 E1_H01E0001
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 N1_V02S0101
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 E1_H02W0301
|
|
arc: B2 E1_H02W0301
|
|
arc: B3 E1_H02W0301
|
|
arc: B4 H02E0101
|
|
arc: B5 V02N0501
|
|
arc: C0 E1_H02W0601
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 E1_H02W0601
|
|
arc: C4 V02S0201
|
|
arc: C5 V00T0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H00R0000
|
|
arc: D1 H00R0000
|
|
arc: D2 H00R0000
|
|
arc: D3 H00R0000
|
|
arc: D4 V00B0000
|
|
arc: D5 W1_H02E0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 F6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H01W0000 F0
|
|
arc: H01W0100 F6
|
|
arc: LSR1 W1_H02E0301
|
|
arc: N1_V01N0101 F6
|
|
arc: S1_V02S0101 F3
|
|
arc: S1_V02S0201 F2
|
|
arc: S3_V06S0103 F1
|
|
arc: V01S0100 F6
|
|
arc: W3_H06W0303 F6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R36C33:PLC2
|
|
arc: W1_H02W0701 H01E0101
|
|
|
|
.tile R36C34:PLC2
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0601 W3_H06E0303
|
|
|
|
.tile R37C13:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R37C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R37C23:PLC2
|
|
arc: E1_H02E0701 E3_H06W0203
|
|
|
|
.tile R37C25:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
|
|
.tile R37C26:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: H00L0100 H02W0101
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: V00T0000 H02W0201
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 V02N0701
|
|
arc: A5 E1_H01W0000
|
|
arc: A7 E1_H01W0000
|
|
arc: B1 H02W0301
|
|
arc: B2 E1_H01W0100
|
|
arc: B3 E1_H01W0100
|
|
arc: C0 H02W0601
|
|
arc: C1 E1_H01W0000
|
|
arc: C2 H02W0401
|
|
arc: C3 H02W0601
|
|
arc: C4 H02W0601
|
|
arc: C5 V02N0201
|
|
arc: C6 H02W0401
|
|
arc: C7 V02N0001
|
|
arc: D1 V02N0001
|
|
arc: D2 V02N0201
|
|
arc: D3 V00B0100
|
|
arc: D5 E1_H01W0100
|
|
arc: D7 E1_H01W0100
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H01W0000 F3
|
|
arc: M0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0000
|
|
word: SLICEA.K0.INIT 1111000011110000
|
|
word: SLICEA.K1.INIT 0011110011110000
|
|
word: SLICEB.K0.INIT 1111000011010010
|
|
word: SLICEB.K1.INIT 1111000001111000
|
|
word: SLICEC.K0.INIT 1111000011110000
|
|
word: SLICEC.K1.INIT 0101101010101010
|
|
word: SLICED.K0.INIT 1111000011110000
|
|
word: SLICED.K1.INIT 0101101010101010
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
|
|
.tile R37C27:PLC2
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
arc: V00B0000 E1_H02W0401
|
|
arc: A1 V02N0701
|
|
arc: A3 V01N0101
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 N1_V01N0101
|
|
arc: B1 E1_H02W0301
|
|
arc: B4 V02N0501
|
|
arc: B5 V00B0100
|
|
arc: B6 V00T0000
|
|
arc: C1 E1_H02W0601
|
|
arc: C2 F6
|
|
arc: C3 E1_H01W0000
|
|
arc: C4 E1_H01E0101
|
|
arc: C5 S1_V02N0001
|
|
arc: C6 V00T0100
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: D1 H02E0201
|
|
arc: D2 S1_V02N0201
|
|
arc: D3 V02N0001
|
|
arc: D4 F2
|
|
arc: D5 V02N0401
|
|
arc: D6 V01N0001
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 F3
|
|
arc: E1_H02E0501 Q5
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0103 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 F4
|
|
arc: H01W0000 Q6
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M3 H02W0201
|
|
arc: M6 W1_H02E0401
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0301 F1
|
|
arc: N1_V02N0401 F6
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 F3
|
|
arc: S1_V02S0401 F4
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q3
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0001 F2
|
|
arc: W1_H02W0101 F3
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q6
|
|
arc: W1_H02W0601 Q6
|
|
word: SLICEC.K1.INIT 0000110010101110
|
|
word: SLICEA.K0.INIT 0000000011111111
|
|
word: SLICEC.K0.INIT 0011111111000000
|
|
word: SLICED.K0.INIT 0000000000000010
|
|
word: SLICEB.K1.INIT 0000000000000101
|
|
word: SLICEB.K0.INIT 0000111100000000
|
|
word: SLICEA.K1.INIT 0110100110010110
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R37C28:PLC2
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0100 H02W0701
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: A0 F5
|
|
arc: A1 F5
|
|
arc: A2 H02E0701
|
|
arc: A4 V00B0000
|
|
arc: A5 H02E0501
|
|
arc: A7 H02E0701
|
|
arc: B0 E1_H01W0100
|
|
arc: B1 Q1
|
|
arc: B2 H00R0000
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 H00L0000
|
|
arc: B7 V00T0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 W1_H02E0601
|
|
arc: C2 H00L0000
|
|
arc: C4 V02S0001
|
|
arc: C5 V00T0100
|
|
arc: C7 V00T0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: D1 V00B0100
|
|
arc: D2 V00T0100
|
|
arc: D4 E1_H01W0100
|
|
arc: D5 V00B0000
|
|
arc: D7 V00B0000
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 F7
|
|
arc: LSR1 H02E0301
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q0
|
|
arc: S1_V02S0501 F5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 F2
|
|
arc: W1_H02W0501 F5
|
|
word: SLICEB.K0.INIT 0010101000000000
|
|
word: SLICEC.K0.INIT 1100111000001010
|
|
word: SLICEA.K0.INIT 1111010011110000
|
|
word: SLICEA.K1.INIT 0010111000001100
|
|
word: SLICEC.K1.INIT 0000101010001010
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R37C29:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
arc: W3_H06W0203 N3_V06S0203
|
|
arc: A0 H02W0701
|
|
arc: A1 H02W0701
|
|
arc: A2 V00T0000
|
|
arc: A4 V00B0000
|
|
arc: A6 F5
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 S1_V02N0301
|
|
arc: B3 Q3
|
|
arc: C0 E1_H02W0401
|
|
arc: C1 E1_H02W0401
|
|
arc: C2 E1_H02W0601
|
|
arc: C3 N1_V01S0100
|
|
arc: C4 N1_V02S0001
|
|
arc: C5 H02E0401
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D1 N1_V02S0201
|
|
arc: D2 V02N0201
|
|
arc: D3 V02N0001
|
|
arc: D4 V02N0401
|
|
arc: D5 V02N0601
|
|
arc: D6 S1_V02N0401
|
|
arc: E1_H01E0101 F6
|
|
arc: E1_H02E0501 F5
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0100 F5
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 F5
|
|
arc: LSR1 V00T0100
|
|
arc: M0 H02W0601
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0101 F6
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0501 F5
|
|
arc: S1_V02S0501 F5
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0501 F5
|
|
arc: W1_H02W0601 Q4
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEB.K0.INIT 1010101011110000
|
|
word: SLICEC.K0.INIT 1010101011110000
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICED.K0.INIT 1111111101010101
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
word: SLICEA.K1.INIT 1001011001101001
|
|
word: SLICEC.K1.INIT 0000111100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
|
|
.tile R37C30:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: V00B0000 H02E0401
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: A0 E1_H02W0701
|
|
arc: A1 E1_H02W0701
|
|
arc: A2 E1_H02W0701
|
|
arc: A3 E1_H02W0701
|
|
arc: A4 E1_H02W0701
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 H00R0000
|
|
arc: A7 Q7
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0301
|
|
arc: B2 H02E0301
|
|
arc: B3 H02E0301
|
|
arc: B4 H02W0101
|
|
arc: B5 H02W0301
|
|
arc: C0 N1_V02S0601
|
|
arc: C1 N1_V02S0601
|
|
arc: C2 N1_V02S0601
|
|
arc: C3 N1_V02S0601
|
|
arc: C4 N1_V02S0201
|
|
arc: C5 S1_V02N0201
|
|
arc: C6 N1_V02S0001
|
|
arc: C7 V01N0101
|
|
arc: CE3 H00R0100
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 N1_V01S0000
|
|
arc: D4 H00L0100
|
|
arc: D5 V02N0401
|
|
arc: D6 V01N0001
|
|
arc: D7 F0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0100
|
|
arc: M0 V00T0100
|
|
arc: M2 V00T0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK1
|
|
arc: MUXCLK1 CLK1
|
|
arc: MUXCLK2 CLK1
|
|
arc: MUXCLK3 CLK1
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0101 F1
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 F2
|
|
arc: V01S0100 F3
|
|
arc: W1_H02W0501 Q5
|
|
arc: W1_H02W0601 Q6
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 1010101011110000
|
|
word: SLICED.K1.INIT 1010111110100000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R37C31:PLC2
|
|
arc: E1_H02E0401 W1_H02E0401
|
|
arc: H00L0000 E1_H02W0201
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: W1_H02W0301 E1_H02W0201
|
|
arc: W1_H02W0401 V02N0401
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: A0 V02S0501
|
|
arc: A1 H02W0701
|
|
arc: A2 H02W0701
|
|
arc: A3 V02S0501
|
|
arc: A4 H02W0701
|
|
arc: A5 H02W0501
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B4 V00B0100
|
|
arc: B5 H00L0000
|
|
arc: C0 V02S0601
|
|
arc: C1 V02S0601
|
|
arc: C2 V02S0601
|
|
arc: C3 V02S0601
|
|
arc: C4 V02S0201
|
|
arc: C5 S1_V02N0001
|
|
arc: CLK1 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 H02E0201
|
|
arc: D2 H02E0201
|
|
arc: D3 H02E0201
|
|
arc: D4 N1_V02S0601
|
|
arc: D5 V00B0000
|
|
arc: E1_H01E0001 F2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 H02E0301
|
|
arc: S1_V02S0301 F1
|
|
arc: V01S0000 F3
|
|
arc: V01S0100 F0
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
enum: SLICEC.MODE RAMW
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE DPRAM
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE DPRAM
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.WREMUX WRE
|
|
enum: CLK1.CLKMUX CLK
|
|
|
|
.tile R37C32:PLC2
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: A0 W1_H02E0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: LSR1 W1_H02E0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
word: SLICEA.K0.INIT 1010101000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R37C33:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: A0 V02N0501
|
|
arc: C0 W1_H02E0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R37C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R38C11:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R38C13:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R38C17:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R38C19:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R38C23:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R38C25:PLC2
|
|
arc: E1_H02E0701 W3_H06E0203
|
|
|
|
.tile R38C26:PLC2
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: A0 H02E0701
|
|
arc: C0 E1_H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V01S0100 Q0
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
|
|
.tile R38C27:PLC2
|
|
arc: E1_H02E0101 V02S0101
|
|
arc: E1_H02E0201 V02S0201
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 V02S0301
|
|
arc: A1 H00L0100
|
|
arc: A2 H00L0100
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 V02S0101
|
|
arc: C0 H00L0100
|
|
arc: C1 H00L0000
|
|
arc: C2 N1_V01S0100
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02S0001
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 V02S0001
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M3 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V01N0101 F2
|
|
arc: V01S0100 F0
|
|
word: SLICEA.K0.INIT 0000111111110000
|
|
word: SLICEA.K1.INIT 0101101010010110
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R38C28:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 V02S0401
|
|
arc: A0 H01E0001
|
|
arc: A1 H01E0001
|
|
arc: A3 H01E0001
|
|
arc: B0 H02E0101
|
|
arc: B1 H02E0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0101
|
|
arc: C0 H00L0000
|
|
arc: C2 H00L0000
|
|
arc: C6 Q6
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: D1 H02E0201
|
|
arc: D2 H01E0101
|
|
arc: D3 H02E0201
|
|
arc: D6 H01W0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H02E0301 Q3
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q7
|
|
arc: H01W0100 Q6
|
|
arc: LSR1 V00T0000
|
|
arc: M0 H02E0601
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M3 H00L0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 Q6
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q7
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q6
|
|
word: SLICEA.K0.INIT 1100100101101100
|
|
word: SLICEA.K1.INIT 0110011011001100
|
|
word: SLICEB.K0.INIT 0011110011001100
|
|
word: SLICEB.K1.INIT 0110011011001100
|
|
word: SLICED.K0.INIT 1111111100001111
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R38C29:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0100 H02E0301
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0100 V02S0701
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: A0 N1_V02S0701
|
|
arc: A7 H02E0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: H00L0000 Q2
|
|
arc: H01W0000 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M0 V00B0100
|
|
arc: M1 H00L0100
|
|
arc: M2 H02W0601
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0000
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0001 Q0
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0303 Q6
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEB.K0.INIT 1111111111110000
|
|
word: SLICEB.K1.INIT 1111111111110000
|
|
word: SLICEC.K0.INIT 1111111111110000
|
|
word: SLICEC.K1.INIT 1111111111110000
|
|
word: SLICED.K0.INIT 1111111111110000
|
|
word: SLICED.K1.INIT 0101010101010000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R38C30:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0601 H01E0001
|
|
arc: A4 V02S0301
|
|
arc: A6 N1_V01S0100
|
|
arc: B0 W1_H02E0101
|
|
arc: C4 Q4
|
|
arc: C6 Q6
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H00L0100
|
|
arc: D6 H01W0000
|
|
arc: E1_H01E0001 F1
|
|
arc: E1_H01E0101 F1
|
|
arc: E1_H02E0001 F0
|
|
arc: E1_H02E0101 F1
|
|
arc: E1_H02E0301 F1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 F1
|
|
arc: H01W0000 F1
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F1
|
|
arc: N1_V01N0101 F1
|
|
arc: N1_V02N0101 F1
|
|
arc: N1_V02N0301 F1
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 F1
|
|
arc: V01S0100 F1
|
|
arc: W1_H02W0101 F1
|
|
arc: W1_H02W0301 F1
|
|
arc: W3_H06W0103 F1
|
|
word: SLICEC.K0.INIT 1111000010101010
|
|
word: SLICED.K0.INIT 1111000010101010
|
|
word: SLICEA.K0.INIT 0011001100110000
|
|
word: SLICEA.K1.INIT 1111111111110000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R38C31:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: V00T0000 V02S0401
|
|
arc: A4 N1_V01S0100
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 V02S0101
|
|
arc: B3 Q3
|
|
arc: C0 H00L0000
|
|
arc: C1 H00L0100
|
|
arc: C2 V02N0401
|
|
arc: C3 H02E0601
|
|
arc: C4 H01E0001
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H01E0101
|
|
arc: D1 H01E0101
|
|
arc: D2 H01E0101
|
|
arc: D3 H01E0101
|
|
arc: D4 V00B0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0401 Q4
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0301 Q1
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q3
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1111000011001100
|
|
word: SLICEB.K0.INIT 1111000011001100
|
|
word: SLICEC.K0.INIT 1111101000001010
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R38C32:PLC2
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 V00B0000
|
|
arc: B0 N1_V02S0101
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 W1_H02E0101
|
|
arc: B3 H02E0301
|
|
arc: C0 V02N0401
|
|
arc: C1 H00L0100
|
|
arc: C2 H00L0000
|
|
arc: C4 H02E0601
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0201
|
|
arc: D1 N1_V02S0201
|
|
arc: D2 V02S0001
|
|
arc: D3 V00T0100
|
|
arc: D4 H02E0001
|
|
arc: E1_H01E0001 Q3
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0401 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q2
|
|
word: SLICEA.K0.INIT 1111000011001100
|
|
word: SLICEA.K1.INIT 1111001111000000
|
|
word: SLICEB.K1.INIT 1010101011001100
|
|
word: SLICEB.K0.INIT 1111001111000000
|
|
word: SLICEC.K0.INIT 1010101011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
|
|
.tile R38C33:PLC2
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
|
|
.tile R38C35:PLC2
|
|
arc: W1_H02W0501 E3_H06W0303
|
|
|
|
.tile R38C3:PLC2
|
|
arc: W1_H02W0501 E1_H02W0401
|
|
|
|
.tile R38C41:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R38C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R38C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R38C59:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R38C5:PLC2
|
|
arc: W1_H02W0401 E3_H06W0203
|
|
|
|
.tile R38C65:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R38C71:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R38C77:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R38C7:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R38C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R39C26:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
|
|
.tile R39C27:PLC2
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 H02W0501
|
|
arc: V00B0000 H02W0401
|
|
arc: A0 H00L0000
|
|
arc: B0 H02E0301
|
|
arc: C0 E1_H01W0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q4
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q6
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M6 N1_V01N0101
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0201 Q0
|
|
arc: V00B0100 Q7
|
|
arc: V00T0100 Q3
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R39C28:PLC2
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: C3 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 N1_V01S0000
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q2
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q3
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: M6 N1_V01N0101
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q0
|
|
arc: V00B0000 Q4
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F3
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEB.K1.INIT 1111000011111111
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
|
|
.tile R39C29:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 H02W0101
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: V00B0000 H02E0401
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: V00T0100 H02W0301
|
|
arc: A0 H00L0100
|
|
arc: A1 H00L0000
|
|
arc: B0 V00T0000
|
|
arc: B1 E1_H01W0100
|
|
arc: B3 Q3
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 N1_V01S0100
|
|
arc: C3 E1_H02W0401
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D1 E1_H02W0201
|
|
arc: D3 V02S0001
|
|
arc: F0 F5A_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: LSR0 V00B0000
|
|
arc: M0 V00T0100
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V02N0001 F0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0301 Q3
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICEB.K1.INIT 1100110011110000
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
word: SLICEA.K1.INIT 1001011001101001
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R39C30:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 W1_H02E0201
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: V00B0100 H02E0701
|
|
arc: A0 H00L0000
|
|
arc: A2 V00T0000
|
|
arc: B1 Q1
|
|
arc: B2 H02E0301
|
|
arc: B3 N1_V02S0101
|
|
arc: C0 N1_V01S0100
|
|
arc: C1 S1_V02N0601
|
|
arc: C3 H00L0100
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0201
|
|
arc: D1 N1_V01S0000
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 N1_V01S0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q1
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0000 Q2
|
|
arc: W1_H02W0101 Q1
|
|
arc: W1_H02W0201 Q0
|
|
arc: W1_H02W0301 Q3
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
word: SLICEA.K1.INIT 1100110011110000
|
|
word: SLICEB.K0.INIT 1010101011001100
|
|
word: SLICEB.K1.INIT 1111000011001100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
|
|
.tile R39C31:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: W1_H02W0401 V06S0203
|
|
arc: A0 F5
|
|
arc: A5 V00B0000
|
|
arc: B2 N1_V02S0301
|
|
arc: B5 H00L0000
|
|
arc: C0 H02E0401
|
|
arc: C2 N1_V01N0001
|
|
arc: C5 H01E0001
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D2 H02E0001
|
|
arc: D5 H02E0201
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V01N0001 Q2
|
|
arc: W1_H02W0201 Q2
|
|
word: SLICEB.K0.INIT 1111000011001100
|
|
word: SLICEC.K1.INIT 1001011001101001
|
|
word: SLICEA.K0.INIT 0101101010100101
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R39C32:PLC2
|
|
arc: H00L0100 V02S0101
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 V02S0101
|
|
arc: A5 N1_V01S0100
|
|
arc: B2 V02S0301
|
|
arc: B3 V02S0301
|
|
arc: B4 H00L0000
|
|
arc: B5 H00L0000
|
|
arc: C2 V02S0401
|
|
arc: C3 V02S0401
|
|
arc: C4 V02S0201
|
|
arc: C5 H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 V02S0001
|
|
arc: D4 H02E0001
|
|
arc: D5 H00L0100
|
|
arc: E1_H01E0001 Q5
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 V00T0000
|
|
arc: M0 V00B0000
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 V00B0100
|
|
arc: M5 V01S0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: V00B0000 F4
|
|
arc: V01S0000 F2
|
|
word: SLICEB.K0.INIT 0110100110010110
|
|
word: SLICEB.K1.INIT 1001011001101001
|
|
word: SLICEC.K0.INIT 0110100110010110
|
|
word: SLICEC.K1.INIT 1001011001101001
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R39C33:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
|
|
.tile R39C37:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R39C38:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R39C43:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R39C44:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R39C49:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R39C50:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R39C55:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R39C56:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R39C61:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R39C62:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R39C67:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R39C68:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R39C73:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R39C74:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R39C79:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R39C80:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R39C85:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
|
|
.tile R39C86:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R3C41:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R40C28:PLC2
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
|
|
.tile R41C30:PLC2
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
|
|
.tile R4C31:PLC2
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile R6C31:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R7C29:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C31:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C33:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C37:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R9C41:PLC2
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile TAP_R33C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R35C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R36C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R37C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R38C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R39C31:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|