micheleandClaude Sonnet 5
5f0d7f101c
Implements M3: three parametric dual-port buffers for the §12 data-plane (Input/Weight/Result), reusing the proven BRAM-inference idiom from the frozen hardware/v1/rtl/act_buffer.v (synchronous write, synchronous REGISTERED read, no reset on the read register -- keeps Yosys off the LUT-RAM path). Verified with Verilator: 10/10 tests pass (write-then-read correctness, extreme INT8 round-tripping, weight_buffer's full 64-bit tile width round-tripping, undisturbed re-reads). Real synthesis at two depths per module (6 configs total): 0 CHECK problems, every configuration correctly infers DP16KD (never LUT-RAM). Non-obvious real finding: weight_buffer's BRAM cost is driven by its P_IN*DATA_WIDTH tile width, not its DEPTH -- an 8x depth reduction (512->64) left DP16KD usage unchanged at 2, while activation_buffer/result_buffer (byte-wide) scale as naively expected (2->1). All default-depth configs PASS at 80MHz with large margin (287-367 MHz) via real nextpnr-ecp5 place&route. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
49 lines
1.7 KiB
Verilog
49 lines
1.7 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// FPGA-Neural V2 -- Weight Buffer (M3, docs/v2-description.md §14)
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//
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// Holds the "Weight Buffer" of the §12 data-plane diagram. Unlike
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// activation_buffer (one INT8 per signal id), each address here holds
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// one WHOLE TILE of P_IN weights -- exactly the width a Neural
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// Processor (M1) consumes per cycle on its weight_data port, so the
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// Memory Manager (M4) can feed a processor one tile/cycle without any
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// additional muxing/serialization at this buffer's boundary (§7:
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// avoid big dynamic muxes).
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//
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// Same BRAM-inference idiom as activation_buffer.v /
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// hardware/v1/rtl/act_buffer.v (dual-port, Port A sync write, Port B
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// sync REGISTERED read, no reset on the read register). DEPTH (in
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// TILES, not individual weights) is fully parametric.
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// ================================================================
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module weight_buffer #(
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parameter DEPTH = 512, // depth in TILES (each DEPTH*P_IN*DATA_WIDTH/8 bytes)
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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localparam ADDR_WIDTH = $clog2(DEPTH),
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localparam TILE_WIDTH = DATA_WIDTH * P_IN
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)(
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input wire clk,
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input wire wr_en,
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input wire [ADDR_WIDTH-1:0] wr_addr,
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input wire signed [TILE_WIDTH-1:0] wr_data,
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input wire [ADDR_WIDTH-1:0] rd_addr,
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output reg signed [TILE_WIDTH-1:0] rd_data
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);
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reg signed [TILE_WIDTH-1:0] mem [0:DEPTH-1];
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always @(posedge clk) begin
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if (wr_en)
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mem[wr_addr] <= wr_data;
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end
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always @(posedge clk) begin
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rd_data <= mem[rd_addr];
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end
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endmodule
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