micheleandClaude Sonnet 5
8b8ca239ca
The repository had accumulated multiple, contradictory "current state" documents for V2 hardware: an old V1 IT/EN datasheet copy nested inside hardware/v2/docs/datasheet/, a stray untracked duplicate at repo root (docs/DatasheetLatex/), and a second, much older documentation track (hardware/v2/docs/*.md: PRE_PCB_VERIFICATION.md, PRE_PCB_CLOSURE_4POINT.md, MEMORY_UPGRADE_64MB_N8.md, and 10 more) describing an earlier PSRAM/ N_SLOTS<=2 milestone alongside the real, current SDRAM/N_SLOTS=4 board. The LaTeX datasheet's own front matter (features/pinout cover pages) and chapter 9 (benchmarks) were themselves still describing that obsolete architecture, contradicting the real, current chapters 5/7/10 elsewhere in the same document. This commit: - Flattens hardware/v2/docs/datasheet/files/docs/datasheet/v2-en/* up to hardware/v2/docs/datasheet/ (was 4 levels of redundant nesting). - Removes the old V1 IT/EN LaTeX copies and the stray root-level duplicate entirely (recoverable from git history, not from disk). - Preserves the real component reference PDFs (ECP5 eval board, ISSI PSRAM, programming cables) under datasheet/references/. - Removes 13 superseded hardware/v2/docs/*.md status documents after folding every real, unique fact they contained into the datasheet: SPI max verified clock (12MHz, exact 12.8MHz CDC edge), SDRAM directed boundary test (21/21 PASS), 16MHz oscillator MPN (ECS-3225MV-160-BN-TR), and the real FPGA<->SDRAM ball mapping cross-check. - Rewrites the datasheet's own front matter, ch.4 (parameters), ch.8 (top-level module -- was documenting the wrong, non-physical top entirely), and ch.9 (benchmarks) to describe the current, real SDRAM/ N_SLOTS=4 production board, while keeping the real PSRAM-era chapters as clearly-labeled history rather than deleting correctly-measured work. - Fixes a title-page tikzpicture that was clipped off the page edge (pre-existing, unrelated to this change) by scaling it to fit. Net: 85 files changed, -8814/+498 lines. hardware/v2/docs/ now contains exactly one current datasheet plus FIRST_POWER_ON.md (a bring-up runbook, not a duplicate spec). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
67 lines
3.7 KiB
TeX
67 lines
3.7 KiB
TeX
\chapter{Dataflow scheduling}
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\label{ch:sched}
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\section{Node lifecycle}
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\begin{center}
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\begin{tikzpicture}[font=\scriptsize,node distance=16mm,>=Stealth]
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\node[fnstate](e){EMPTY};
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\node[fnstate,right=of e](w){WAITING};
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\node[fnstate,right=of w](r){READY};
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\node[fnstate,right=of r](d){DISPATCHED};
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\draw[fnarrow] (e) -- node[fnlbl,above]{register, deps$>$0} (w);
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\draw[fnarrow] (e) to[bend left=25] node[fnlbl,above]{register, deps$=$0} (r);
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\draw[fnarrow] (w) -- node[fnlbl,above]{all producers done} (r);
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\draw[fnarrow] (r) -- node[fnlbl,above]{Director accepts} (d);
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\end{tikzpicture}
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\end{center}
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\code{DISPATCHED} is terminal (\S\ref{ch:arch}): a real, honest
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consequence, not an oversight --- see the roadmap (ch.~\ref{ch:roadmap})
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for the deferred slot-reclamation work item.
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\section{Verified graph topologies}
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\begin{tabularx}{\textwidth}{L{3.4cm} Y}
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\toprule
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\rowh \thd{Topology} & \thd{What it proves} \\
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\midrule
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Shared producer, 2 consumers & One node's completion resolves the dependency count of \emph{two} different waiting nodes independently. \\
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\rowa Multiple producers, 1 consumer & A node with \code{required}$>$1 only becomes \code{READY} once \emph{every} listed producer has completed, tracked across separate wake-up events. \\
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2-hop transitive diamond ($A,B$ independent; $C$ dep-$A$; $D$ dep-$B$; $E$ dep-$C,D$) & Correct cascading wake-up two hops deep --- $E$ does not fire until $C$ and $D$ have \emph{themselves} genuinely completed, not merely been marked ready. \\
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\rowa Mixed-depth fan-in (node depending on both a root and a 1-hop descendant) & Dependency resolution does not assume a uniform graph depth. \\
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Multilayer (8 layer-1 neurons, random INT8 data, feeding 2 layer-2 neurons reading their real shared result bytes) & Real cross-node \emph{data} forwarding through real PSRAM --- layer-2's golden values are computed from the real bytes layer-1 actually wrote, not from an independent expectation. \\
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\bottomrule
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\end{tabularx}
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All topologies above were exercised with the real, full
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\code{neural\_multiprocessor.v} (real V1 PSRAM chain, real
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\code{slot\_mem\_arbiter.v}) and verified bit-exact against a software
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golden model.
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\section{First-free dispatch}
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The Neural Director's own scheduling policy is deliberately the simplest
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one that is provably correct: a fixed, lowest-index priority scan over
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currently-free slots. Round-robin, least-loaded, or any fairness-aware
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alternative was explicitly deferred until real measured data showed
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whether it mattered (\S\ref{sec:fairness}).
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\section{Measured scheduling behavior}
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\label{sec:fairness}
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Real per-slot data (\code{N\_SLOTS}=4, a 128-neuron dense-layer
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workload) shows a striking imbalance: slots~0 and~1 each deliver 1008
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real tiles, while slots~2 and~3 deliver only 16 each --- despite all four
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slots reporting near-100\% ``busy'' utilization. The cause is not
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unfairness in isolation: once the shared PSRAM port is saturated
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(ch.~\ref{ch:mem}), there is rarely a moment where the low-index slots
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are simultaneously busy \emph{and} the high-index slots have nothing to
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do, so the fixed low-index-first scan keeps re-selecting the same two
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slots. This is a real, measured limitation of the current scheduler,
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carried into ch.~\ref{ch:roadmap} as an open item rather than patched
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without first measuring whether it is worth the added complexity for
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real workloads.
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\section{Correctness guarantees (measured, not assumed)}
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Across the full final benchmark campaign (6 workloads $\times$ 4
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\code{N\_SLOTS} configurations, re-verified after both memory
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optimizations): \textbf{zero} lost jobs, \textbf{zero} duplicated jobs
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(\code{jobs\_allocated == jobs\_completed == neurons\_completed} exactly,
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every run), \textbf{zero} deadlocks, \textbf{zero} timeouts, correct
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multi-hop dependency wake-up in every topology tested.
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