micheleandClaude Sonnet 5
8af16d3a12
Implements M6: dependency_manager.v tracks a table of node
descriptors (node_id/state/required_dependencies/resolved_
dependencies/producer_ids -- §10's exact field list), incrementing a
waiting node's resolved count whenever one of its listed producers
completes, transitioning it to READY once resolved==required, and
dispatching ready nodes to the Neural Director (M5) one at a time via
a backpressure-safe valid/ready interface.
Verified with Verilator on a small hand-built DAG: node0/node1 have no
dependencies (dispatch immediately); node2 depends on BOTH node0 AND
node1 ("dipendenze multiple") and stays WAITING until both complete,
confirmed via an explicit negative check after only one resolves;
node3 depends on node0 ALONE, demonstrating a single producer
("node0") satisfying two different consumers' dependencies
("risultati condivisi... piu' consumer") -- node3 fully, node2
partially. 4/4 tests pass.
Scope for this milestone (decisions.log DEC-0008): dependency
COUNTING/readiness only, no direct producer-to-consumer value
forwarding (§11 frames that as a "quando possibile" optimization, not
a correctness requirement -- deferred until real bandwidth
measurements justify it) and no node-slot reclamation after dispatch
(not exercised by any scenario built so far).
Real synthesis: 0 CHECK problems, 763 LUT4/474 FF/0 DSP/0 CCU2C. Real
place&route (module fits the TRELLIS_IO budget as a bare top-level
this time, no harness needed): Fmax 155.30 MHz, PASS at 80MHz.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
3.1 KiB
3.1 KiB
FPGA-Neural V2 — stato roadmap
Fonte del mandato: docs/v2-description.md (root del repository). Baseline
funzionale/numerica/bit-exact: hardware/v1/ (frozen, sola lettura — vedi
hardware/v1/README.md).
Legenda: [ ] non iniziato · [~] in corso · [x] completo (sim+synth+timing
reali, non solo scritto).
- M1 — Neural Processor (
hardware/v2/rtl/neural_processor.v, P8). Bit-exact vs V1 (7/7 test, Verilator), pipeline a 8 stadi funzionante, throughput reale (1 tile/ciclo). Sintesi reale: 0 problemi CHECK, Fmax 183.12 MHz (ACC_WIDTH=32) — vedilogs/experiments.logEXP-0001/EXP-0002,logs/errors.logper 3 bug reali trovati e risolti (2 del toolchain Icarus, 1 RTL). - M2 — Processor Array (
neural_processor_array.v). 1/2/4/8 processor testati (sim concorrenza reale + sintesi/P&R reali). Fmax sempre PASS a 80MHz (159.11→134.70 MHz). Scoperta: il DSP (MULT18X18D), non LUT/FF, satura per primo (88% a N=8) — vedilogs/decisions.logDEC-0005. - M3 — Buffers (
activation_buffer.v,weight_buffer.v,result_buffer.v). Tutti inferiscono DP16KD reale (10/10 test, 6/6 config sintetizzate 0 problemi). Scoperta: il costo BRAM di weight_buffer e' guidato da P_IN (larghezza), non da DEPTH. - M4 — Memory Manager (
memory_manager.v,prefetch_engine.v), backend PSRAM V1 riusato SENZA MODIFICHE. End-to-end reale (3/3 job PASS) con vero neural_processor + vera catena PSRAM V1. 3 bug RTL trovati/risolti (logs/errors.logERR-0006). Fmax 165.86 MHz. - M5 — Neural Director (
neural_director.v), scheduling first-free. 4/4 test PASS (dispatch + coda + backpressure reale su N_SLOTS=2). FSM ridotta a 4 stati, dependency rimandata a M6 (logs/decisions.logDEC-0007). Fmax 250.50 MHz. - M6 — Dependency Manager (
dependency_manager.v), ready/waiting queue, dependency counters, wake-up, producer tracking. 4/4 test PASS (dipendenze multiple + produttore condiviso/piu' consumer). Fmax 155.30 MHz. Forwarding di valori e riuso slot rimandati (logs/decisions.logDEC-0008). - M7 — Dataflow Core (
dataflow_core.v), integrazione completa. - M8 — PSRAM integration, controller V1 non modificato, misura reale.
- M9 — Full benchmark, tabella V1 vs V2 (§32 del mandato).
- M10 — Optimization, solo sulla base dei dati raccolti in M1-M9.
Log
Vedi hardware/v2/logs/ (development.log per la cronologia di sessione,
decisions.log per le decisioni architetturali con motivazione,
experiments.log per ogni EXP-XXXX end-to-end).
Regole non negoziabili attive (§34 del mandato, per riferimento rapido)
- V1 (
hardware/v1/) rimane intatta — mai modificata. - V2 vive esclusivamente sotto
hardware/v2/. - Nessun risultato inventato: THEORETICAL vs SIMULATED vs SYNTHESIZED vs POST-P&R sempre etichettati esplicitamente.
- Ogni modifica/esperimento/decisione registrata nei log, mai persa.
- Ogni esperimento ha un ID univoco, mai riutilizzato — anche i FAIL restano.