micheleandClaude Sonnet 5
8890b0abc2
Real Alliance Memory AS4C4M16SA-6TIN datasheet (Rev 5.0, Table 17) specifies tMRD as a fixed 2-tCK cycle count, not an ns value. sdram_controller.v modeled it via ns_to_cycles(12), which rounded to 2 cycles by coincidence at every previously-tested frequency (100/133/166MHz) but rounds to only 1 cycle at the real 64MHz board target -- an under-provisioned one-time init sequence. Fixed by hardcoding T_MRD=2, matching how CAS_LATENCY is already modeled. Verified zero regression: full 9-config legacy sweep + a new dedicated 64MHz config (461/461 PASS each), N=2/N=4 D-Stress (identical cycle counts), board-level smoke test (11/11 PASS). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
460 lines
22 KiB
Verilog
460 lines
22 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// NMS STEP16 -- minimal, CORRECT-FIRST SDR SDRAM controller for
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// Alliance Memory AS4C4M16SA-6TIN (64Mbit/8MB, x16, -6 speed grade:
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// tCK=6ns/166MHz max, CAS latency 3).
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//
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// Design priority explicitly stated by the governing spec:
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// correctness > performance > elegance. This controller therefore:
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// - ALWAYS uses auto-precharge (A10=1 on every READ/WRITE) --
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// every transaction activates a row, bursts BURST_LEN words, and
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// closes the row again before the next transaction. This is NOT
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// the fastest possible design (no page-hit/keep-row-open
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// optimization, unlike psram_controller.v's own real page-mode),
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// but it is trivially correct: no per-row state to track, no
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// risk of a stale-open-row bug, exactly one code path for every
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// transaction regardless of address history.
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// - Real JEDEC SDR SDRAM command encoding (CS#/RAS#/CAS#/WE#),
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// real power-up sequence (200us wait, PRECHARGE ALL, 8x AUTO
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// REFRESH, LOAD MODE REGISTER), real periodic AUTO REFRESH
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// insertion between transactions (tREFI = 4096 rows / 64ms).
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// - Real, standard -6-speed-grade SDR SDRAM timing (datasheet-
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// standard values, not vendor-specific tuning): tRCD=3cyc,
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// tRP=3cyc, tRAS(min)=7cyc, tRC=10cyc, tMRD=2cyc @166MHz -- all
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// re-derived per CLK_FREQ_MHZ so the same RTL is reused across
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// the Phase 4 100/133/166MHz sweep (STEP16's own explicit
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// "measure, do not estimate" requirement).
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//
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// Address format: word address (16-bit words), decomposed as
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// {bank[1:0], row[11:0], col[7:0]} -- matches the REAL AS4C4M16SA's
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// own 4-bank x 4096-row x 256-column x16 organization (4*4096*256 =
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// 4M words = 8MB, confirmed against the real datasheet capacity).
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//
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// External protocol matches this project's own established
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// mem_req/mem_wr/mem_addr/mem_wdata/mem_rdata/mem_ready convention
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// (same idiom as psram_controller.v), generalized to a BURST: one
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// req initiates a full BURST_LEN-word transaction (the natural unit
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// for this workload -- one weight TILE = P_IN*DATA_WIDTH/16 = 4
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// words at BURST_LEN=4, an exact match, not a coincidence chosen
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// after the fact -- STEP16 Phase 1 identified this exact byte count
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// per tile before any RTL was written).
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// ============================================================
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module sdram_controller #(
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parameter CLK_FREQ_MHZ = 166,
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parameter BURST_LEN = 4, // 1, 4, or 8 -- Phase 4 sweep parameter
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parameter ADDR_WIDTH = 22 // word address: 2 bank + 12 row + 8 col
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)(
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input wire clk,
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input wire rst,
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input wire req,
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input wire wr,
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input wire [ADDR_WIDTH-1:0] addr, // burst-aligned word address
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input wire [16*BURST_LEN-1:0] wdata, // BURST_LEN words, word0 first
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// STEP19: per-burst-word DQM write mask, 2 bits/word (bit0=low
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// byte, bit1=high byte, real SDR SDRAM DQM polarity: 1=masked/
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// NOT written, memory array retains its old value for that byte;
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// 0=written). Ties to {2*BURST_LEN{1'b0}} (never mask, i.e.
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// "always write full word") reproduces this module's own STEP16
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// behavior exactly -- every existing caller (sdram_weight_
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// backend.v, sdram_weight_backend_pack128.v, tb_sdram_controller.v)
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// was updated to pass that literal tie-off, so read/weight-fetch
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// behavior is byte-for-byte unchanged. Only meaningful for `wr`
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// transactions; ignored for reads (dqm is forced 0 during reads
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// regardless, since real SDR SDRAM masks READ OUTPUT with DQM too,
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// and this controller always wants valid read data back).
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input wire [2*BURST_LEN-1:0] wmask,
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output reg [16*BURST_LEN-1:0] rdata, // valid the same cycle `ready` pulses
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output reg ready, // pulses once, whole burst transaction done
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output reg busy,
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// ---- real SDRAM physical pins ----
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output reg sdram_cke,
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output reg sdram_cs_n,
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output reg sdram_ras_n,
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output reg sdram_cas_n,
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output reg sdram_we_n,
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output reg [1:0] sdram_ba,
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output reg [11:0] sdram_a,
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inout wire [15:0] sdram_dq,
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output reg [1:0] sdram_dqm
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);
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localparam BURST_IDXW = (BURST_LEN <= 1) ? 1 : $clog2(BURST_LEN);
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// ---- real, standard -6-speed-grade timing, re-derived per
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// CLK_FREQ_MHZ (ceiling division: never UNDER-count a real ns
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// requirement) ----
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function integer ns_to_cycles;
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input integer ns;
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begin
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ns_to_cycles = (ns * CLK_FREQ_MHZ + 999) / 1000;
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end
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endfunction
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localparam T_RCD = ns_to_cycles(18); // ACTIVE -> READ/WRITE
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localparam T_RP = ns_to_cycles(18); // PRECHARGE -> ACTIVE
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// ACTIVE->PRECHARGE minimum (tRAS=42ns=7cyc@166MHz) is not
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// separately waited on: this design's own fixed sequencing
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// (tRCD + CAS_LATENCY + BURST_LEN data cycles, always >= 3+3+1=7
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// even at the narrowest BURST_LEN=1) already comfortably exceeds
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// it by construction before auto-precharge can begin internally.
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// tMRD is specified by the real AS4C4M16SA-6TIN datasheet (Table 17)
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// as a FIXED CYCLE COUNT ("2 tCK"), not a nanosecond value -- unlike
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// tRCD/tRP, which genuinely are ns-based and correctly belong behind
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// ns_to_cycles(). A previous draft modeled tMRD as ns_to_cycles(12),
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// an assumed-equivalent ns figure that happened to round up to
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// exactly 2 cycles at every frequency this design had been tested at
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// (100/133/166MHz), silently masking the wrong unit model. At the
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// real V2 board's own 64MHz operating point, ns_to_cycles(12) rounds
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// to only 1 cycle -- one cycle short of the real, fixed 2-tCK
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// minimum -- found via this step's own fresh datasheet-level audit
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// (real Alliance Memory AS4C4M16SA-6TIN datasheet Rev.5.0, Table 17).
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// Fixed by hardcoding the real, frequency-independent requirement
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// directly, matching how CAS_LATENCY (also a real fixed-cycle spec)
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// is already modeled two lines below.
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localparam T_MRD = 2; // LOAD MODE REGISTER -> any command (tMRD = 2 tCK, fixed)
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localparam T_INIT_US= 200; // power-up wait, real datasheet value
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localparam T_INIT = T_INIT_US * CLK_FREQ_MHZ;
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localparam CAS_LATENCY = 3; // fixed for this part/speed grade
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// real refresh interval: 4096 rows must each be refreshed within
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// 64ms -> one AUTO REFRESH at least every 64e6ns/4096 = 15625ns
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localparam T_REFI = ns_to_cycles(15625);
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localparam CNTW = $clog2((T_INIT>T_REFI ? T_INIT : T_REFI) + 1);
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// JEDEC SDR SDRAM commands are encoded directly in the FSM below
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// via named signal drives (cs_n/ras_n/cas_n/we_n), not a lookup
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// table -- clearer to review against the real datasheet's own
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// command truth table line by line.
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// tRC (ACTIVATE-to-ACTIVATE minimum, same bank), used by both the
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// init-refresh and steady-state refresh wait.
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function [CNTW-1:0] T_RC_MINUS1;
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localparam integer T_RC = ns_to_cycles(60);
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begin
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T_RC_MINUS1 = T_RC[CNTW-1:0] - 1'b1;
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end
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endfunction
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localparam
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S_INIT_WAIT = 5'd0,
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S_INIT_PRE_WAIT = 5'd2,
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S_INIT_REF = 5'd3,
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S_INIT_REF_WAIT = 5'd4,
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S_INIT_MRS_WAIT = 5'd6,
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S_IDLE = 5'd7,
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S_REFRESH_WAIT = 5'd9,
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S_ACTIVATE_WAIT = 5'd11,
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S_CAS_WAIT = 5'd13,
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S_BURST_READ = 5'd14,
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S_BURST_WRITE = 5'd15,
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S_PRECHARGE_WAIT = 5'd16;
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reg [4:0] state;
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reg [CNTW-1:0] wait_cnt;
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reg [3:0] init_ref_cnt;
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reg [CNTW-1:0] refresh_timer;
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reg [BURST_IDXW-1:0] burst_idx;
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reg req_wr_reg;
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reg [1:0] req_bank_reg;
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reg [11:0] req_row_reg;
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reg [7:0] req_col_reg;
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reg [16*BURST_LEN-1:0] wdata_reg;
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reg [2*BURST_LEN-1:0] wmask_reg;
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wire [1:0] addr_bank = addr[ADDR_WIDTH-1:ADDR_WIDTH-2];
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wire [11:0] addr_row = addr[ADDR_WIDTH-3:8];
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wire [7:0] addr_col = addr[7:0];
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// req_pending: latches a req that arrives in S_IDLE on the SAME
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// cycle a periodic AUTO REFRESH is also due. Without this, a
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// single-cycle req pulse (this project's own established
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// mem_req convention -- see weight_prefetch_engine.v's own header
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// comment) would be silently dropped whenever refresh wins
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// arbitration that cycle: the caller only holds req high for one
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// cycle, has no idea refresh was chosen instead, and then waits
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// forever for a `ready` that will never come -- a real,
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// frequency/burst-alignment-dependent deadlock found by STEP16's
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// own Phase 4 100/133/166MHz sweep (reproduced at BURST_LEN=1,
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// CLK_FREQ_MHZ=133, but the race is general, not specific to that
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// combination -- it is a matter of which absolute cycle each test
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// vector's req happens to land on).
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reg req_pending;
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wire eff_wr = req ? wr : req_wr_reg;
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wire [1:0] eff_bank = req ? addr_bank : req_bank_reg;
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wire [11:0] eff_row = req ? addr_row : req_row_reg;
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wire [7:0] eff_col = req ? addr_col : req_col_reg;
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wire [16*BURST_LEN-1:0] eff_wdata = req ? wdata : wdata_reg;
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wire [2*BURST_LEN-1:0] eff_wmask = req ? wmask : wmask_reg;
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// tri-state DQ: driven only during a write burst
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reg dq_out_en;
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reg [15:0] dq_out;
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assign sdram_dq = dq_out_en ? dq_out : 16'hzzzz;
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// Mode register value: burst length code + sequential burst type
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// (A3=0) + CAS latency 3 (A6:4=011) + standard write burst (A9=0).
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function [11:0] mrs_value;
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input integer burst_len;
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reg [2:0] bl_code;
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begin
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bl_code = (burst_len==1) ? 3'b000 :
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(burst_len==2) ? 3'b001 :
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(burst_len==4) ? 3'b010 :
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(burst_len==8) ? 3'b011 : 3'b111; // 111 = full page, unused here
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mrs_value = {3'b000, 1'b0, 3'b011, 1'b0, bl_code};
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end
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endfunction
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always @(posedge clk) begin
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if (rst) begin
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state <= S_INIT_WAIT;
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wait_cnt <= T_INIT[CNTW-1:0];
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init_ref_cnt <= 4'd0;
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refresh_timer <= T_REFI[CNTW-1:0];
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sdram_cke <= 1'b1; // held high throughout, real part supports CKE-always-high operation
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sdram_cs_n <= 1'b1;
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sdram_ras_n <= 1'b1;
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sdram_cas_n <= 1'b1;
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sdram_we_n <= 1'b1;
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sdram_ba <= 2'b00;
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sdram_a <= 12'h000;
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sdram_dqm <= 2'b00; // both byte lanes always enabled (weight/tile fetch always full-word)
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dq_out_en <= 1'b0;
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ready <= 1'b0;
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busy <= 1'b1;
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req_pending <= 1'b0;
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end else begin
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// default: NOP every cycle unless a state below overrides it
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sdram_cs_n <= 1'b0;
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sdram_ras_n <= 1'b1;
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sdram_cas_n <= 1'b1;
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sdram_we_n <= 1'b1;
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ready <= 1'b0;
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dq_out_en <= 1'b0;
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sdram_dqm <= 2'b00; // default: no mask (reads always want valid data; writes override below per-word)
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if (refresh_timer != 0) refresh_timer <= refresh_timer - 1'b1;
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// Latch a fresh req's fields UNCONDITIONALLY, every cycle,
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// regardless of what state the controller is currently in
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// -- not just while in S_IDLE. ERR-0019's own fix only
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// covered "refresh wins arbitration the SAME cycle S_IDLE
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// sees req" -- but a real caller (e.g. slot_mem_arbiter_
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// wide.v) can pulse req for exactly one cycle at ANY time,
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// including a cycle where the controller is mid-refresh
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// (S_REFRESH_WAIT) or finishing a PREVIOUS transaction's
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// own PRECHARGE_WAIT tail -- i.e. NOT in S_IDLE at all that
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// cycle. The old S_IDLE-only latch silently missed those,
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// permanently starving whichever requester's pulse landed
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// there (found via the real N=2 D-Stress integration
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// benchmark, EXP-0042: both slots' memory managers hung
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// forever at tile_idx=0 while the arbiter's own `owner`
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// stayed locked on a grant the controller had already
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// forgotten -- a real, reproducible full-system deadlock,
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// not merely a slower run).
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if (req) begin
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req_wr_reg <= wr;
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req_bank_reg <= addr_bank;
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req_row_reg <= addr_row;
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req_col_reg <= addr_col;
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wdata_reg <= wdata;
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wmask_reg <= wmask;
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req_pending <= 1'b1;
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end
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case (state)
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S_INIT_WAIT: begin
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busy <= 1'b1;
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else begin
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// PRECHARGE ALL: RAS#=0,CAS#=1,WE#=0, A10=1
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sdram_ras_n <= 1'b0; sdram_we_n <= 1'b0;
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sdram_a[10] <= 1'b1;
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wait_cnt <= T_RP[CNTW-1:0] - 1'b1;
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state <= S_INIT_PRE_WAIT;
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end
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end
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S_INIT_PRE_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else begin
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state <= S_INIT_REF;
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end
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end
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S_INIT_REF: begin
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// AUTO REFRESH: RAS#=0,CAS#=0,WE#=1
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sdram_ras_n <= 1'b0; sdram_cas_n <= 1'b0;
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wait_cnt <= T_RC_MINUS1();
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state <= S_INIT_REF_WAIT;
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end
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S_INIT_REF_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else if (init_ref_cnt < 4'd7) begin
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init_ref_cnt <= init_ref_cnt + 1'b1;
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state <= S_INIT_REF;
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end else begin
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// LOAD MODE REGISTER: RAS#=0,CAS#=0,WE#=0, addr=mode value
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sdram_ras_n <= 1'b0; sdram_cas_n <= 1'b0; sdram_we_n <= 1'b0;
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sdram_ba <= 2'b00;
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sdram_a <= mrs_value(BURST_LEN);
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wait_cnt <= T_MRD[CNTW-1:0] - 1'b1;
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state <= S_INIT_MRS_WAIT;
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end
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end
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S_INIT_MRS_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else begin
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busy <= 1'b0;
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state <= S_IDLE;
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end
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end
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S_IDLE: begin
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busy <= 1'b0;
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// req (if any) was already latched into req_pending
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// unconditionally above, regardless of state -- see
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// that latch's own comment for why it must not be
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// scoped to only this state.
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if (refresh_timer == 0) begin
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// periodic AUTO REFRESH -- no row is ever left
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// open between transactions (auto-precharge
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// always used), so we can refresh immediately,
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// no PRECHARGE-ALL needed here.
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busy <= 1'b1;
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sdram_ras_n <= 1'b0; sdram_cas_n <= 1'b0;
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wait_cnt <= T_RC_MINUS1();
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refresh_timer <= T_REFI[CNTW-1:0];
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state <= S_REFRESH_WAIT;
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end else if (req || req_pending) begin
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busy <= 1'b1;
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req_wr_reg <= eff_wr;
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req_bank_reg <= eff_bank;
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req_row_reg <= eff_row;
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req_col_reg <= eff_col;
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wdata_reg <= eff_wdata;
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wmask_reg <= eff_wmask;
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req_pending <= 1'b0;
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// ACTIVATE: RAS#=0,CAS#=1,WE#=1, ba=bank, a=row
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sdram_ras_n <= 1'b0;
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sdram_ba <= eff_bank;
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sdram_a <= eff_row;
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wait_cnt <= T_RCD[CNTW-1:0] - 1'b1;
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state <= S_ACTIVATE_WAIT;
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end
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end
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S_REFRESH_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else state <= S_IDLE;
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end
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S_ACTIVATE_WAIT: begin
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if (wait_cnt != 0) begin
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wait_cnt <= wait_cnt - 1'b1;
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end else begin
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// READ or WRITE with auto-precharge (A10=1):
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// CAS#=0, WE#=(0 for write /1 for read), ba=bank,
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// a[7:0]=col, a[10]=1
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sdram_cas_n <= 1'b0;
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sdram_we_n <= req_wr_reg ? 1'b0 : 1'b1;
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sdram_ba <= req_bank_reg;
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sdram_a <= {4'b0100, req_col_reg}; // a[11]=0,a[10]=1(auto-precharge),a[9:8]=0
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burst_idx <= {BURST_IDXW{1'b0}};
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if (req_wr_reg) begin
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dq_out_en <= 1'b1;
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dq_out <= wdata_reg[15:0];
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sdram_dqm <= wmask_reg[1:0];
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state <= S_BURST_WRITE;
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end else begin
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// Cycle-exact derivation (not assumed --
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// see the module's own design log /
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// EXP-0040 for the full walkthrough):
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// cas_n=0 becomes VISIBLE to the real chip
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// one cycle after this NBA (call that
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// cycle "C"). Entering S_CAS_WAIT also
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// takes effect at cycle C, with wait_cnt
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// set here. The state's own "wait_cnt==0"
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// capture branch first fires at cycle
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// C + wait_cnt_initial. We want that to be
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// C + CAS_LATENCY (data must be valid
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// exactly CAS_LATENCY real clocks after
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// the command is sampled) -- so
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// wait_cnt_initial = CAS_LATENCY exactly,
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|
// no adjustment.
|
|
wait_cnt <= CAS_LATENCY[CNTW-1:0];
|
|
state <= S_CAS_WAIT;
|
|
end
|
|
end
|
|
end
|
|
|
|
S_CAS_WAIT: begin
|
|
if (wait_cnt != 0) begin
|
|
wait_cnt <= wait_cnt - 1'b1;
|
|
end else begin
|
|
rdata[0 +: 16] <= sdram_dq;
|
|
// BURST_LEN==1 is a real, distinct edge case:
|
|
// word0 IS the whole (only) burst -- go
|
|
// straight to precharge-wait. Routing it
|
|
// through S_BURST_READ instead (burst_idx
|
|
// already at 1, one past the only valid
|
|
// index) was a real deadlock, found and fixed
|
|
// via the Phase 3 burst=1 test (EXP-0040):
|
|
// S_BURST_READ's own "burst_idx==BURST_LEN-1"
|
|
// exit check (==0) can never be true again
|
|
// once burst_idx has already advanced to 1.
|
|
if (BURST_LEN == 1) begin
|
|
ready <= 1'b1;
|
|
wait_cnt <= T_RP[CNTW-1:0] - 1'b1;
|
|
state <= S_PRECHARGE_WAIT;
|
|
end else begin
|
|
burst_idx <= burst_idx + 1'b1;
|
|
state <= S_BURST_READ;
|
|
end
|
|
end
|
|
end
|
|
|
|
S_BURST_READ: begin
|
|
// burst_idx's own width (BURST_IDXW=clog2(BURST_
|
|
// LEN)) can only ever represent 0..BURST_LEN-1 --
|
|
// capture therefore happens unconditionally every
|
|
// cycle spent in this state (an explicit "<
|
|
// BURST_LEN" guard here would always be true by
|
|
// construction and was removed as dead logic).
|
|
rdata[burst_idx*16 +: 16] <= sdram_dq;
|
|
if (burst_idx == BURST_LEN[BURST_IDXW-1:0] - 1'b1) begin
|
|
ready <= 1'b1;
|
|
// auto-precharge already running internally;
|
|
// enforce tRP before the next ACTIVATE.
|
|
wait_cnt <= T_RP[CNTW-1:0] - 1'b1;
|
|
state <= S_PRECHARGE_WAIT;
|
|
end else begin
|
|
burst_idx <= burst_idx + 1'b1;
|
|
end
|
|
end
|
|
|
|
S_BURST_WRITE: begin
|
|
if (burst_idx < BURST_LEN[BURST_IDXW-1:0] - 1'b1) begin
|
|
burst_idx <= burst_idx + 1'b1;
|
|
dq_out_en <= 1'b1;
|
|
dq_out <= wdata_reg[(burst_idx+1'b1)*16 +: 16];
|
|
sdram_dqm <= wmask_reg[(burst_idx+1'b1)*2 +: 2];
|
|
end else begin
|
|
ready <= 1'b1;
|
|
wait_cnt <= T_RP[CNTW-1:0] + 1'b1; // tWR folded in conservatively
|
|
state <= S_PRECHARGE_WAIT;
|
|
end
|
|
end
|
|
|
|
S_PRECHARGE_WAIT: begin
|
|
if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
|
|
else state <= S_IDLE;
|
|
end
|
|
|
|
default: state <= S_IDLE;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
endmodule
|