105 lines
2.8 KiB
Verilog
105 lines
2.8 KiB
Verilog
module memory_model #(
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parameter ADDR_WIDTH = 22,
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parameter DATA_WIDTH = 16,
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parameter DEPTH = 4096,
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parameter READ_LATENCY = 2
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)(
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input wire clk,
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input wire rst,
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input wire req,
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input wire wr,
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input wire [ADDR_WIDTH-1:0] addr,
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input wire [DATA_WIDTH-1:0] wdata,
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output reg [DATA_WIDTH-1:0] rdata,
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output reg ready
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);
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reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
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reg busy;
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reg pending_wr;
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reg [ADDR_WIDTH-1:0] pending_addr;
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reg [DATA_WIDTH-1:0] pending_wdata;
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integer delay_count;
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integer i;
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always @(posedge clk) begin
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if (rst) begin
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rdata <= {DATA_WIDTH{1'b0}};
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ready <= 1'b0;
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busy <= 1'b0;
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pending_wr <= 1'b0;
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pending_addr <= {ADDR_WIDTH{1'b0}};
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pending_wdata <= {DATA_WIDTH{1'b0}};
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delay_count <= 0;
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for (i = 0; i < DEPTH; i = i + 1)
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mem[i] <= {DATA_WIDTH{1'b0}};
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end else begin
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// ready is a one-cycle pulse
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ready <= 1'b0;
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// ----------------------------------------------------
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// Accept request
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// ----------------------------------------------------
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if (!busy) begin
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if (req) begin
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busy <= 1'b1;
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pending_wr <= wr;
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pending_addr <= addr;
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pending_wdata <= wdata;
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delay_count <= READ_LATENCY;
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end
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end else begin
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// ------------------------------------------------
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// Wait
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// ------------------------------------------------
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if (delay_count > 0) begin
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delay_count <= delay_count - 1;
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end else begin
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// --------------------------------------------
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// Complete transaction
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// --------------------------------------------
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if (pending_wr) begin
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// WRITE
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if (pending_addr < DEPTH)
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mem[pending_addr] <= pending_wdata;
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end else begin
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// READ
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if (pending_addr < DEPTH)
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rdata <= mem[pending_addr];
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else
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rdata <= {DATA_WIDTH{1'b0}};
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end
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ready <= 1'b1;
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busy <= 1'b0;
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end
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end
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end
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end
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endmodule |