94 lines
2.4 KiB
Verilog
94 lines
2.4 KiB
Verilog
module memory_interface #(
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parameter ADDR_WIDTH = 22,
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parameter DATA_WIDTH = 16
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)(
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input wire clk,
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input wire rst,
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input wire req,
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input wire wr,
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input wire [ADDR_WIDTH-1:0] addr,
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input wire [DATA_WIDTH-1:0] wdata,
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input wire lb_n,
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input wire ub_n,
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output reg [DATA_WIDTH-1:0] rdata,
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output reg ready,
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output reg mem_req,
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output reg mem_wr,
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output reg [ADDR_WIDTH-1:0] mem_addr,
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output reg [DATA_WIDTH-1:0] mem_wdata,
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output reg mem_lb_n,
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output reg mem_ub_n,
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input wire [DATA_WIDTH-1:0] mem_rdata,
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input wire mem_ready
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);
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localparam STATE_IDLE = 2'd0;
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localparam STATE_WAIT = 2'd1;
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reg [1:0] state;
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always @(posedge clk) begin
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if (rst) begin
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state <= STATE_IDLE;
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rdata <= {DATA_WIDTH{1'b0}};
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ready <= 1'b0;
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mem_lb_n <= 1'b1;
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mem_ub_n <= 1'b1;
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mem_req <= 1'b0;
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mem_wr <= 1'b0;
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mem_addr <= {ADDR_WIDTH{1'b0}};
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mem_wdata <= {DATA_WIDTH{1'b0}};
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end else begin
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// Default: pulses
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ready <= 1'b0;
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mem_req <= 1'b0;
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case (state)
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STATE_IDLE: begin
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if (req) begin
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// Latch transaction
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mem_wr <= wr;
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mem_addr <= addr;
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mem_wdata <= wdata;
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mem_lb_n <= lb_n;
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mem_ub_n <= ub_n;
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// Issue exactly one-cycle request
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mem_req <= 1'b1;
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state <= STATE_WAIT;
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end
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end
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STATE_WAIT: begin
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// Wait for memory completion
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if (mem_ready) begin
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if (!mem_wr)
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rdata <= mem_rdata;
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ready <= 1'b1;
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state <= STATE_IDLE;
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end
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end
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default: begin
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state <= STATE_IDLE;
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end
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endcase
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end
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end
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endmodule |