FPGA-Neural

Files

T

micheleandClaude Sonnet 5 80c89fa10d exp: real end-to-end weight-reuse integration with neural_processor.v (EXP-0058)

New tb_neural_processor_layer_reuse.v wires the real SDRAM controller,
layer_prefetch_ctrl.v and layer_weight_buffer.v into a real
neural_processor.v compute engine: one resident filter is fetched once
and reused across 8 independent jobs per layer, verified bit-exact
against an independent golden dot-product model (32/32 PASS).

Also found and fixed a real testbench-vs-DUT scheduling race present in
tb_layer_prefetch_ctrl.v (and hardened in the new file): clearing a
one-cycle control pulse on the very next clock edge lands the clear in
the same active-region pass as the edge a receiving module's own
synchronous logic reads it at, so the pulse can be silently missed
depending on implementation-defined process ordering. This had been
silently preventing tb_layer_prefetch_ctrl.v's own claimed 8192/8192
result from ever actually being observed; fixed by holding the pulse
past the edge with a real time delay before clearing, and the
8192/8192 result is now genuinely reproducible (5/5 consecutive runs).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-16 14:26:09 +02:00

tb_benchmark_suite.v

test(v2): final benchmark campaign - real end-to-end characterization (EXP-0014)

2026-09-05 19:58:30 +02:00

tb_buffers.v

feat(v2): M3 activation/weight/result buffers, real BRAM mapping

2026-09-05 14:19:11 +02:00

tb_dataflow_core.v

perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)

2026-09-05 20:59:14 +02:00

tb_dependency_manager_fast.v

exp: N=16 timing closure fixed (EXP-0056), weight-reuse gives real 7.16x memory speedup without DDR3 (EXP-0057)