micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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"direction": "input",
|
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"bits": [ 35 ]
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},
|
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"A16": {
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"direction": "input",
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},
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"A15": {
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"direction": "input",
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},
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"A14": {
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"direction": "input",
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},
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"direction": "input",
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},
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"A12": {
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"direction": "input",
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"A11": {
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"direction": "input",
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"direction": "input",
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"direction": "input",
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"A6": {
|
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"direction": "input",
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|
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"direction": "input",
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"direction": "input",
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"direction": "input",
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"direction": "input",
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
|
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|
|
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|
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|
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|
|
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
"bits": [ 197 ]
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},
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"MA34": {
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"direction": "input",
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"bits": [ 198 ]
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},
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"MA33": {
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"direction": "input",
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"bits": [ 199 ]
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},
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"MA32": {
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"direction": "input",
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"bits": [ 200 ]
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},
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"MA31": {
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"direction": "input",
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"bits": [ 201 ]
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},
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"MA30": {
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"direction": "input",
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"bits": [ 202 ]
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},
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"MA29": {
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"direction": "input",
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"bits": [ 203 ]
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},
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"MA28": {
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"direction": "input",
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"bits": [ 204 ]
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},
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"MA27": {
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"direction": "input",
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"bits": [ 205 ]
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},
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"MA26": {
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"direction": "input",
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"bits": [ 206 ]
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},
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"MA25": {
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"direction": "input",
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"bits": [ 207 ]
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},
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"MA24": {
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"direction": "input",
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"bits": [ 208 ]
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},
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"MA23": {
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"direction": "input",
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"bits": [ 209 ]
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},
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"MA22": {
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"direction": "input",
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"bits": [ 210 ]
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},
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"MA21": {
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"direction": "input",
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"bits": [ 211 ]
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},
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"MA20": {
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"direction": "input",
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"bits": [ 212 ]
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},
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"MA19": {
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"direction": "input",
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"bits": [ 213 ]
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},
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"MA18": {
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"direction": "input",
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"bits": [ 214 ]
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},
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"MA17": {
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"direction": "input",
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"bits": [ 215 ]
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},
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"MA16": {
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"direction": "input",
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"bits": [ 216 ]
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},
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"MA15": {
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"direction": "input",
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"bits": [ 217 ]
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},
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"MA14": {
|
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"direction": "input",
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"bits": [ 218 ]
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},
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"MA13": {
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"direction": "input",
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},
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"MA12": {
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"direction": "input",
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"MA11": {
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"direction": "input",
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"direction": "input",
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|
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"direction": "input",
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|
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"direction": "input",
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|
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|
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|
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"direction": "input",
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|
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|
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"direction": "input",
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|
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"direction": "input",
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|
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|
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|
|
"direction": "input",
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|
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|
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|
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"direction": "input",
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|
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|
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|
|
"direction": "input",
|
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|
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|
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|
|
"direction": "input",
|
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"bits": [ 231 ]
|
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|
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"MA0": {
|
|
"direction": "input",
|
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|
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|
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|
|
"direction": "input",
|
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|
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|
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"MB34": {
|
|
"direction": "input",
|
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|
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|
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"MB33": {
|
|
"direction": "input",
|
|
"bits": [ 235 ]
|
|
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|
|
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|
|
"direction": "input",
|
|
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|
|
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|
|
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|
|
"direction": "input",
|
|
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|
|
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|
|
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|
|
"direction": "input",
|
|
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|
|
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|
|
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|
|
"direction": "input",
|
|
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|
|
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|
|
"MB28": {
|
|
"direction": "input",
|
|
"bits": [ 240 ]
|
|
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|
|
"MB27": {
|
|
"direction": "input",
|
|
"bits": [ 241 ]
|
|
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|
|
"MB26": {
|
|
"direction": "input",
|
|
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|
|
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|
|
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|
|
"direction": "input",
|
|
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|
|
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|
|
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|
|
"direction": "input",
|
|
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|
|
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|
|
"MB23": {
|
|
"direction": "input",
|
|
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|
|
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|
|
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|
|
"direction": "input",
|
|
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|
|
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|
|
"MB21": {
|
|
"direction": "input",
|
|
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|
|
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|
|
"MB20": {
|
|
"direction": "input",
|
|
"bits": [ 248 ]
|
|
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|
|
"MB19": {
|
|
"direction": "input",
|
|
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|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 250 ]
|
|
},
|
|
"MB17": {
|
|
"direction": "input",
|
|
"bits": [ 251 ]
|
|
},
|
|
"MB16": {
|
|
"direction": "input",
|
|
"bits": [ 252 ]
|
|
},
|
|
"MB15": {
|
|
"direction": "input",
|
|
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|
|
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|
|
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|
|
"direction": "input",
|
|
"bits": [ 254 ]
|
|
},
|
|
"MB13": {
|
|
"direction": "input",
|
|
"bits": [ 255 ]
|
|
},
|
|
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|
|
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|
|
"bits": [ 256 ]
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
"R35": {
|
|
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|
|
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|
|
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|
|
"R34": {
|
|
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|
|
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|
|
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|
|
"R33": {
|
|
"direction": "output",
|
|
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|
|
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|
|
"R32": {
|
|
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|
|
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|
|
},
|
|
"R31": {
|
|
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|
|
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|
|
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|
|
"R30": {
|
|
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|
|
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|
|
},
|
|
"R29": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
"R28": {
|
|
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|
|
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|
|
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|
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"bits": [ 6 ]
|
|
},
|
|
"DCSOUT": {
|
|
"direction": "output",
|
|
"bits": [ 7 ]
|
|
}
|
|
},
|
|
"cells": {
|
|
},
|
|
"netnames": {
|
|
"CLK0": {
|
|
"hide_name": 0,
|
|
"bits": [ 3 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1035.11-1035.15"
|
|
}
|
|
},
|
|
"CLK1": {
|
|
"hide_name": 0,
|
|
"bits": [ 2 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1034.11-1034.15"
|
|
}
|
|
},
|
|
"DCSOUT": {
|
|
"hide_name": 0,
|
|
"bits": [ 7 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1039.12-1039.18"
|
|
}
|
|
},
|
|
"MODESEL": {
|
|
"hide_name": 0,
|
|
"bits": [ 6 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1038.11-1038.18"
|
|
}
|
|
},
|
|
"SEL0": {
|
|
"hide_name": 0,
|
|
"bits": [ 5 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1037.11-1037.15"
|
|
}
|
|
},
|
|
"SEL1": {
|
|
"hide_name": 0,
|
|
"bits": [ 4 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1036.11-1036.15"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"DCUA": {
|
|
"attributes": {
|
|
"keep": "00000000000000000000000000000001",
|
|
"blackbox": "00000000000000000000000000000001",
|
|
"cells_not_processed": "00000000000000000000000000000001",
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1456.1-2032.10"
|
|
},
|
|
"parameter_default_values": {
|
|
"CH0_AUTO_CALIB_EN": "DONTCARE",
|
|
"CH0_AUTO_FACQ_EN": "DONTCARE",
|
|
"CH0_BAND_THRESHOLD": "DONTCARE",
|
|
"CH0_CALIB_CK_MODE": "DONTCARE",
|
|
"CH0_CC_MATCH_1": "DONTCARE",
|
|
"CH0_CC_MATCH_2": "DONTCARE",
|
|
"CH0_CC_MATCH_3": "DONTCARE",
|
|
"CH0_CC_MATCH_4": "DONTCARE",
|
|
"CH0_CDR_CNT4SEL": "DONTCARE",
|
|
"CH0_CDR_CNT8SEL": "DONTCARE",
|
|
"CH0_CDR_MAX_RATE": "DONTCARE",
|
|
"CH0_CTC_BYPASS": "DONTCARE",
|
|
"CH0_DCOATDCFG": "DONTCARE",
|
|
"CH0_DCOATDDLY": "DONTCARE",
|
|
"CH0_DCOBYPSATD": "DONTCARE",
|
|
"CH0_DCOCALDIV": "DONTCARE",
|
|
"CH0_DCOCTLGI": "DONTCARE",
|
|
"CH0_DCODISBDAVOID": "DONTCARE",
|
|
"CH0_DCOFLTDAC": "DONTCARE",
|
|
"CH0_DCOFTNRG": "DONTCARE",
|
|
"CH0_DCOIOSTUNE": "DONTCARE",
|
|
"CH0_DCOITUNE": "DONTCARE",
|
|
"CH0_DCOITUNE4LSB": "DONTCARE",
|
|
"CH0_DCOIUPDNX2": "DONTCARE",
|
|
"CH0_DCONUOFLSB": "DONTCARE",
|
|
"CH0_DCOSCALEI": "DONTCARE",
|
|
"CH0_DCOSTARTVAL": "DONTCARE",
|
|
"CH0_DCOSTEP": "DONTCARE",
|
|
"CH0_DEC_BYPASS": "DONTCARE",
|
|
"CH0_ENABLE_CG_ALIGN": "DONTCARE",
|
|
"CH0_ENC_BYPASS": "DONTCARE",
|
|
"CH0_FF_RX_F_CLK_DIS": "DONTCARE",
|
|
"CH0_FF_RX_H_CLK_EN": "DONTCARE",
|
|
"CH0_FF_TX_F_CLK_DIS": "DONTCARE",
|
|
"CH0_FF_TX_H_CLK_EN": "DONTCARE",
|
|
"CH0_GE_AN_ENABLE": "DONTCARE",
|
|
"CH0_INVERT_RX": "DONTCARE",
|
|
"CH0_INVERT_TX": "DONTCARE",
|
|
"CH0_LDR_CORE2TX_SEL": "DONTCARE",
|
|
"CH0_LDR_RX2CORE_SEL": "DONTCARE",
|
|
"CH0_LEQ_OFFSET_SEL": "DONTCARE",
|
|
"CH0_LEQ_OFFSET_TRIM": "DONTCARE",
|
|
"CH0_LSM_DISABLE": "DONTCARE",
|
|
"CH0_MATCH_2_ENABLE": "DONTCARE",
|
|
"CH0_MATCH_4_ENABLE": "DONTCARE",
|
|
"CH0_MIN_IPG_CNT": "DONTCARE",
|
|
"CH0_PCIE_EI_EN": "DONTCARE",
|
|
"CH0_PCIE_MODE": "DONTCARE",
|
|
"CH0_PCS_DET_TIME_SEL": "DONTCARE",
|
|
"CH0_PDEN_SEL": "DONTCARE",
|
|
"CH0_PRBS_ENABLE": "DONTCARE",
|
|
"CH0_PRBS_LOCK": "DONTCARE",
|
|
"CH0_PRBS_SELECTION": "DONTCARE",
|
|
"CH0_PROTOCOL": "DONTCARE",
|
|
"CH0_RATE_MODE_RX": "DONTCARE",
|
|
"CH0_RATE_MODE_TX": "DONTCARE",
|
|
"CH0_RCV_DCC_EN": "DONTCARE",
|
|
"CH0_REG_BAND_OFFSET": "DONTCARE",
|
|
"CH0_REG_BAND_SEL": "DONTCARE",
|
|
"CH0_REG_IDAC_EN": "DONTCARE",
|
|
"CH0_REG_IDAC_SEL": "DONTCARE",
|
|
"CH0_REQ_EN": "DONTCARE",
|
|
"CH0_REQ_LVL_SET": "DONTCARE",
|
|
"CH0_RIO_MODE": "DONTCARE",
|
|
"CH0_RLOS_SEL": "DONTCARE",
|
|
"CH0_RPWDNB": "DONTCARE",
|
|
"CH0_RTERM_RX": "DONTCARE",
|
|
"CH0_RTERM_TX": "DONTCARE",
|
|
"CH0_RXIN_CM": "DONTCARE",
|
|
"CH0_RXTERM_CM": "DONTCARE",
|
|
"CH0_RX_DCO_CK_DIV": "DONTCARE",
|
|
"CH0_RX_DIV11_SEL": "DONTCARE",
|
|
"CH0_RX_GEAR_BYPASS": "DONTCARE",
|
|
"CH0_RX_GEAR_MODE": "DONTCARE",
|
|
"CH0_RX_LOS_CEQ": "DONTCARE",
|
|
"CH0_RX_LOS_EN": "DONTCARE",
|
|
"CH0_RX_LOS_HYST_EN": "DONTCARE",
|
|
"CH0_RX_LOS_LVL": "DONTCARE",
|
|
"CH0_RX_RATE_SEL": "DONTCARE",
|
|
"CH0_RX_SB_BYPASS": "DONTCARE",
|
|
"CH0_SB_BYPASS": "DONTCARE",
|
|
"CH0_SEL_SD_RX_CLK": "DONTCARE",
|
|
"CH0_TDRV_DAT_SEL": "DONTCARE",
|
|
"CH0_TDRV_POST_EN": "DONTCARE",
|
|
"CH0_TDRV_PRE_EN": "DONTCARE",
|
|
"CH0_TDRV_SLICE0_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE0_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE1_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE1_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE2_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE2_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE3_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE3_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE4_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE4_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE5_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE5_SEL": "DONTCARE",
|
|
"CH0_TPWDNB": "DONTCARE",
|
|
"CH0_TXAMPLITUDE": "DONTCARE",
|
|
"CH0_TXDEPOST": "DONTCARE",
|
|
"CH0_TXDEPRE": "DONTCARE",
|
|
"CH0_TX_CM_SEL": "DONTCARE",
|
|
"CH0_TX_DIV11_SEL": "DONTCARE",
|
|
"CH0_TX_GEAR_BYPASS": "DONTCARE",
|
|
"CH0_TX_GEAR_MODE": "DONTCARE",
|
|
"CH0_TX_POST_SIGN": "DONTCARE",
|
|
"CH0_TX_PRE_SIGN": "DONTCARE",
|
|
"CH0_UC_MODE": "DONTCARE",
|
|
"CH0_UDF_COMMA_A": "DONTCARE",
|
|
"CH0_UDF_COMMA_B": "DONTCARE",
|
|
"CH0_UDF_COMMA_MASK": "DONTCARE",
|
|
"CH0_WA_BYPASS": "DONTCARE",
|
|
"CH0_WA_MODE": "DONTCARE",
|
|
"CH1_AUTO_CALIB_EN": "DONTCARE",
|
|
"CH1_AUTO_FACQ_EN": "DONTCARE",
|
|
"CH1_BAND_THRESHOLD": "DONTCARE",
|
|
"CH1_CALIB_CK_MODE": "DONTCARE",
|
|
"CH1_CC_MATCH_1": "DONTCARE",
|
|
"CH1_CC_MATCH_2": "DONTCARE",
|
|
"CH1_CC_MATCH_3": "DONTCARE",
|
|
"CH1_CC_MATCH_4": "DONTCARE",
|
|
"CH1_CDR_CNT4SEL": "DONTCARE",
|
|
"CH1_CDR_CNT8SEL": "DONTCARE",
|
|
"CH1_CDR_MAX_RATE": "DONTCARE",
|
|
"CH1_CTC_BYPASS": "DONTCARE",
|
|
"CH1_DCOATDCFG": "DONTCARE",
|
|
"CH1_DCOATDDLY": "DONTCARE",
|
|
"CH1_DCOBYPSATD": "DONTCARE",
|
|
"CH1_DCOCALDIV": "DONTCARE",
|
|
"CH1_DCOCTLGI": "DONTCARE",
|
|
"CH1_DCODISBDAVOID": "DONTCARE",
|
|
"CH1_DCOFLTDAC": "DONTCARE",
|
|
"CH1_DCOFTNRG": "DONTCARE",
|
|
"CH1_DCOIOSTUNE": "DONTCARE",
|
|
"CH1_DCOITUNE": "DONTCARE",
|
|
"CH1_DCOITUNE4LSB": "DONTCARE",
|
|
"CH1_DCOIUPDNX2": "DONTCARE",
|
|
"CH1_DCONUOFLSB": "DONTCARE",
|
|
"CH1_DCOSCALEI": "DONTCARE",
|
|
"CH1_DCOSTARTVAL": "DONTCARE",
|
|
"CH1_DCOSTEP": "DONTCARE",
|
|
"CH1_DEC_BYPASS": "DONTCARE",
|
|
"CH1_ENABLE_CG_ALIGN": "DONTCARE",
|
|
"CH1_ENC_BYPASS": "DONTCARE",
|
|
"CH1_FF_RX_F_CLK_DIS": "DONTCARE",
|
|
"CH1_FF_RX_H_CLK_EN": "DONTCARE",
|
|
"CH1_FF_TX_F_CLK_DIS": "DONTCARE",
|
|
"CH1_FF_TX_H_CLK_EN": "DONTCARE",
|
|
"CH1_GE_AN_ENABLE": "DONTCARE",
|
|
"CH1_INVERT_RX": "DONTCARE",
|
|
"CH1_INVERT_TX": "DONTCARE",
|
|
"CH1_LDR_CORE2TX_SEL": "DONTCARE",
|
|
"CH1_LDR_RX2CORE_SEL": "DONTCARE",
|
|
"CH1_LEQ_OFFSET_SEL": "DONTCARE",
|
|
"CH1_LEQ_OFFSET_TRIM": "DONTCARE",
|
|
"CH1_LSM_DISABLE": "DONTCARE",
|
|
"CH1_MATCH_2_ENABLE": "DONTCARE",
|
|
"CH1_MATCH_4_ENABLE": "DONTCARE",
|
|
"CH1_MIN_IPG_CNT": "DONTCARE",
|
|
"CH1_PCIE_EI_EN": "DONTCARE",
|
|
"CH1_PCIE_MODE": "DONTCARE",
|
|
"CH1_PCS_DET_TIME_SEL": "DONTCARE",
|
|
"CH1_PDEN_SEL": "DONTCARE",
|
|
"CH1_PRBS_ENABLE": "DONTCARE",
|
|
"CH1_PRBS_LOCK": "DONTCARE",
|
|
"CH1_PRBS_SELECTION": "DONTCARE",
|
|
"CH1_PROTOCOL": "DONTCARE",
|
|
"CH1_RATE_MODE_RX": "DONTCARE",
|
|
"CH1_RATE_MODE_TX": "DONTCARE",
|
|
"CH1_RCV_DCC_EN": "DONTCARE",
|
|
"CH1_REG_BAND_OFFSET": "DONTCARE",
|
|
"CH1_REG_BAND_SEL": "DONTCARE",
|
|
"CH1_REG_IDAC_EN": "DONTCARE",
|
|
"CH1_REG_IDAC_SEL": "DONTCARE",
|
|
"CH1_REQ_EN": "DONTCARE",
|
|
"CH1_REQ_LVL_SET": "DONTCARE",
|
|
"CH1_RIO_MODE": "DONTCARE",
|
|
"CH1_RLOS_SEL": "DONTCARE",
|
|
"CH1_RPWDNB": "DONTCARE",
|
|
"CH1_RTERM_RX": "DONTCARE",
|
|
"CH1_RTERM_TX": "DONTCARE",
|
|
"CH1_RXIN_CM": "DONTCARE",
|
|
"CH1_RXTERM_CM": "DONTCARE",
|
|
"CH1_RX_DCO_CK_DIV": "DONTCARE",
|
|
"CH1_RX_DIV11_SEL": "DONTCARE",
|
|
"CH1_RX_GEAR_BYPASS": "DONTCARE",
|
|
"CH1_RX_GEAR_MODE": "DONTCARE",
|
|
"CH1_RX_LOS_CEQ": "DONTCARE",
|
|
"CH1_RX_LOS_EN": "DONTCARE",
|
|
"CH1_RX_LOS_HYST_EN": "DONTCARE",
|
|
"CH1_RX_LOS_LVL": "DONTCARE",
|
|
"CH1_RX_RATE_SEL": "DONTCARE",
|
|
"CH1_RX_SB_BYPASS": "DONTCARE",
|
|
"CH1_SB_BYPASS": "DONTCARE",
|
|
"CH1_SEL_SD_RX_CLK": "DONTCARE",
|
|
"CH1_TDRV_DAT_SEL": "DONTCARE",
|
|
"CH1_TDRV_POST_EN": "DONTCARE",
|
|
"CH1_TDRV_PRE_EN": "DONTCARE",
|
|
"CH1_TDRV_SLICE0_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE0_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE1_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE1_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE2_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE2_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE3_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE3_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE4_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE4_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE5_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE5_SEL": "DONTCARE",
|
|
"CH1_TPWDNB": "DONTCARE",
|
|
"CH1_TXAMPLITUDE": "DONTCARE",
|
|
"CH1_TXDEPOST": "DONTCARE",
|
|
"CH1_TXDEPRE": "DONTCARE",
|
|
"CH1_TX_CM_SEL": "DONTCARE",
|
|
"CH1_TX_DIV11_SEL": "DONTCARE",
|
|
"CH1_TX_GEAR_BYPASS": "DONTCARE",
|
|
"CH1_TX_GEAR_MODE": "DONTCARE",
|
|
"CH1_TX_POST_SIGN": "DONTCARE",
|
|
"CH1_TX_PRE_SIGN": "DONTCARE",
|
|
"CH1_UC_MODE": "DONTCARE",
|
|
"CH1_UDF_COMMA_A": "DONTCARE",
|
|
"CH1_UDF_COMMA_B": "DONTCARE",
|
|
"CH1_UDF_COMMA_MASK": "DONTCARE",
|
|
"CH1_WA_BYPASS": "DONTCARE",
|
|
"CH1_WA_MODE": "DONTCARE",
|
|
"D_BITCLK_FROM_ND_EN": "DONTCARE",
|
|
"D_BITCLK_LOCAL_EN": "DONTCARE",
|
|
"D_BITCLK_ND_EN": "DONTCARE",
|
|
"D_BUS8BIT_SEL": "DONTCARE",
|
|
"D_CDR_LOL_SET": "DONTCARE",
|
|
"D_CMUSETBIASI": "DONTCARE",
|
|
"D_CMUSETI4CPP": "DONTCARE",
|
|
"D_CMUSETI4CPZ": "DONTCARE",
|
|
"D_CMUSETI4VCO": "DONTCARE",
|
|
"D_CMUSETICP4P": "DONTCARE",
|
|
"D_CMUSETICP4Z": "DONTCARE",
|
|
"D_CMUSETINITVCT": "DONTCARE",
|
|
"D_CMUSETISCL4VCO": "DONTCARE",
|
|
"D_CMUSETP1GM": "DONTCARE",
|
|
"D_CMUSETP2AGM": "DONTCARE",
|
|
"D_CMUSETZGM": "DONTCARE",
|
|
"D_DCO_CALIB_TIME_SEL": "DONTCARE",
|
|
"D_HIGH_MARK": "DONTCARE",
|
|
"D_IB_PWDNB": "DONTCARE",
|
|
"D_ISETLOS": "DONTCARE",
|
|
"D_LOW_MARK": "DONTCARE",
|
|
"D_MACROPDB": "DONTCARE",
|
|
"D_PD_ISET": "DONTCARE",
|
|
"D_PLL_LOL_SET": "DONTCARE",
|
|
"D_REFCK_MODE": "DONTCARE",
|
|
"D_REQ_ISET": "DONTCARE",
|
|
"D_RG_EN": "DONTCARE",
|
|
"D_RG_SET": "DONTCARE",
|
|
"D_SETICONST_AUX": "DONTCARE",
|
|
"D_SETICONST_CH": "DONTCARE",
|
|
"D_SETIRPOLY_AUX": "DONTCARE",
|
|
"D_SETIRPOLY_CH": "DONTCARE",
|
|
"D_SETPLLRC": "DONTCARE",
|
|
"D_SYNC_LOCAL_EN": "DONTCARE",
|
|
"D_SYNC_ND_EN": "DONTCARE",
|
|
"D_TXPLL_PWDNB": "DONTCARE",
|
|
"D_TX_MAX_RATE": "DONTCARE",
|
|
"D_TX_VCO_CK_DIV": "DONTCARE",
|
|
"D_XGE_MODE": "DONTCARE"
|
|
},
|
|
"ports": {
|
|
"CH0_HDINP": {
|
|
"direction": "input",
|
|
"bits": [ 2 ]
|
|
},
|
|
"CH1_HDINP": {
|
|
"direction": "input",
|
|
"bits": [ 3 ]
|
|
},
|
|
"CH0_HDINN": {
|
|
"direction": "input",
|
|
"bits": [ 4 ]
|
|
},
|
|
"CH1_HDINN": {
|
|
"direction": "input",
|
|
"bits": [ 5 ]
|
|
},
|
|
"D_TXBIT_CLKP_FROM_ND": {
|
|
"direction": "input",
|
|
"bits": [ 6 ]
|
|
},
|
|
"D_TXBIT_CLKN_FROM_ND": {
|
|
"direction": "input",
|
|
"bits": [ 7 ]
|
|
},
|
|
"D_SYNC_ND": {
|
|
"direction": "input",
|
|
"bits": [ 8 ]
|
|
},
|
|
"D_TXPLL_LOL_FROM_ND": {
|
|
"direction": "input",
|
|
"bits": [ 9 ]
|
|
},
|
|
"CH0_RX_REFCLK": {
|
|
"direction": "input",
|
|
"bits": [ 10 ]
|
|
},
|
|
"CH1_RX_REFCLK": {
|
|
"direction": "input",
|
|
"bits": [ 11 ]
|
|
},
|
|
"CH0_FF_RXI_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 12 ]
|
|
},
|
|
"CH1_FF_RXI_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 13 ]
|
|
},
|
|
"CH0_FF_TXI_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 14 ]
|
|
},
|
|
"CH1_FF_TXI_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 15 ]
|
|
},
|
|
"CH0_FF_EBRD_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 16 ]
|
|
},
|
|
"CH1_FF_EBRD_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 17 ]
|
|
},
|
|
"CH0_FF_TX_D_0": {
|
|
"direction": "input",
|
|
"bits": [ 18 ]
|
|
},
|
|
"CH1_FF_TX_D_0": {
|
|
"direction": "input",
|
|
"bits": [ 19 ]
|
|
},
|
|
"CH0_FF_TX_D_1": {
|
|
"direction": "input",
|
|
"bits": [ 20 ]
|
|
},
|
|
"CH1_FF_TX_D_1": {
|
|
"direction": "input",
|
|
"bits": [ 21 ]
|
|
},
|
|
"CH0_FF_TX_D_2": {
|
|
"direction": "input",
|
|
"bits": [ 22 ]
|
|
},
|
|
"CH1_FF_TX_D_2": {
|
|
"direction": "input",
|
|
"bits": [ 23 ]
|
|
},
|
|
"CH0_FF_TX_D_3": {
|
|
"direction": "input",
|
|
"bits": [ 24 ]
|
|
},
|
|
"CH1_FF_TX_D_3": {
|
|
"direction": "input",
|
|
"bits": [ 25 ]
|
|
},
|
|
"CH0_FF_TX_D_4": {
|
|
"direction": "input",
|
|
"bits": [ 26 ]
|
|
},
|
|
"CH1_FF_TX_D_4": {
|
|
"direction": "input",
|
|
"bits": [ 27 ]
|
|
},
|
|
"CH0_FF_TX_D_5": {
|
|
"direction": "input",
|
|
"bits": [ 28 ]
|
|
},
|
|
"CH1_FF_TX_D_5": {
|
|
"direction": "input",
|
|
"bits": [ 29 ]
|
|
},
|
|
"CH0_FF_TX_D_6": {
|
|
"direction": "input",
|
|
"bits": [ 30 ]
|
|
},
|
|
"CH1_FF_TX_D_6": {
|
|
"direction": "input",
|
|
"bits": [ 31 ]
|
|
},
|
|
"CH0_FF_TX_D_7": {
|
|
"direction": "input",
|
|
"bits": [ 32 ]
|
|
},
|
|
"CH1_FF_TX_D_7": {
|
|
"direction": "input",
|
|
"bits": [ 33 ]
|
|
},
|
|
"CH0_FF_TX_D_8": {
|
|
"direction": "input",
|
|
"bits": [ 34 ]
|
|
},
|
|
"CH1_FF_TX_D_8": {
|
|
"direction": "input",
|
|
"bits": [ 35 ]
|
|
},
|
|
"CH0_FF_TX_D_9": {
|
|
"direction": "input",
|
|
"bits": [ 36 ]
|
|
},
|
|
"CH1_FF_TX_D_9": {
|
|
"direction": "input",
|
|
"bits": [ 37 ]
|
|
},
|
|
"CH0_FF_TX_D_10": {
|
|
"direction": "input",
|
|
"bits": [ 38 ]
|
|
},
|
|
"CH1_FF_TX_D_10": {
|
|
"direction": "input",
|
|
"bits": [ 39 ]
|
|
},
|
|
"CH0_FF_TX_D_11": {
|
|
"direction": "input",
|
|
"bits": [ 40 ]
|
|
},
|
|
"CH1_FF_TX_D_11": {
|
|
"direction": "input",
|
|
"bits": [ 41 ]
|
|
},
|
|
"CH0_FF_TX_D_12": {
|
|
"direction": "input",
|
|
"bits": [ 42 ]
|
|
},
|
|
"CH1_FF_TX_D_12": {
|
|
"direction": "input",
|
|
"bits": [ 43 ]
|
|
},
|
|
"CH0_FF_TX_D_13": {
|
|
"direction": "input",
|
|
"bits": [ 44 ]
|
|
},
|
|
"CH1_FF_TX_D_13": {
|
|
"direction": "input",
|
|
"bits": [ 45 ]
|
|
},
|
|
"CH0_FF_TX_D_14": {
|
|
"direction": "input",
|
|
"bits": [ 46 ]
|
|
},
|
|
"CH1_FF_TX_D_14": {
|
|
"direction": "input",
|
|
"bits": [ 47 ]
|
|
},
|
|
"CH0_FF_TX_D_15": {
|
|
"direction": "input",
|
|
"bits": [ 48 ]
|
|
},
|
|
"CH1_FF_TX_D_15": {
|
|
"direction": "input",
|
|
"bits": [ 49 ]
|
|
},
|
|
"CH0_FF_TX_D_16": {
|
|
"direction": "input",
|
|
"bits": [ 50 ]
|
|
},
|
|
"CH1_FF_TX_D_16": {
|
|
"direction": "input",
|
|
"bits": [ 51 ]
|
|
},
|
|
"CH0_FF_TX_D_17": {
|
|
"direction": "input",
|
|
"bits": [ 52 ]
|
|
},
|
|
"CH1_FF_TX_D_17": {
|
|
"direction": "input",
|
|
"bits": [ 53 ]
|
|
},
|
|
"CH0_FF_TX_D_18": {
|
|
"direction": "input",
|
|
"bits": [ 54 ]
|
|
},
|
|
"CH1_FF_TX_D_18": {
|
|
"direction": "input",
|
|
"bits": [ 55 ]
|
|
},
|
|
"CH0_FF_TX_D_19": {
|
|
"direction": "input",
|
|
"bits": [ 56 ]
|
|
},
|
|
"CH1_FF_TX_D_19": {
|
|
"direction": "input",
|
|
"bits": [ 57 ]
|
|
},
|
|
"CH0_FF_TX_D_20": {
|
|
"direction": "input",
|
|
"bits": [ 58 ]
|
|
},
|
|
"CH1_FF_TX_D_20": {
|
|
"direction": "input",
|
|
"bits": [ 59 ]
|
|
},
|
|
"CH0_FF_TX_D_21": {
|
|
"direction": "input",
|
|
"bits": [ 60 ]
|
|
},
|
|
"CH1_FF_TX_D_21": {
|
|
"direction": "input",
|
|
"bits": [ 61 ]
|
|
},
|
|
"CH0_FF_TX_D_22": {
|
|
"direction": "input",
|
|
"bits": [ 62 ]
|
|
},
|
|
"CH1_FF_TX_D_22": {
|
|
"direction": "input",
|
|
"bits": [ 63 ]
|
|
},
|
|
"CH0_FF_TX_D_23": {
|
|
"direction": "input",
|
|
"bits": [ 64 ]
|
|
},
|
|
"CH1_FF_TX_D_23": {
|
|
"direction": "input",
|
|
"bits": [ 65 ]
|
|
},
|
|
"CH0_FFC_EI_EN": {
|
|
"direction": "input",
|
|
"bits": [ 66 ]
|
|
},
|
|
"CH1_FFC_EI_EN": {
|
|
"direction": "input",
|
|
"bits": [ 67 ]
|
|
},
|
|
"CH0_FFC_PCIE_DET_EN": {
|
|
"direction": "input",
|
|
"bits": [ 68 ]
|
|
},
|
|
"CH1_FFC_PCIE_DET_EN": {
|
|
"direction": "input",
|
|
"bits": [ 69 ]
|
|
},
|
|
"CH0_FFC_PCIE_CT": {
|
|
"direction": "input",
|
|
"bits": [ 70 ]
|
|
},
|
|
"CH1_FFC_PCIE_CT": {
|
|
"direction": "input",
|
|
"bits": [ 71 ]
|
|
},
|
|
"CH0_FFC_SB_INV_RX": {
|
|
"direction": "input",
|
|
"bits": [ 72 ]
|
|
},
|
|
"CH1_FFC_SB_INV_RX": {
|
|
"direction": "input",
|
|
"bits": [ 73 ]
|
|
},
|
|
"CH0_FFC_ENABLE_CGALIGN": {
|
|
"direction": "input",
|
|
"bits": [ 74 ]
|
|
},
|
|
"CH1_FFC_ENABLE_CGALIGN": {
|
|
"direction": "input",
|
|
"bits": [ 75 ]
|
|
},
|
|
"CH0_FFC_SIGNAL_DETECT": {
|
|
"direction": "input",
|
|
"bits": [ 76 ]
|
|
},
|
|
"CH1_FFC_SIGNAL_DETECT": {
|
|
"direction": "input",
|
|
"bits": [ 77 ]
|
|
},
|
|
"CH0_FFC_FB_LOOPBACK": {
|
|
"direction": "input",
|
|
"bits": [ 78 ]
|
|
},
|
|
"CH1_FFC_FB_LOOPBACK": {
|
|
"direction": "input",
|
|
"bits": [ 79 ]
|
|
},
|
|
"CH0_FFC_SB_PFIFO_LP": {
|
|
"direction": "input",
|
|
"bits": [ 80 ]
|
|
},
|
|
"CH1_FFC_SB_PFIFO_LP": {
|
|
"direction": "input",
|
|
"bits": [ 81 ]
|
|
},
|
|
"CH0_FFC_PFIFO_CLR": {
|
|
"direction": "input",
|
|
"bits": [ 82 ]
|
|
},
|
|
"CH1_FFC_PFIFO_CLR": {
|
|
"direction": "input",
|
|
"bits": [ 83 ]
|
|
},
|
|
"CH0_FFC_RATE_MODE_RX": {
|
|
"direction": "input",
|
|
"bits": [ 84 ]
|
|
},
|
|
"CH1_FFC_RATE_MODE_RX": {
|
|
"direction": "input",
|
|
"bits": [ 85 ]
|
|
},
|
|
"CH0_FFC_RATE_MODE_TX": {
|
|
"direction": "input",
|
|
"bits": [ 86 ]
|
|
},
|
|
"CH1_FFC_RATE_MODE_TX": {
|
|
"direction": "input",
|
|
"bits": [ 87 ]
|
|
},
|
|
"CH0_FFC_DIV11_MODE_RX": {
|
|
"direction": "input",
|
|
"bits": [ 88 ]
|
|
},
|
|
"CH1_FFC_DIV11_MODE_RX": {
|
|
"direction": "input",
|
|
"bits": [ 89 ]
|
|
},
|
|
"CH0_FFC_RX_GEAR_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 90 ]
|
|
},
|
|
"CH1_FFC_RX_GEAR_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 91 ]
|
|
},
|
|
"CH0_FFC_TX_GEAR_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 92 ]
|
|
},
|
|
"CH1_FFC_TX_GEAR_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 93 ]
|
|
},
|
|
"CH0_FFC_DIV11_MODE_TX": {
|
|
"direction": "input",
|
|
"bits": [ 94 ]
|
|
},
|
|
"CH1_FFC_DIV11_MODE_TX": {
|
|
"direction": "input",
|
|
"bits": [ 95 ]
|
|
},
|
|
"CH0_FFC_LDR_CORE2TX_EN": {
|
|
"direction": "input",
|
|
"bits": [ 96 ]
|
|
},
|
|
"CH1_FFC_LDR_CORE2TX_EN": {
|
|
"direction": "input",
|
|
"bits": [ 97 ]
|
|
},
|
|
"CH0_FFC_LANE_TX_RST": {
|
|
"direction": "input",
|
|
"bits": [ 98 ]
|
|
},
|
|
"CH1_FFC_LANE_TX_RST": {
|
|
"direction": "input",
|
|
"bits": [ 99 ]
|
|
},
|
|
"CH0_FFC_LANE_RX_RST": {
|
|
"direction": "input",
|
|
"bits": [ 100 ]
|
|
},
|
|
"CH1_FFC_LANE_RX_RST": {
|
|
"direction": "input",
|
|
"bits": [ 101 ]
|
|
},
|
|
"CH0_FFC_RRST": {
|
|
"direction": "input",
|
|
"bits": [ 102 ]
|
|
},
|
|
"CH1_FFC_RRST": {
|
|
"direction": "input",
|
|
"bits": [ 103 ]
|
|
},
|
|
"CH0_FFC_TXPWDNB": {
|
|
"direction": "input",
|
|
"bits": [ 104 ]
|
|
},
|
|
"CH1_FFC_TXPWDNB": {
|
|
"direction": "input",
|
|
"bits": [ 105 ]
|
|
},
|
|
"CH0_FFC_RXPWDNB": {
|
|
"direction": "input",
|
|
"bits": [ 106 ]
|
|
},
|
|
"CH1_FFC_RXPWDNB": {
|
|
"direction": "input",
|
|
"bits": [ 107 ]
|
|
},
|
|
"CH0_LDR_CORE2TX": {
|
|
"direction": "input",
|
|
"bits": [ 108 ]
|
|
},
|
|
"CH1_LDR_CORE2TX": {
|
|
"direction": "input",
|
|
"bits": [ 109 ]
|
|
},
|
|
"D_SCIWDATA0": {
|
|
"direction": "input",
|
|
"bits": [ 110 ]
|
|
},
|
|
"D_SCIWDATA1": {
|
|
"direction": "input",
|
|
"bits": [ 111 ]
|
|
},
|
|
"D_SCIWDATA2": {
|
|
"direction": "input",
|
|
"bits": [ 112 ]
|
|
},
|
|
"D_SCIWDATA3": {
|
|
"direction": "input",
|
|
"bits": [ 113 ]
|
|
},
|
|
"D_SCIWDATA4": {
|
|
"direction": "input",
|
|
"bits": [ 114 ]
|
|
},
|
|
"D_SCIWDATA5": {
|
|
"direction": "input",
|
|
"bits": [ 115 ]
|
|
},
|
|
"D_SCIWDATA6": {
|
|
"direction": "input",
|
|
"bits": [ 116 ]
|
|
},
|
|
"D_SCIWDATA7": {
|
|
"direction": "input",
|
|
"bits": [ 117 ]
|
|
},
|
|
"D_SCIADDR0": {
|
|
"direction": "input",
|
|
"bits": [ 118 ]
|
|
},
|
|
"D_SCIADDR1": {
|
|
"direction": "input",
|
|
"bits": [ 119 ]
|
|
},
|
|
"D_SCIADDR2": {
|
|
"direction": "input",
|
|
"bits": [ 120 ]
|
|
},
|
|
"D_SCIADDR3": {
|
|
"direction": "input",
|
|
"bits": [ 121 ]
|
|
},
|
|
"D_SCIADDR4": {
|
|
"direction": "input",
|
|
"bits": [ 122 ]
|
|
},
|
|
"D_SCIADDR5": {
|
|
"direction": "input",
|
|
"bits": [ 123 ]
|
|
},
|
|
"D_SCIENAUX": {
|
|
"direction": "input",
|
|
"bits": [ 124 ]
|
|
},
|
|
"D_SCISELAUX": {
|
|
"direction": "input",
|
|
"bits": [ 125 ]
|
|
},
|
|
"CH0_SCIEN": {
|
|
"direction": "input",
|
|
"bits": [ 126 ]
|
|
},
|
|
"CH1_SCIEN": {
|
|
"direction": "input",
|
|
"bits": [ 127 ]
|
|
},
|
|
"CH0_SCISEL": {
|
|
"direction": "input",
|
|
"bits": [ 128 ]
|
|
},
|
|
"CH1_SCISEL": {
|
|
"direction": "input",
|
|
"bits": [ 129 ]
|
|
},
|
|
"D_SCIRD": {
|
|
"direction": "input",
|
|
"bits": [ 130 ]
|
|
},
|
|
"D_SCIWSTN": {
|
|
"direction": "input",
|
|
"bits": [ 131 ]
|
|
},
|
|
"D_CYAWSTN": {
|
|
"direction": "input",
|
|
"bits": [ 132 ]
|
|
},
|
|
"D_FFC_SYNC_TOGGLE": {
|
|
"direction": "input",
|
|
"bits": [ 133 ]
|
|
},
|
|
"D_FFC_DUAL_RST": {
|
|
"direction": "input",
|
|
"bits": [ 134 ]
|
|
},
|
|
"D_FFC_MACRO_RST": {
|
|
"direction": "input",
|
|
"bits": [ 135 ]
|
|
},
|
|
"D_FFC_MACROPDB": {
|
|
"direction": "input",
|
|
"bits": [ 136 ]
|
|
},
|
|
"D_FFC_TRST": {
|
|
"direction": "input",
|
|
"bits": [ 137 ]
|
|
},
|
|
"CH0_FFC_CDR_EN_BITSLIP": {
|
|
"direction": "input",
|
|
"bits": [ 138 ]
|
|
},
|
|
"CH1_FFC_CDR_EN_BITSLIP": {
|
|
"direction": "input",
|
|
"bits": [ 139 ]
|
|
},
|
|
"D_SCAN_ENABLE": {
|
|
"direction": "input",
|
|
"bits": [ 140 ]
|
|
},
|
|
"D_SCAN_IN_0": {
|
|
"direction": "input",
|
|
"bits": [ 141 ]
|
|
},
|
|
"D_SCAN_IN_1": {
|
|
"direction": "input",
|
|
"bits": [ 142 ]
|
|
},
|
|
"D_SCAN_IN_2": {
|
|
"direction": "input",
|
|
"bits": [ 143 ]
|
|
},
|
|
"D_SCAN_IN_3": {
|
|
"direction": "input",
|
|
"bits": [ 144 ]
|
|
},
|
|
"D_SCAN_IN_4": {
|
|
"direction": "input",
|
|
"bits": [ 145 ]
|
|
},
|
|
"D_SCAN_IN_5": {
|
|
"direction": "input",
|
|
"bits": [ 146 ]
|
|
},
|
|
"D_SCAN_IN_6": {
|
|
"direction": "input",
|
|
"bits": [ 147 ]
|
|
},
|
|
"D_SCAN_IN_7": {
|
|
"direction": "input",
|
|
"bits": [ 148 ]
|
|
},
|
|
"D_SCAN_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 149 ]
|
|
},
|
|
"D_SCAN_RESET": {
|
|
"direction": "input",
|
|
"bits": [ 150 ]
|
|
},
|
|
"D_CIN0": {
|
|
"direction": "input",
|
|
"bits": [ 151 ]
|
|
},
|
|
"D_CIN1": {
|
|
"direction": "input",
|
|
"bits": [ 152 ]
|
|
},
|
|
"D_CIN2": {
|
|
"direction": "input",
|
|
"bits": [ 153 ]
|
|
},
|
|
"D_CIN3": {
|
|
"direction": "input",
|
|
"bits": [ 154 ]
|
|
},
|
|
"D_CIN4": {
|
|
"direction": "input",
|
|
"bits": [ 155 ]
|
|
},
|
|
"D_CIN5": {
|
|
"direction": "input",
|
|
"bits": [ 156 ]
|
|
},
|
|
"D_CIN6": {
|
|
"direction": "input",
|
|
"bits": [ 157 ]
|
|
},
|
|
"D_CIN7": {
|
|
"direction": "input",
|
|
"bits": [ 158 ]
|
|
},
|
|
"D_CIN8": {
|
|
"direction": "input",
|
|
"bits": [ 159 ]
|
|
},
|
|
"D_CIN9": {
|
|
"direction": "input",
|
|
"bits": [ 160 ]
|
|
},
|
|
"D_CIN10": {
|
|
"direction": "input",
|
|
"bits": [ 161 ]
|
|
},
|
|
"D_CIN11": {
|
|
"direction": "input",
|
|
"bits": [ 162 ]
|
|
},
|
|
"CH0_HDOUTP": {
|
|
"direction": "output",
|
|
"bits": [ 163 ]
|
|
},
|
|
"CH1_HDOUTP": {
|
|
"direction": "output",
|
|
"bits": [ 164 ]
|
|
},
|
|
"CH0_HDOUTN": {
|
|
"direction": "output",
|
|
"bits": [ 165 ]
|
|
},
|
|
"CH1_HDOUTN": {
|
|
"direction": "output",
|
|
"bits": [ 166 ]
|
|
},
|
|
"D_TXBIT_CLKP_TO_ND": {
|
|
"direction": "output",
|
|
"bits": [ 167 ]
|
|
},
|
|
"D_TXBIT_CLKN_TO_ND": {
|
|
"direction": "output",
|
|
"bits": [ 168 ]
|
|
},
|
|
"D_SYNC_PULSE2ND": {
|
|
"direction": "output",
|
|
"bits": [ 169 ]
|
|
},
|
|
"D_TXPLL_LOL_TO_ND": {
|
|
"direction": "output",
|
|
"bits": [ 170 ]
|
|
},
|
|
"CH0_FF_RX_F_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 171 ]
|
|
},
|
|
"CH1_FF_RX_F_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 172 ]
|
|
},
|
|
"CH0_FF_RX_H_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 173 ]
|
|
},
|
|
"CH1_FF_RX_H_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 174 ]
|
|
},
|
|
"CH0_FF_TX_F_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 175 ]
|
|
},
|
|
"CH1_FF_TX_F_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 176 ]
|
|
},
|
|
"CH0_FF_TX_H_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 177 ]
|
|
},
|
|
"CH1_FF_TX_H_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 178 ]
|
|
},
|
|
"CH0_FF_RX_PCLK": {
|
|
"direction": "output",
|
|
"bits": [ 179 ]
|
|
},
|
|
"CH1_FF_RX_PCLK": {
|
|
"direction": "output",
|
|
"bits": [ 180 ]
|
|
},
|
|
"CH0_FF_TX_PCLK": {
|
|
"direction": "output",
|
|
"bits": [ 181 ]
|
|
},
|
|
"CH1_FF_TX_PCLK": {
|
|
"direction": "output",
|
|
"bits": [ 182 ]
|
|
},
|
|
"CH0_FF_RX_D_0": {
|
|
"direction": "output",
|
|
"bits": [ 183 ]
|
|
},
|
|
"CH1_FF_RX_D_0": {
|
|
"direction": "output",
|
|
"bits": [ 184 ]
|
|
},
|
|
"CH0_FF_RX_D_1": {
|
|
"direction": "output",
|
|
"bits": [ 185 ]
|
|
},
|
|
"CH1_FF_RX_D_1": {
|
|
"direction": "output",
|
|
"bits": [ 186 ]
|
|
},
|
|
"CH0_FF_RX_D_2": {
|
|
"direction": "output",
|
|
"bits": [ 187 ]
|
|
},
|
|
"CH1_FF_RX_D_2": {
|
|
"direction": "output",
|
|
"bits": [ 188 ]
|
|
},
|
|
"CH0_FF_RX_D_3": {
|
|
"direction": "output",
|
|
"bits": [ 189 ]
|
|
},
|
|
"CH1_FF_RX_D_3": {
|
|
"direction": "output",
|
|
"bits": [ 190 ]
|
|
},
|
|
"CH0_FF_RX_D_4": {
|
|
"direction": "output",
|
|
"bits": [ 191 ]
|
|
},
|
|
"CH1_FF_RX_D_4": {
|
|
"direction": "output",
|
|
"bits": [ 192 ]
|
|
},
|
|
"CH0_FF_RX_D_5": {
|
|
"direction": "output",
|
|
"bits": [ 193 ]
|
|
},
|
|
"CH1_FF_RX_D_5": {
|
|
"direction": "output",
|
|
"bits": [ 194 ]
|
|
},
|
|
"CH0_FF_RX_D_6": {
|
|
"direction": "output",
|
|
"bits": [ 195 ]
|
|
},
|
|
"CH1_FF_RX_D_6": {
|
|
"direction": "output",
|
|
"bits": [ 196 ]
|
|
},
|
|
"CH0_FF_RX_D_7": {
|
|
"direction": "output",
|
|
"bits": [ 197 ]
|
|
},
|
|
"CH1_FF_RX_D_7": {
|
|
"direction": "output",
|
|
"bits": [ 198 ]
|
|
},
|
|
"CH0_FF_RX_D_8": {
|
|
"direction": "output",
|
|
"bits": [ 199 ]
|
|
},
|
|
"CH1_FF_RX_D_8": {
|
|
"direction": "output",
|
|
"bits": [ 200 ]
|
|
},
|
|
"CH0_FF_RX_D_9": {
|
|
"direction": "output",
|
|
"bits": [ 201 ]
|
|
},
|
|
"CH1_FF_RX_D_9": {
|
|
"direction": "output",
|
|
"bits": [ 202 ]
|
|
},
|
|
"CH0_FF_RX_D_10": {
|
|
"direction": "output",
|
|
"bits": [ 203 ]
|
|
},
|
|
"CH1_FF_RX_D_10": {
|
|
"direction": "output",
|
|
"bits": [ 204 ]
|
|
},
|
|
"CH0_FF_RX_D_11": {
|
|
"direction": "output",
|
|
"bits": [ 205 ]
|
|
},
|
|
"CH1_FF_RX_D_11": {
|
|
"direction": "output",
|
|
"bits": [ 206 ]
|
|
},
|
|
"CH0_FF_RX_D_12": {
|
|
"direction": "output",
|
|
"bits": [ 207 ]
|
|
},
|
|
"CH1_FF_RX_D_12": {
|
|
"direction": "output",
|
|
"bits": [ 208 ]
|
|
},
|
|
"CH0_FF_RX_D_13": {
|
|
"direction": "output",
|
|
"bits": [ 209 ]
|
|
},
|
|
"CH1_FF_RX_D_13": {
|
|
"direction": "output",
|
|
"bits": [ 210 ]
|
|
},
|
|
"CH0_FF_RX_D_14": {
|
|
"direction": "output",
|
|
"bits": [ 211 ]
|
|
},
|
|
"CH1_FF_RX_D_14": {
|
|
"direction": "output",
|
|
"bits": [ 212 ]
|
|
},
|
|
"CH0_FF_RX_D_15": {
|
|
"direction": "output",
|
|
"bits": [ 213 ]
|
|
},
|
|
"CH1_FF_RX_D_15": {
|
|
"direction": "output",
|
|
"bits": [ 214 ]
|
|
},
|
|
"CH0_FF_RX_D_16": {
|
|
"direction": "output",
|
|
"bits": [ 215 ]
|
|
},
|
|
"CH1_FF_RX_D_16": {
|
|
"direction": "output",
|
|
"bits": [ 216 ]
|
|
},
|
|
"CH0_FF_RX_D_17": {
|
|
"direction": "output",
|
|
"bits": [ 217 ]
|
|
},
|
|
"CH1_FF_RX_D_17": {
|
|
"direction": "output",
|
|
"bits": [ 218 ]
|
|
},
|
|
"CH0_FF_RX_D_18": {
|
|
"direction": "output",
|
|
"bits": [ 219 ]
|
|
},
|
|
"CH1_FF_RX_D_18": {
|
|
"direction": "output",
|
|
"bits": [ 220 ]
|
|
},
|
|
"CH0_FF_RX_D_19": {
|
|
"direction": "output",
|
|
"bits": [ 221 ]
|
|
},
|
|
"CH1_FF_RX_D_19": {
|
|
"direction": "output",
|
|
"bits": [ 222 ]
|
|
},
|
|
"CH0_FF_RX_D_20": {
|
|
"direction": "output",
|
|
"bits": [ 223 ]
|
|
},
|
|
"CH1_FF_RX_D_20": {
|
|
"direction": "output",
|
|
"bits": [ 224 ]
|
|
},
|
|
"CH0_FF_RX_D_21": {
|
|
"direction": "output",
|
|
"bits": [ 225 ]
|
|
},
|
|
"CH1_FF_RX_D_21": {
|
|
"direction": "output",
|
|
"bits": [ 226 ]
|
|
},
|
|
"CH0_FF_RX_D_22": {
|
|
"direction": "output",
|
|
"bits": [ 227 ]
|
|
},
|
|
"CH1_FF_RX_D_22": {
|
|
"direction": "output",
|
|
"bits": [ 228 ]
|
|
},
|
|
"CH0_FF_RX_D_23": {
|
|
"direction": "output",
|
|
"bits": [ 229 ]
|
|
},
|
|
"CH1_FF_RX_D_23": {
|
|
"direction": "output",
|
|
"bits": [ 230 ]
|
|
},
|
|
"CH0_FFS_PCIE_DONE": {
|
|
"direction": "output",
|
|
"bits": [ 231 ]
|
|
},
|
|
"CH1_FFS_PCIE_DONE": {
|
|
"direction": "output",
|
|
"bits": [ 232 ]
|
|
},
|
|
"CH0_FFS_PCIE_CON": {
|
|
"direction": "output",
|
|
"bits": [ 233 ]
|
|
},
|
|
"CH1_FFS_PCIE_CON": {
|
|
"direction": "output",
|
|
"bits": [ 234 ]
|
|
},
|
|
"CH0_FFS_RLOS": {
|
|
"direction": "output",
|
|
"bits": [ 235 ]
|
|
},
|
|
"CH1_FFS_RLOS": {
|
|
"direction": "output",
|
|
"bits": [ 236 ]
|
|
},
|
|
"CH0_FFS_LS_SYNC_STATUS": {
|
|
"direction": "output",
|
|
"bits": [ 237 ]
|
|
},
|
|
"CH1_FFS_LS_SYNC_STATUS": {
|
|
"direction": "output",
|
|
"bits": [ 238 ]
|
|
},
|
|
"CH0_FFS_CC_UNDERRUN": {
|
|
"direction": "output",
|
|
"bits": [ 239 ]
|
|
},
|
|
"CH1_FFS_CC_UNDERRUN": {
|
|
"direction": "output",
|
|
"bits": [ 240 ]
|
|
},
|
|
"CH0_FFS_CC_OVERRUN": {
|
|
"direction": "output",
|
|
"bits": [ 241 ]
|
|
},
|
|
"CH1_FFS_CC_OVERRUN": {
|
|
"direction": "output",
|
|
"bits": [ 242 ]
|
|
},
|
|
"CH0_FFS_RXFBFIFO_ERROR": {
|
|
"direction": "output",
|
|
"bits": [ 243 ]
|
|
},
|
|
"CH1_FFS_RXFBFIFO_ERROR": {
|
|
"direction": "output",
|
|
"bits": [ 244 ]
|
|
},
|
|
"CH0_FFS_TXFBFIFO_ERROR": {
|
|
"direction": "output",
|
|
"bits": [ 245 ]
|
|
},
|
|
"CH1_FFS_TXFBFIFO_ERROR": {
|
|
"direction": "output",
|
|
"bits": [ 246 ]
|
|
},
|
|
"CH0_FFS_RLOL": {
|
|
"direction": "output",
|
|
"bits": [ 247 ]
|
|
},
|
|
"CH1_FFS_RLOL": {
|
|
"direction": "output",
|
|
"bits": [ 248 ]
|
|
},
|
|
"CH0_FFS_SKP_ADDED": {
|
|
"direction": "output",
|
|
"bits": [ 249 ]
|
|
},
|
|
"CH1_FFS_SKP_ADDED": {
|
|
"direction": "output",
|
|
"bits": [ 250 ]
|
|
},
|
|
"CH0_FFS_SKP_DELETED": {
|
|
"direction": "output",
|
|
"bits": [ 251 ]
|
|
},
|
|
"CH1_FFS_SKP_DELETED": {
|
|
"direction": "output",
|
|
"bits": [ 252 ]
|
|
},
|
|
"CH0_LDR_RX2CORE": {
|
|
"direction": "output",
|
|
"bits": [ 253 ]
|
|
},
|
|
"CH1_LDR_RX2CORE": {
|
|
"direction": "output",
|
|
"bits": [ 254 ]
|
|
},
|
|
"D_SCIRDATA0": {
|
|
"direction": "output",
|
|
"bits": [ 255 ]
|
|
},
|
|
"D_SCIRDATA1": {
|
|
"direction": "output",
|
|
"bits": [ 256 ]
|
|
},
|
|
"D_SCIRDATA2": {
|
|
"direction": "output",
|
|
"bits": [ 257 ]
|
|
},
|
|
"D_SCIRDATA3": {
|
|
"direction": "output",
|
|
"bits": [ 258 ]
|
|
},
|
|
"D_SCIRDATA4": {
|
|
"direction": "output",
|
|
"bits": [ 259 ]
|
|
},
|
|
"D_SCIRDATA5": {
|
|
"direction": "output",
|
|
"bits": [ 260 ]
|
|
},
|
|
"D_SCIRDATA6": {
|
|
"direction": "output",
|
|
"bits": [ 261 ]
|
|
},
|
|
"D_SCIRDATA7": {
|
|
"direction": "output",
|
|
"bits": [ 262 ]
|
|
},
|
|
"D_SCIINT": {
|
|
"direction": "output",
|
|
"bits": [ 263 ]
|
|
},
|
|
"D_SCAN_OUT_0": {
|
|
"direction": "output",
|
|
"bits": [ 264 ]
|
|
},
|
|
"D_SCAN_OUT_1": {
|
|
"direction": "output",
|
|
"bits": [ 265 ]
|
|
},
|
|
"D_SCAN_OUT_2": {
|
|
"direction": "output",
|
|
"bits": [ 266 ]
|
|
},
|
|
"D_SCAN_OUT_3": {
|
|
"direction": "output",
|
|
"bits": [ 267 ]
|
|
},
|
|
"D_SCAN_OUT_4": {
|
|
"direction": "output",
|
|
"bits": [ 268 ]
|
|
},
|
|
"D_SCAN_OUT_5": {
|
|
"direction": "output",
|
|
"bits": [ 269 ]
|
|
},
|
|
"D_SCAN_OUT_6": {
|
|
"direction": "output",
|
|
"bits": [ 270 ]
|
|
},
|
|
"D_SCAN_OUT_7": {
|
|
"direction": "output",
|
|
"bits": [ 271 ]
|
|
},
|
|
"D_COUT0": {
|
|
"direction": "output",
|
|
"bits": [ 272 ]
|
|
},
|
|
"D_COUT1": {
|
|
"direction": "output",
|
|
"bits": [ 273 ]
|
|
},
|
|
"D_COUT2": {
|
|
"direction": "output",
|
|
"bits": [ 274 ]
|
|
},
|
|
"D_COUT3": {
|
|
"direction": "output",
|
|
"bits": [ 275 ]
|
|
},
|
|
"D_COUT4": {
|
|
"direction": "output",
|
|
"bits": [ 276 ]
|
|
},
|
|
"D_COUT5": {
|
|
"direction": "output",
|
|
"bits": [ 277 ]
|
|
},
|
|
"D_COUT6": {
|
|
"direction": "output",
|
|
"bits": [ 278 ]
|
|
},
|
|
"D_COUT7": {
|
|
"direction": "output",
|
|
"bits": [ 279 ]
|
|
},
|
|
"D_COUT8": {
|
|
"direction": "output",
|
|
"bits": [ 280 ]
|
|
},
|
|
"D_COUT9": {
|
|
"direction": "output",
|
|
"bits": [ 281 ]
|
|
},
|
|
"D_COUT10": {
|
|
"direction": "output",
|
|
"bits": [ 282 ]
|
|
},
|
|
"D_COUT11": {
|
|
"direction": "output",
|
|
"bits": [ 283 ]
|
|
},
|
|
"D_COUT12": {
|
|
"direction": "output",
|
|
"bits": [ 284 ]
|
|
},
|
|
"D_COUT13": {
|
|
"direction": "output",
|
|
"bits": [ 285 ]
|
|
},
|
|
"D_COUT14": {
|
|
"direction": "output",
|
|
"bits": [ 286 ]
|
|
},
|
|
"D_COUT15": {
|
|
"direction": "output",
|
|
"bits": [ 287 ]
|
|
},
|
|
"D_COUT16": {
|
|
"direction": "output",
|
|
"bits": [ 288 ]
|
|
},
|
|
"D_COUT17": {
|
|
"direction": "output",
|
|
"bits": [ 289 ]
|
|
},
|
|
"D_COUT18": {
|
|
"direction": "output",
|
|
"bits": [ 290 ]
|
|
},
|
|
"D_COUT19": {
|
|
"direction": "output",
|
|
"bits": [ 291 ]
|
|
},
|
|
"D_REFCLKI": {
|
|
"direction": "input",
|
|
"bits": [ 292 ]
|
|
},
|
|
"D_FFS_PLOL": {
|
|
"direction": "output",
|
|
"bits": [ 293 ]
|
|
}
|
|
},
|
|
"cells": {
|
|
},
|
|
"netnames": {
|
|
"CH0_FFC_CDR_EN_BITSLIP": {
|
|
"hide_name": 0,
|
|
"bits": [ 138 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1876.11-1876.33"
|
|
}
|
|
},
|
|
"CH0_FFC_DIV11_MODE_RX": {
|
|
"hide_name": 0,
|
|
"bits": [ 88 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1826.11-1826.32"
|
|
}
|
|
},
|
|
"CH0_FFC_DIV11_MODE_TX": {
|
|
"hide_name": 0,
|
|
"bits": [ 94 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1832.11-1832.32"
|
|
}
|
|
},
|
|
"CH0_FFC_EI_EN": {
|
|
"hide_name": 0,
|
|
"bits": [ 66 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v:1804.11-1804.24"
|
|
}
|
|
},
|
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|
|
"ports": {
|
|
"Z": {
|
|
"direction": "output",
|
|
"bits": [ 2 ]
|
|
}
|
|
},
|
|
"cells": {
|
|
},
|
|
"netnames": {
|
|
"Z": {
|
|
"hide_name": 0,
|
|
"bits": [ 2 ],
|
|
"attributes": {
|
|
"src": "/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:398.19-398.20"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|