Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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"direction": "input",
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
|
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|
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|
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|
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|
|
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|
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|
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|
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|
|
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|
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|
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|
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
"direction": "input",
|
|
"bits": [ 235 ]
|
|
},
|
|
"MB32": {
|
|
"direction": "input",
|
|
"bits": [ 236 ]
|
|
},
|
|
"MB31": {
|
|
"direction": "input",
|
|
"bits": [ 237 ]
|
|
},
|
|
"MB30": {
|
|
"direction": "input",
|
|
"bits": [ 238 ]
|
|
},
|
|
"MB29": {
|
|
"direction": "input",
|
|
"bits": [ 239 ]
|
|
},
|
|
"MB28": {
|
|
"direction": "input",
|
|
"bits": [ 240 ]
|
|
},
|
|
"MB27": {
|
|
"direction": "input",
|
|
"bits": [ 241 ]
|
|
},
|
|
"MB26": {
|
|
"direction": "input",
|
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"bits": [ 242 ]
|
|
},
|
|
"MB25": {
|
|
"direction": "input",
|
|
"bits": [ 243 ]
|
|
},
|
|
"MB24": {
|
|
"direction": "input",
|
|
"bits": [ 244 ]
|
|
},
|
|
"MB23": {
|
|
"direction": "input",
|
|
"bits": [ 245 ]
|
|
},
|
|
"MB22": {
|
|
"direction": "input",
|
|
"bits": [ 246 ]
|
|
},
|
|
"MB21": {
|
|
"direction": "input",
|
|
"bits": [ 247 ]
|
|
},
|
|
"MB20": {
|
|
"direction": "input",
|
|
"bits": [ 248 ]
|
|
},
|
|
"MB19": {
|
|
"direction": "input",
|
|
"bits": [ 249 ]
|
|
},
|
|
"MB18": {
|
|
"direction": "input",
|
|
"bits": [ 250 ]
|
|
},
|
|
"MB17": {
|
|
"direction": "input",
|
|
"bits": [ 251 ]
|
|
},
|
|
"MB16": {
|
|
"direction": "input",
|
|
"bits": [ 252 ]
|
|
},
|
|
"MB15": {
|
|
"direction": "input",
|
|
"bits": [ 253 ]
|
|
},
|
|
"MB14": {
|
|
"direction": "input",
|
|
"bits": [ 254 ]
|
|
},
|
|
"MB13": {
|
|
"direction": "input",
|
|
"bits": [ 255 ]
|
|
},
|
|
"MB12": {
|
|
"direction": "input",
|
|
"bits": [ 256 ]
|
|
},
|
|
"MB11": {
|
|
"direction": "input",
|
|
"bits": [ 257 ]
|
|
},
|
|
"MB10": {
|
|
"direction": "input",
|
|
"bits": [ 258 ]
|
|
},
|
|
"MB9": {
|
|
"direction": "input",
|
|
"bits": [ 259 ]
|
|
},
|
|
"MB8": {
|
|
"direction": "input",
|
|
"bits": [ 260 ]
|
|
},
|
|
"MB7": {
|
|
"direction": "input",
|
|
"bits": [ 261 ]
|
|
},
|
|
"MB6": {
|
|
"direction": "input",
|
|
"bits": [ 262 ]
|
|
},
|
|
"MB5": {
|
|
"direction": "input",
|
|
"bits": [ 263 ]
|
|
},
|
|
"MB4": {
|
|
"direction": "input",
|
|
"bits": [ 264 ]
|
|
},
|
|
"MB3": {
|
|
"direction": "input",
|
|
"bits": [ 265 ]
|
|
},
|
|
"MB2": {
|
|
"direction": "input",
|
|
"bits": [ 266 ]
|
|
},
|
|
"MB1": {
|
|
"direction": "input",
|
|
"bits": [ 267 ]
|
|
},
|
|
"MB0": {
|
|
"direction": "input",
|
|
"bits": [ 268 ]
|
|
},
|
|
"CIN53": {
|
|
"direction": "input",
|
|
"bits": [ 269 ]
|
|
},
|
|
"CIN52": {
|
|
"direction": "input",
|
|
"bits": [ 270 ]
|
|
},
|
|
"CIN51": {
|
|
"direction": "input",
|
|
"bits": [ 271 ]
|
|
},
|
|
"CIN50": {
|
|
"direction": "input",
|
|
"bits": [ 272 ]
|
|
},
|
|
"CIN49": {
|
|
"direction": "input",
|
|
"bits": [ 273 ]
|
|
},
|
|
"CIN48": {
|
|
"direction": "input",
|
|
"bits": [ 274 ]
|
|
},
|
|
"CIN47": {
|
|
"direction": "input",
|
|
"bits": [ 275 ]
|
|
},
|
|
"CIN46": {
|
|
"direction": "input",
|
|
"bits": [ 276 ]
|
|
},
|
|
"CIN45": {
|
|
"direction": "input",
|
|
"bits": [ 277 ]
|
|
},
|
|
"CIN44": {
|
|
"direction": "input",
|
|
"bits": [ 278 ]
|
|
},
|
|
"CIN43": {
|
|
"direction": "input",
|
|
"bits": [ 279 ]
|
|
},
|
|
"CIN42": {
|
|
"direction": "input",
|
|
"bits": [ 280 ]
|
|
},
|
|
"CIN41": {
|
|
"direction": "input",
|
|
"bits": [ 281 ]
|
|
},
|
|
"CIN40": {
|
|
"direction": "input",
|
|
"bits": [ 282 ]
|
|
},
|
|
"CIN39": {
|
|
"direction": "input",
|
|
"bits": [ 283 ]
|
|
},
|
|
"CIN38": {
|
|
"direction": "input",
|
|
"bits": [ 284 ]
|
|
},
|
|
"CIN37": {
|
|
"direction": "input",
|
|
"bits": [ 285 ]
|
|
},
|
|
"CIN36": {
|
|
"direction": "input",
|
|
"bits": [ 286 ]
|
|
},
|
|
"CIN35": {
|
|
"direction": "input",
|
|
"bits": [ 287 ]
|
|
},
|
|
"CIN34": {
|
|
"direction": "input",
|
|
"bits": [ 288 ]
|
|
},
|
|
"CIN33": {
|
|
"direction": "input",
|
|
"bits": [ 289 ]
|
|
},
|
|
"CIN32": {
|
|
"direction": "input",
|
|
"bits": [ 290 ]
|
|
},
|
|
"CIN31": {
|
|
"direction": "input",
|
|
"bits": [ 291 ]
|
|
},
|
|
"CIN30": {
|
|
"direction": "input",
|
|
"bits": [ 292 ]
|
|
},
|
|
"CIN29": {
|
|
"direction": "input",
|
|
"bits": [ 293 ]
|
|
},
|
|
"CIN28": {
|
|
"direction": "input",
|
|
"bits": [ 294 ]
|
|
},
|
|
"CIN27": {
|
|
"direction": "input",
|
|
"bits": [ 295 ]
|
|
},
|
|
"CIN26": {
|
|
"direction": "input",
|
|
"bits": [ 296 ]
|
|
},
|
|
"CIN25": {
|
|
"direction": "input",
|
|
"bits": [ 297 ]
|
|
},
|
|
"CIN24": {
|
|
"direction": "input",
|
|
"bits": [ 298 ]
|
|
},
|
|
"CIN23": {
|
|
"direction": "input",
|
|
"bits": [ 299 ]
|
|
},
|
|
"CIN22": {
|
|
"direction": "input",
|
|
"bits": [ 300 ]
|
|
},
|
|
"CIN21": {
|
|
"direction": "input",
|
|
"bits": [ 301 ]
|
|
},
|
|
"CIN20": {
|
|
"direction": "input",
|
|
"bits": [ 302 ]
|
|
},
|
|
"CIN19": {
|
|
"direction": "input",
|
|
"bits": [ 303 ]
|
|
},
|
|
"CIN18": {
|
|
"direction": "input",
|
|
"bits": [ 304 ]
|
|
},
|
|
"CIN17": {
|
|
"direction": "input",
|
|
"bits": [ 305 ]
|
|
},
|
|
"CIN16": {
|
|
"direction": "input",
|
|
"bits": [ 306 ]
|
|
},
|
|
"CIN15": {
|
|
"direction": "input",
|
|
"bits": [ 307 ]
|
|
},
|
|
"CIN14": {
|
|
"direction": "input",
|
|
"bits": [ 308 ]
|
|
},
|
|
"CIN13": {
|
|
"direction": "input",
|
|
"bits": [ 309 ]
|
|
},
|
|
"CIN12": {
|
|
"direction": "input",
|
|
"bits": [ 310 ]
|
|
},
|
|
"CIN11": {
|
|
"direction": "input",
|
|
"bits": [ 311 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 312 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 313 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 314 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 315 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 316 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 317 ]
|
|
},
|
|
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|
|
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|
|
"bits": [ 318 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 319 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 320 ]
|
|
},
|
|
"CIN1": {
|
|
"direction": "input",
|
|
"bits": [ 321 ]
|
|
},
|
|
"CIN0": {
|
|
"direction": "input",
|
|
"bits": [ 322 ]
|
|
},
|
|
"OP10": {
|
|
"direction": "input",
|
|
"bits": [ 323 ]
|
|
},
|
|
"OP9": {
|
|
"direction": "input",
|
|
"bits": [ 324 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 325 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
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|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 327 ]
|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 330 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
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|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 332 ]
|
|
},
|
|
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|
|
"direction": "input",
|
|
"bits": [ 333 ]
|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
"R27": {
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
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|
|
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|
|
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|
|
},
|
|
"R0": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
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|
|
"direction": "output",
|
|
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|
|
},
|
|
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|
|
"direction": "output",
|
|
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|
|
},
|
|
"CO51": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
"CO50": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
"CO49": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
"CO48": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
"CO47": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
"CO46": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
"CO45": {
|
|
"direction": "output",
|
|
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|
|
},
|
|
"CO44": {
|
|
"direction": "output",
|
|
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|
|
},
|
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"CH0_INVERT_TX": "DONTCARE",
|
|
"CH0_LDR_CORE2TX_SEL": "DONTCARE",
|
|
"CH0_LDR_RX2CORE_SEL": "DONTCARE",
|
|
"CH0_LEQ_OFFSET_SEL": "DONTCARE",
|
|
"CH0_LEQ_OFFSET_TRIM": "DONTCARE",
|
|
"CH0_LSM_DISABLE": "DONTCARE",
|
|
"CH0_MATCH_2_ENABLE": "DONTCARE",
|
|
"CH0_MATCH_4_ENABLE": "DONTCARE",
|
|
"CH0_MIN_IPG_CNT": "DONTCARE",
|
|
"CH0_PCIE_EI_EN": "DONTCARE",
|
|
"CH0_PCIE_MODE": "DONTCARE",
|
|
"CH0_PCS_DET_TIME_SEL": "DONTCARE",
|
|
"CH0_PDEN_SEL": "DONTCARE",
|
|
"CH0_PRBS_ENABLE": "DONTCARE",
|
|
"CH0_PRBS_LOCK": "DONTCARE",
|
|
"CH0_PRBS_SELECTION": "DONTCARE",
|
|
"CH0_PROTOCOL": "DONTCARE",
|
|
"CH0_RATE_MODE_RX": "DONTCARE",
|
|
"CH0_RATE_MODE_TX": "DONTCARE",
|
|
"CH0_RCV_DCC_EN": "DONTCARE",
|
|
"CH0_REG_BAND_OFFSET": "DONTCARE",
|
|
"CH0_REG_BAND_SEL": "DONTCARE",
|
|
"CH0_REG_IDAC_EN": "DONTCARE",
|
|
"CH0_REG_IDAC_SEL": "DONTCARE",
|
|
"CH0_REQ_EN": "DONTCARE",
|
|
"CH0_REQ_LVL_SET": "DONTCARE",
|
|
"CH0_RIO_MODE": "DONTCARE",
|
|
"CH0_RLOS_SEL": "DONTCARE",
|
|
"CH0_RPWDNB": "DONTCARE",
|
|
"CH0_RTERM_RX": "DONTCARE",
|
|
"CH0_RTERM_TX": "DONTCARE",
|
|
"CH0_RXIN_CM": "DONTCARE",
|
|
"CH0_RXTERM_CM": "DONTCARE",
|
|
"CH0_RX_DCO_CK_DIV": "DONTCARE",
|
|
"CH0_RX_DIV11_SEL": "DONTCARE",
|
|
"CH0_RX_GEAR_BYPASS": "DONTCARE",
|
|
"CH0_RX_GEAR_MODE": "DONTCARE",
|
|
"CH0_RX_LOS_CEQ": "DONTCARE",
|
|
"CH0_RX_LOS_EN": "DONTCARE",
|
|
"CH0_RX_LOS_HYST_EN": "DONTCARE",
|
|
"CH0_RX_LOS_LVL": "DONTCARE",
|
|
"CH0_RX_RATE_SEL": "DONTCARE",
|
|
"CH0_RX_SB_BYPASS": "DONTCARE",
|
|
"CH0_SB_BYPASS": "DONTCARE",
|
|
"CH0_SEL_SD_RX_CLK": "DONTCARE",
|
|
"CH0_TDRV_DAT_SEL": "DONTCARE",
|
|
"CH0_TDRV_POST_EN": "DONTCARE",
|
|
"CH0_TDRV_PRE_EN": "DONTCARE",
|
|
"CH0_TDRV_SLICE0_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE0_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE1_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE1_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE2_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE2_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE3_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE3_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE4_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE4_SEL": "DONTCARE",
|
|
"CH0_TDRV_SLICE5_CUR": "DONTCARE",
|
|
"CH0_TDRV_SLICE5_SEL": "DONTCARE",
|
|
"CH0_TPWDNB": "DONTCARE",
|
|
"CH0_TXAMPLITUDE": "DONTCARE",
|
|
"CH0_TXDEPOST": "DONTCARE",
|
|
"CH0_TXDEPRE": "DONTCARE",
|
|
"CH0_TX_CM_SEL": "DONTCARE",
|
|
"CH0_TX_DIV11_SEL": "DONTCARE",
|
|
"CH0_TX_GEAR_BYPASS": "DONTCARE",
|
|
"CH0_TX_GEAR_MODE": "DONTCARE",
|
|
"CH0_TX_POST_SIGN": "DONTCARE",
|
|
"CH0_TX_PRE_SIGN": "DONTCARE",
|
|
"CH0_UC_MODE": "DONTCARE",
|
|
"CH0_UDF_COMMA_A": "DONTCARE",
|
|
"CH0_UDF_COMMA_B": "DONTCARE",
|
|
"CH0_UDF_COMMA_MASK": "DONTCARE",
|
|
"CH0_WA_BYPASS": "DONTCARE",
|
|
"CH0_WA_MODE": "DONTCARE",
|
|
"CH1_AUTO_CALIB_EN": "DONTCARE",
|
|
"CH1_AUTO_FACQ_EN": "DONTCARE",
|
|
"CH1_BAND_THRESHOLD": "DONTCARE",
|
|
"CH1_CALIB_CK_MODE": "DONTCARE",
|
|
"CH1_CC_MATCH_1": "DONTCARE",
|
|
"CH1_CC_MATCH_2": "DONTCARE",
|
|
"CH1_CC_MATCH_3": "DONTCARE",
|
|
"CH1_CC_MATCH_4": "DONTCARE",
|
|
"CH1_CDR_CNT4SEL": "DONTCARE",
|
|
"CH1_CDR_CNT8SEL": "DONTCARE",
|
|
"CH1_CDR_MAX_RATE": "DONTCARE",
|
|
"CH1_CTC_BYPASS": "DONTCARE",
|
|
"CH1_DCOATDCFG": "DONTCARE",
|
|
"CH1_DCOATDDLY": "DONTCARE",
|
|
"CH1_DCOBYPSATD": "DONTCARE",
|
|
"CH1_DCOCALDIV": "DONTCARE",
|
|
"CH1_DCOCTLGI": "DONTCARE",
|
|
"CH1_DCODISBDAVOID": "DONTCARE",
|
|
"CH1_DCOFLTDAC": "DONTCARE",
|
|
"CH1_DCOFTNRG": "DONTCARE",
|
|
"CH1_DCOIOSTUNE": "DONTCARE",
|
|
"CH1_DCOITUNE": "DONTCARE",
|
|
"CH1_DCOITUNE4LSB": "DONTCARE",
|
|
"CH1_DCOIUPDNX2": "DONTCARE",
|
|
"CH1_DCONUOFLSB": "DONTCARE",
|
|
"CH1_DCOSCALEI": "DONTCARE",
|
|
"CH1_DCOSTARTVAL": "DONTCARE",
|
|
"CH1_DCOSTEP": "DONTCARE",
|
|
"CH1_DEC_BYPASS": "DONTCARE",
|
|
"CH1_ENABLE_CG_ALIGN": "DONTCARE",
|
|
"CH1_ENC_BYPASS": "DONTCARE",
|
|
"CH1_FF_RX_F_CLK_DIS": "DONTCARE",
|
|
"CH1_FF_RX_H_CLK_EN": "DONTCARE",
|
|
"CH1_FF_TX_F_CLK_DIS": "DONTCARE",
|
|
"CH1_FF_TX_H_CLK_EN": "DONTCARE",
|
|
"CH1_GE_AN_ENABLE": "DONTCARE",
|
|
"CH1_INVERT_RX": "DONTCARE",
|
|
"CH1_INVERT_TX": "DONTCARE",
|
|
"CH1_LDR_CORE2TX_SEL": "DONTCARE",
|
|
"CH1_LDR_RX2CORE_SEL": "DONTCARE",
|
|
"CH1_LEQ_OFFSET_SEL": "DONTCARE",
|
|
"CH1_LEQ_OFFSET_TRIM": "DONTCARE",
|
|
"CH1_LSM_DISABLE": "DONTCARE",
|
|
"CH1_MATCH_2_ENABLE": "DONTCARE",
|
|
"CH1_MATCH_4_ENABLE": "DONTCARE",
|
|
"CH1_MIN_IPG_CNT": "DONTCARE",
|
|
"CH1_PCIE_EI_EN": "DONTCARE",
|
|
"CH1_PCIE_MODE": "DONTCARE",
|
|
"CH1_PCS_DET_TIME_SEL": "DONTCARE",
|
|
"CH1_PDEN_SEL": "DONTCARE",
|
|
"CH1_PRBS_ENABLE": "DONTCARE",
|
|
"CH1_PRBS_LOCK": "DONTCARE",
|
|
"CH1_PRBS_SELECTION": "DONTCARE",
|
|
"CH1_PROTOCOL": "DONTCARE",
|
|
"CH1_RATE_MODE_RX": "DONTCARE",
|
|
"CH1_RATE_MODE_TX": "DONTCARE",
|
|
"CH1_RCV_DCC_EN": "DONTCARE",
|
|
"CH1_REG_BAND_OFFSET": "DONTCARE",
|
|
"CH1_REG_BAND_SEL": "DONTCARE",
|
|
"CH1_REG_IDAC_EN": "DONTCARE",
|
|
"CH1_REG_IDAC_SEL": "DONTCARE",
|
|
"CH1_REQ_EN": "DONTCARE",
|
|
"CH1_REQ_LVL_SET": "DONTCARE",
|
|
"CH1_RIO_MODE": "DONTCARE",
|
|
"CH1_RLOS_SEL": "DONTCARE",
|
|
"CH1_RPWDNB": "DONTCARE",
|
|
"CH1_RTERM_RX": "DONTCARE",
|
|
"CH1_RTERM_TX": "DONTCARE",
|
|
"CH1_RXIN_CM": "DONTCARE",
|
|
"CH1_RXTERM_CM": "DONTCARE",
|
|
"CH1_RX_DCO_CK_DIV": "DONTCARE",
|
|
"CH1_RX_DIV11_SEL": "DONTCARE",
|
|
"CH1_RX_GEAR_BYPASS": "DONTCARE",
|
|
"CH1_RX_GEAR_MODE": "DONTCARE",
|
|
"CH1_RX_LOS_CEQ": "DONTCARE",
|
|
"CH1_RX_LOS_EN": "DONTCARE",
|
|
"CH1_RX_LOS_HYST_EN": "DONTCARE",
|
|
"CH1_RX_LOS_LVL": "DONTCARE",
|
|
"CH1_RX_RATE_SEL": "DONTCARE",
|
|
"CH1_RX_SB_BYPASS": "DONTCARE",
|
|
"CH1_SB_BYPASS": "DONTCARE",
|
|
"CH1_SEL_SD_RX_CLK": "DONTCARE",
|
|
"CH1_TDRV_DAT_SEL": "DONTCARE",
|
|
"CH1_TDRV_POST_EN": "DONTCARE",
|
|
"CH1_TDRV_PRE_EN": "DONTCARE",
|
|
"CH1_TDRV_SLICE0_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE0_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE1_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE1_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE2_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE2_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE3_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE3_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE4_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE4_SEL": "DONTCARE",
|
|
"CH1_TDRV_SLICE5_CUR": "DONTCARE",
|
|
"CH1_TDRV_SLICE5_SEL": "DONTCARE",
|
|
"CH1_TPWDNB": "DONTCARE",
|
|
"CH1_TXAMPLITUDE": "DONTCARE",
|
|
"CH1_TXDEPOST": "DONTCARE",
|
|
"CH1_TXDEPRE": "DONTCARE",
|
|
"CH1_TX_CM_SEL": "DONTCARE",
|
|
"CH1_TX_DIV11_SEL": "DONTCARE",
|
|
"CH1_TX_GEAR_BYPASS": "DONTCARE",
|
|
"CH1_TX_GEAR_MODE": "DONTCARE",
|
|
"CH1_TX_POST_SIGN": "DONTCARE",
|
|
"CH1_TX_PRE_SIGN": "DONTCARE",
|
|
"CH1_UC_MODE": "DONTCARE",
|
|
"CH1_UDF_COMMA_A": "DONTCARE",
|
|
"CH1_UDF_COMMA_B": "DONTCARE",
|
|
"CH1_UDF_COMMA_MASK": "DONTCARE",
|
|
"CH1_WA_BYPASS": "DONTCARE",
|
|
"CH1_WA_MODE": "DONTCARE",
|
|
"D_BITCLK_FROM_ND_EN": "DONTCARE",
|
|
"D_BITCLK_LOCAL_EN": "DONTCARE",
|
|
"D_BITCLK_ND_EN": "DONTCARE",
|
|
"D_BUS8BIT_SEL": "DONTCARE",
|
|
"D_CDR_LOL_SET": "DONTCARE",
|
|
"D_CMUSETBIASI": "DONTCARE",
|
|
"D_CMUSETI4CPP": "DONTCARE",
|
|
"D_CMUSETI4CPZ": "DONTCARE",
|
|
"D_CMUSETI4VCO": "DONTCARE",
|
|
"D_CMUSETICP4P": "DONTCARE",
|
|
"D_CMUSETICP4Z": "DONTCARE",
|
|
"D_CMUSETINITVCT": "DONTCARE",
|
|
"D_CMUSETISCL4VCO": "DONTCARE",
|
|
"D_CMUSETP1GM": "DONTCARE",
|
|
"D_CMUSETP2AGM": "DONTCARE",
|
|
"D_CMUSETZGM": "DONTCARE",
|
|
"D_DCO_CALIB_TIME_SEL": "DONTCARE",
|
|
"D_HIGH_MARK": "DONTCARE",
|
|
"D_IB_PWDNB": "DONTCARE",
|
|
"D_ISETLOS": "DONTCARE",
|
|
"D_LOW_MARK": "DONTCARE",
|
|
"D_MACROPDB": "DONTCARE",
|
|
"D_PD_ISET": "DONTCARE",
|
|
"D_PLL_LOL_SET": "DONTCARE",
|
|
"D_REFCK_MODE": "DONTCARE",
|
|
"D_REQ_ISET": "DONTCARE",
|
|
"D_RG_EN": "DONTCARE",
|
|
"D_RG_SET": "DONTCARE",
|
|
"D_SETICONST_AUX": "DONTCARE",
|
|
"D_SETICONST_CH": "DONTCARE",
|
|
"D_SETIRPOLY_AUX": "DONTCARE",
|
|
"D_SETIRPOLY_CH": "DONTCARE",
|
|
"D_SETPLLRC": "DONTCARE",
|
|
"D_SYNC_LOCAL_EN": "DONTCARE",
|
|
"D_SYNC_ND_EN": "DONTCARE",
|
|
"D_TXPLL_PWDNB": "DONTCARE",
|
|
"D_TX_MAX_RATE": "DONTCARE",
|
|
"D_TX_VCO_CK_DIV": "DONTCARE",
|
|
"D_XGE_MODE": "DONTCARE"
|
|
},
|
|
"ports": {
|
|
"CH0_HDINP": {
|
|
"direction": "input",
|
|
"bits": [ 2 ]
|
|
},
|
|
"CH1_HDINP": {
|
|
"direction": "input",
|
|
"bits": [ 3 ]
|
|
},
|
|
"CH0_HDINN": {
|
|
"direction": "input",
|
|
"bits": [ 4 ]
|
|
},
|
|
"CH1_HDINN": {
|
|
"direction": "input",
|
|
"bits": [ 5 ]
|
|
},
|
|
"D_TXBIT_CLKP_FROM_ND": {
|
|
"direction": "input",
|
|
"bits": [ 6 ]
|
|
},
|
|
"D_TXBIT_CLKN_FROM_ND": {
|
|
"direction": "input",
|
|
"bits": [ 7 ]
|
|
},
|
|
"D_SYNC_ND": {
|
|
"direction": "input",
|
|
"bits": [ 8 ]
|
|
},
|
|
"D_TXPLL_LOL_FROM_ND": {
|
|
"direction": "input",
|
|
"bits": [ 9 ]
|
|
},
|
|
"CH0_RX_REFCLK": {
|
|
"direction": "input",
|
|
"bits": [ 10 ]
|
|
},
|
|
"CH1_RX_REFCLK": {
|
|
"direction": "input",
|
|
"bits": [ 11 ]
|
|
},
|
|
"CH0_FF_RXI_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 12 ]
|
|
},
|
|
"CH1_FF_RXI_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 13 ]
|
|
},
|
|
"CH0_FF_TXI_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 14 ]
|
|
},
|
|
"CH1_FF_TXI_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 15 ]
|
|
},
|
|
"CH0_FF_EBRD_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 16 ]
|
|
},
|
|
"CH1_FF_EBRD_CLK": {
|
|
"direction": "input",
|
|
"bits": [ 17 ]
|
|
},
|
|
"CH0_FF_TX_D_0": {
|
|
"direction": "input",
|
|
"bits": [ 18 ]
|
|
},
|
|
"CH1_FF_TX_D_0": {
|
|
"direction": "input",
|
|
"bits": [ 19 ]
|
|
},
|
|
"CH0_FF_TX_D_1": {
|
|
"direction": "input",
|
|
"bits": [ 20 ]
|
|
},
|
|
"CH1_FF_TX_D_1": {
|
|
"direction": "input",
|
|
"bits": [ 21 ]
|
|
},
|
|
"CH0_FF_TX_D_2": {
|
|
"direction": "input",
|
|
"bits": [ 22 ]
|
|
},
|
|
"CH1_FF_TX_D_2": {
|
|
"direction": "input",
|
|
"bits": [ 23 ]
|
|
},
|
|
"CH0_FF_TX_D_3": {
|
|
"direction": "input",
|
|
"bits": [ 24 ]
|
|
},
|
|
"CH1_FF_TX_D_3": {
|
|
"direction": "input",
|
|
"bits": [ 25 ]
|
|
},
|
|
"CH0_FF_TX_D_4": {
|
|
"direction": "input",
|
|
"bits": [ 26 ]
|
|
},
|
|
"CH1_FF_TX_D_4": {
|
|
"direction": "input",
|
|
"bits": [ 27 ]
|
|
},
|
|
"CH0_FF_TX_D_5": {
|
|
"direction": "input",
|
|
"bits": [ 28 ]
|
|
},
|
|
"CH1_FF_TX_D_5": {
|
|
"direction": "input",
|
|
"bits": [ 29 ]
|
|
},
|
|
"CH0_FF_TX_D_6": {
|
|
"direction": "input",
|
|
"bits": [ 30 ]
|
|
},
|
|
"CH1_FF_TX_D_6": {
|
|
"direction": "input",
|
|
"bits": [ 31 ]
|
|
},
|
|
"CH0_FF_TX_D_7": {
|
|
"direction": "input",
|
|
"bits": [ 32 ]
|
|
},
|
|
"CH1_FF_TX_D_7": {
|
|
"direction": "input",
|
|
"bits": [ 33 ]
|
|
},
|
|
"CH0_FF_TX_D_8": {
|
|
"direction": "input",
|
|
"bits": [ 34 ]
|
|
},
|
|
"CH1_FF_TX_D_8": {
|
|
"direction": "input",
|
|
"bits": [ 35 ]
|
|
},
|
|
"CH0_FF_TX_D_9": {
|
|
"direction": "input",
|
|
"bits": [ 36 ]
|
|
},
|
|
"CH1_FF_TX_D_9": {
|
|
"direction": "input",
|
|
"bits": [ 37 ]
|
|
},
|
|
"CH0_FF_TX_D_10": {
|
|
"direction": "input",
|
|
"bits": [ 38 ]
|
|
},
|
|
"CH1_FF_TX_D_10": {
|
|
"direction": "input",
|
|
"bits": [ 39 ]
|
|
},
|
|
"CH0_FF_TX_D_11": {
|
|
"direction": "input",
|
|
"bits": [ 40 ]
|
|
},
|
|
"CH1_FF_TX_D_11": {
|
|
"direction": "input",
|
|
"bits": [ 41 ]
|
|
},
|
|
"CH0_FF_TX_D_12": {
|
|
"direction": "input",
|
|
"bits": [ 42 ]
|
|
},
|
|
"CH1_FF_TX_D_12": {
|
|
"direction": "input",
|
|
"bits": [ 43 ]
|
|
},
|
|
"CH0_FF_TX_D_13": {
|
|
"direction": "input",
|
|
"bits": [ 44 ]
|
|
},
|
|
"CH1_FF_TX_D_13": {
|
|
"direction": "input",
|
|
"bits": [ 45 ]
|
|
},
|
|
"CH0_FF_TX_D_14": {
|
|
"direction": "input",
|
|
"bits": [ 46 ]
|
|
},
|
|
"CH1_FF_TX_D_14": {
|
|
"direction": "input",
|
|
"bits": [ 47 ]
|
|
},
|
|
"CH0_FF_TX_D_15": {
|
|
"direction": "input",
|
|
"bits": [ 48 ]
|
|
},
|
|
"CH1_FF_TX_D_15": {
|
|
"direction": "input",
|
|
"bits": [ 49 ]
|
|
},
|
|
"CH0_FF_TX_D_16": {
|
|
"direction": "input",
|
|
"bits": [ 50 ]
|
|
},
|
|
"CH1_FF_TX_D_16": {
|
|
"direction": "input",
|
|
"bits": [ 51 ]
|
|
},
|
|
"CH0_FF_TX_D_17": {
|
|
"direction": "input",
|
|
"bits": [ 52 ]
|
|
},
|
|
"CH1_FF_TX_D_17": {
|
|
"direction": "input",
|
|
"bits": [ 53 ]
|
|
},
|
|
"CH0_FF_TX_D_18": {
|
|
"direction": "input",
|
|
"bits": [ 54 ]
|
|
},
|
|
"CH1_FF_TX_D_18": {
|
|
"direction": "input",
|
|
"bits": [ 55 ]
|
|
},
|
|
"CH0_FF_TX_D_19": {
|
|
"direction": "input",
|
|
"bits": [ 56 ]
|
|
},
|
|
"CH1_FF_TX_D_19": {
|
|
"direction": "input",
|
|
"bits": [ 57 ]
|
|
},
|
|
"CH0_FF_TX_D_20": {
|
|
"direction": "input",
|
|
"bits": [ 58 ]
|
|
},
|
|
"CH1_FF_TX_D_20": {
|
|
"direction": "input",
|
|
"bits": [ 59 ]
|
|
},
|
|
"CH0_FF_TX_D_21": {
|
|
"direction": "input",
|
|
"bits": [ 60 ]
|
|
},
|
|
"CH1_FF_TX_D_21": {
|
|
"direction": "input",
|
|
"bits": [ 61 ]
|
|
},
|
|
"CH0_FF_TX_D_22": {
|
|
"direction": "input",
|
|
"bits": [ 62 ]
|
|
},
|
|
"CH1_FF_TX_D_22": {
|
|
"direction": "input",
|
|
"bits": [ 63 ]
|
|
},
|
|
"CH0_FF_TX_D_23": {
|
|
"direction": "input",
|
|
"bits": [ 64 ]
|
|
},
|
|
"CH1_FF_TX_D_23": {
|
|
"direction": "input",
|
|
"bits": [ 65 ]
|
|
},
|
|
"CH0_FFC_EI_EN": {
|
|
"direction": "input",
|
|
"bits": [ 66 ]
|
|
},
|
|
"CH1_FFC_EI_EN": {
|
|
"direction": "input",
|
|
"bits": [ 67 ]
|
|
},
|
|
"CH0_FFC_PCIE_DET_EN": {
|
|
"direction": "input",
|
|
"bits": [ 68 ]
|
|
},
|
|
"CH1_FFC_PCIE_DET_EN": {
|
|
"direction": "input",
|
|
"bits": [ 69 ]
|
|
},
|
|
"CH0_FFC_PCIE_CT": {
|
|
"direction": "input",
|
|
"bits": [ 70 ]
|
|
},
|
|
"CH1_FFC_PCIE_CT": {
|
|
"direction": "input",
|
|
"bits": [ 71 ]
|
|
},
|
|
"CH0_FFC_SB_INV_RX": {
|
|
"direction": "input",
|
|
"bits": [ 72 ]
|
|
},
|
|
"CH1_FFC_SB_INV_RX": {
|
|
"direction": "input",
|
|
"bits": [ 73 ]
|
|
},
|
|
"CH0_FFC_ENABLE_CGALIGN": {
|
|
"direction": "input",
|
|
"bits": [ 74 ]
|
|
},
|
|
"CH1_FFC_ENABLE_CGALIGN": {
|
|
"direction": "input",
|
|
"bits": [ 75 ]
|
|
},
|
|
"CH0_FFC_SIGNAL_DETECT": {
|
|
"direction": "input",
|
|
"bits": [ 76 ]
|
|
},
|
|
"CH1_FFC_SIGNAL_DETECT": {
|
|
"direction": "input",
|
|
"bits": [ 77 ]
|
|
},
|
|
"CH0_FFC_FB_LOOPBACK": {
|
|
"direction": "input",
|
|
"bits": [ 78 ]
|
|
},
|
|
"CH1_FFC_FB_LOOPBACK": {
|
|
"direction": "input",
|
|
"bits": [ 79 ]
|
|
},
|
|
"CH0_FFC_SB_PFIFO_LP": {
|
|
"direction": "input",
|
|
"bits": [ 80 ]
|
|
},
|
|
"CH1_FFC_SB_PFIFO_LP": {
|
|
"direction": "input",
|
|
"bits": [ 81 ]
|
|
},
|
|
"CH0_FFC_PFIFO_CLR": {
|
|
"direction": "input",
|
|
"bits": [ 82 ]
|
|
},
|
|
"CH1_FFC_PFIFO_CLR": {
|
|
"direction": "input",
|
|
"bits": [ 83 ]
|
|
},
|
|
"CH0_FFC_RATE_MODE_RX": {
|
|
"direction": "input",
|
|
"bits": [ 84 ]
|
|
},
|
|
"CH1_FFC_RATE_MODE_RX": {
|
|
"direction": "input",
|
|
"bits": [ 85 ]
|
|
},
|
|
"CH0_FFC_RATE_MODE_TX": {
|
|
"direction": "input",
|
|
"bits": [ 86 ]
|
|
},
|
|
"CH1_FFC_RATE_MODE_TX": {
|
|
"direction": "input",
|
|
"bits": [ 87 ]
|
|
},
|
|
"CH0_FFC_DIV11_MODE_RX": {
|
|
"direction": "input",
|
|
"bits": [ 88 ]
|
|
},
|
|
"CH1_FFC_DIV11_MODE_RX": {
|
|
"direction": "input",
|
|
"bits": [ 89 ]
|
|
},
|
|
"CH0_FFC_RX_GEAR_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 90 ]
|
|
},
|
|
"CH1_FFC_RX_GEAR_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 91 ]
|
|
},
|
|
"CH0_FFC_TX_GEAR_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 92 ]
|
|
},
|
|
"CH1_FFC_TX_GEAR_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 93 ]
|
|
},
|
|
"CH0_FFC_DIV11_MODE_TX": {
|
|
"direction": "input",
|
|
"bits": [ 94 ]
|
|
},
|
|
"CH1_FFC_DIV11_MODE_TX": {
|
|
"direction": "input",
|
|
"bits": [ 95 ]
|
|
},
|
|
"CH0_FFC_LDR_CORE2TX_EN": {
|
|
"direction": "input",
|
|
"bits": [ 96 ]
|
|
},
|
|
"CH1_FFC_LDR_CORE2TX_EN": {
|
|
"direction": "input",
|
|
"bits": [ 97 ]
|
|
},
|
|
"CH0_FFC_LANE_TX_RST": {
|
|
"direction": "input",
|
|
"bits": [ 98 ]
|
|
},
|
|
"CH1_FFC_LANE_TX_RST": {
|
|
"direction": "input",
|
|
"bits": [ 99 ]
|
|
},
|
|
"CH0_FFC_LANE_RX_RST": {
|
|
"direction": "input",
|
|
"bits": [ 100 ]
|
|
},
|
|
"CH1_FFC_LANE_RX_RST": {
|
|
"direction": "input",
|
|
"bits": [ 101 ]
|
|
},
|
|
"CH0_FFC_RRST": {
|
|
"direction": "input",
|
|
"bits": [ 102 ]
|
|
},
|
|
"CH1_FFC_RRST": {
|
|
"direction": "input",
|
|
"bits": [ 103 ]
|
|
},
|
|
"CH0_FFC_TXPWDNB": {
|
|
"direction": "input",
|
|
"bits": [ 104 ]
|
|
},
|
|
"CH1_FFC_TXPWDNB": {
|
|
"direction": "input",
|
|
"bits": [ 105 ]
|
|
},
|
|
"CH0_FFC_RXPWDNB": {
|
|
"direction": "input",
|
|
"bits": [ 106 ]
|
|
},
|
|
"CH1_FFC_RXPWDNB": {
|
|
"direction": "input",
|
|
"bits": [ 107 ]
|
|
},
|
|
"CH0_LDR_CORE2TX": {
|
|
"direction": "input",
|
|
"bits": [ 108 ]
|
|
},
|
|
"CH1_LDR_CORE2TX": {
|
|
"direction": "input",
|
|
"bits": [ 109 ]
|
|
},
|
|
"D_SCIWDATA0": {
|
|
"direction": "input",
|
|
"bits": [ 110 ]
|
|
},
|
|
"D_SCIWDATA1": {
|
|
"direction": "input",
|
|
"bits": [ 111 ]
|
|
},
|
|
"D_SCIWDATA2": {
|
|
"direction": "input",
|
|
"bits": [ 112 ]
|
|
},
|
|
"D_SCIWDATA3": {
|
|
"direction": "input",
|
|
"bits": [ 113 ]
|
|
},
|
|
"D_SCIWDATA4": {
|
|
"direction": "input",
|
|
"bits": [ 114 ]
|
|
},
|
|
"D_SCIWDATA5": {
|
|
"direction": "input",
|
|
"bits": [ 115 ]
|
|
},
|
|
"D_SCIWDATA6": {
|
|
"direction": "input",
|
|
"bits": [ 116 ]
|
|
},
|
|
"D_SCIWDATA7": {
|
|
"direction": "input",
|
|
"bits": [ 117 ]
|
|
},
|
|
"D_SCIADDR0": {
|
|
"direction": "input",
|
|
"bits": [ 118 ]
|
|
},
|
|
"D_SCIADDR1": {
|
|
"direction": "input",
|
|
"bits": [ 119 ]
|
|
},
|
|
"D_SCIADDR2": {
|
|
"direction": "input",
|
|
"bits": [ 120 ]
|
|
},
|
|
"D_SCIADDR3": {
|
|
"direction": "input",
|
|
"bits": [ 121 ]
|
|
},
|
|
"D_SCIADDR4": {
|
|
"direction": "input",
|
|
"bits": [ 122 ]
|
|
},
|
|
"D_SCIADDR5": {
|
|
"direction": "input",
|
|
"bits": [ 123 ]
|
|
},
|
|
"D_SCIENAUX": {
|
|
"direction": "input",
|
|
"bits": [ 124 ]
|
|
},
|
|
"D_SCISELAUX": {
|
|
"direction": "input",
|
|
"bits": [ 125 ]
|
|
},
|
|
"CH0_SCIEN": {
|
|
"direction": "input",
|
|
"bits": [ 126 ]
|
|
},
|
|
"CH1_SCIEN": {
|
|
"direction": "input",
|
|
"bits": [ 127 ]
|
|
},
|
|
"CH0_SCISEL": {
|
|
"direction": "input",
|
|
"bits": [ 128 ]
|
|
},
|
|
"CH1_SCISEL": {
|
|
"direction": "input",
|
|
"bits": [ 129 ]
|
|
},
|
|
"D_SCIRD": {
|
|
"direction": "input",
|
|
"bits": [ 130 ]
|
|
},
|
|
"D_SCIWSTN": {
|
|
"direction": "input",
|
|
"bits": [ 131 ]
|
|
},
|
|
"D_CYAWSTN": {
|
|
"direction": "input",
|
|
"bits": [ 132 ]
|
|
},
|
|
"D_FFC_SYNC_TOGGLE": {
|
|
"direction": "input",
|
|
"bits": [ 133 ]
|
|
},
|
|
"D_FFC_DUAL_RST": {
|
|
"direction": "input",
|
|
"bits": [ 134 ]
|
|
},
|
|
"D_FFC_MACRO_RST": {
|
|
"direction": "input",
|
|
"bits": [ 135 ]
|
|
},
|
|
"D_FFC_MACROPDB": {
|
|
"direction": "input",
|
|
"bits": [ 136 ]
|
|
},
|
|
"D_FFC_TRST": {
|
|
"direction": "input",
|
|
"bits": [ 137 ]
|
|
},
|
|
"CH0_FFC_CDR_EN_BITSLIP": {
|
|
"direction": "input",
|
|
"bits": [ 138 ]
|
|
},
|
|
"CH1_FFC_CDR_EN_BITSLIP": {
|
|
"direction": "input",
|
|
"bits": [ 139 ]
|
|
},
|
|
"D_SCAN_ENABLE": {
|
|
"direction": "input",
|
|
"bits": [ 140 ]
|
|
},
|
|
"D_SCAN_IN_0": {
|
|
"direction": "input",
|
|
"bits": [ 141 ]
|
|
},
|
|
"D_SCAN_IN_1": {
|
|
"direction": "input",
|
|
"bits": [ 142 ]
|
|
},
|
|
"D_SCAN_IN_2": {
|
|
"direction": "input",
|
|
"bits": [ 143 ]
|
|
},
|
|
"D_SCAN_IN_3": {
|
|
"direction": "input",
|
|
"bits": [ 144 ]
|
|
},
|
|
"D_SCAN_IN_4": {
|
|
"direction": "input",
|
|
"bits": [ 145 ]
|
|
},
|
|
"D_SCAN_IN_5": {
|
|
"direction": "input",
|
|
"bits": [ 146 ]
|
|
},
|
|
"D_SCAN_IN_6": {
|
|
"direction": "input",
|
|
"bits": [ 147 ]
|
|
},
|
|
"D_SCAN_IN_7": {
|
|
"direction": "input",
|
|
"bits": [ 148 ]
|
|
},
|
|
"D_SCAN_MODE": {
|
|
"direction": "input",
|
|
"bits": [ 149 ]
|
|
},
|
|
"D_SCAN_RESET": {
|
|
"direction": "input",
|
|
"bits": [ 150 ]
|
|
},
|
|
"D_CIN0": {
|
|
"direction": "input",
|
|
"bits": [ 151 ]
|
|
},
|
|
"D_CIN1": {
|
|
"direction": "input",
|
|
"bits": [ 152 ]
|
|
},
|
|
"D_CIN2": {
|
|
"direction": "input",
|
|
"bits": [ 153 ]
|
|
},
|
|
"D_CIN3": {
|
|
"direction": "input",
|
|
"bits": [ 154 ]
|
|
},
|
|
"D_CIN4": {
|
|
"direction": "input",
|
|
"bits": [ 155 ]
|
|
},
|
|
"D_CIN5": {
|
|
"direction": "input",
|
|
"bits": [ 156 ]
|
|
},
|
|
"D_CIN6": {
|
|
"direction": "input",
|
|
"bits": [ 157 ]
|
|
},
|
|
"D_CIN7": {
|
|
"direction": "input",
|
|
"bits": [ 158 ]
|
|
},
|
|
"D_CIN8": {
|
|
"direction": "input",
|
|
"bits": [ 159 ]
|
|
},
|
|
"D_CIN9": {
|
|
"direction": "input",
|
|
"bits": [ 160 ]
|
|
},
|
|
"D_CIN10": {
|
|
"direction": "input",
|
|
"bits": [ 161 ]
|
|
},
|
|
"D_CIN11": {
|
|
"direction": "input",
|
|
"bits": [ 162 ]
|
|
},
|
|
"CH0_HDOUTP": {
|
|
"direction": "output",
|
|
"bits": [ 163 ]
|
|
},
|
|
"CH1_HDOUTP": {
|
|
"direction": "output",
|
|
"bits": [ 164 ]
|
|
},
|
|
"CH0_HDOUTN": {
|
|
"direction": "output",
|
|
"bits": [ 165 ]
|
|
},
|
|
"CH1_HDOUTN": {
|
|
"direction": "output",
|
|
"bits": [ 166 ]
|
|
},
|
|
"D_TXBIT_CLKP_TO_ND": {
|
|
"direction": "output",
|
|
"bits": [ 167 ]
|
|
},
|
|
"D_TXBIT_CLKN_TO_ND": {
|
|
"direction": "output",
|
|
"bits": [ 168 ]
|
|
},
|
|
"D_SYNC_PULSE2ND": {
|
|
"direction": "output",
|
|
"bits": [ 169 ]
|
|
},
|
|
"D_TXPLL_LOL_TO_ND": {
|
|
"direction": "output",
|
|
"bits": [ 170 ]
|
|
},
|
|
"CH0_FF_RX_F_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 171 ]
|
|
},
|
|
"CH1_FF_RX_F_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 172 ]
|
|
},
|
|
"CH0_FF_RX_H_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 173 ]
|
|
},
|
|
"CH1_FF_RX_H_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 174 ]
|
|
},
|
|
"CH0_FF_TX_F_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 175 ]
|
|
},
|
|
"CH1_FF_TX_F_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 176 ]
|
|
},
|
|
"CH0_FF_TX_H_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 177 ]
|
|
},
|
|
"CH1_FF_TX_H_CLK": {
|
|
"direction": "output",
|
|
"bits": [ 178 ]
|
|
},
|
|
"CH0_FF_RX_PCLK": {
|
|
"direction": "output",
|
|
"bits": [ 179 ]
|
|
},
|
|
"CH1_FF_RX_PCLK": {
|
|
"direction": "output",
|
|
"bits": [ 180 ]
|
|
},
|
|
"CH0_FF_TX_PCLK": {
|
|
"direction": "output",
|
|
"bits": [ 181 ]
|
|
},
|
|
"CH1_FF_TX_PCLK": {
|
|
"direction": "output",
|
|
"bits": [ 182 ]
|
|
},
|
|
"CH0_FF_RX_D_0": {
|
|
"direction": "output",
|
|
"bits": [ 183 ]
|
|
},
|
|
"CH1_FF_RX_D_0": {
|
|
"direction": "output",
|
|
"bits": [ 184 ]
|
|
},
|
|
"CH0_FF_RX_D_1": {
|
|
"direction": "output",
|
|
"bits": [ 185 ]
|
|
},
|
|
"CH1_FF_RX_D_1": {
|
|
"direction": "output",
|
|
"bits": [ 186 ]
|
|
},
|
|
"CH0_FF_RX_D_2": {
|
|
"direction": "output",
|
|
"bits": [ 187 ]
|
|
},
|
|
"CH1_FF_RX_D_2": {
|
|
"direction": "output",
|
|
"bits": [ 188 ]
|
|
},
|
|
"CH0_FF_RX_D_3": {
|
|
"direction": "output",
|
|
"bits": [ 189 ]
|
|
},
|
|
"CH1_FF_RX_D_3": {
|
|
"direction": "output",
|
|
"bits": [ 190 ]
|
|
},
|
|
"CH0_FF_RX_D_4": {
|
|
"direction": "output",
|
|
"bits": [ 191 ]
|
|
},
|
|
"CH1_FF_RX_D_4": {
|
|
"direction": "output",
|
|
"bits": [ 192 ]
|
|
},
|
|
"CH0_FF_RX_D_5": {
|
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|
"CLK2_DIV": "ENABLED",
|
|
"CLK3_DIV": "ENABLED",
|
|
"GSR": "ENABLED",
|
|
"HIGHSPEED_CLK": "NONE",
|
|
"MULT_BYPASS": "DISABLED",
|
|
"REG_INPUTA_CE": "CE0",
|
|
"REG_INPUTA_CLK": "NONE",
|
|
"REG_INPUTA_RST": "RST0",
|
|
"REG_INPUTB_CE": "CE0",
|
|
"REG_INPUTB_CLK": "NONE",
|
|
"REG_INPUTB_RST": "RST0",
|
|
"REG_INPUTC_CE": "CE0",
|
|
"REG_INPUTC_CLK": "NONE",
|
|
"REG_INPUTC_RST": "RST0",
|
|
"REG_OUTPUT_CE": "CE0",
|
|
"REG_OUTPUT_CLK": "NONE",
|
|
"REG_OUTPUT_RST": "RST0",
|
|
"REG_PIPELINE_CE": "CE0",
|
|
"REG_PIPELINE_CLK": "NONE",
|
|
"REG_PIPELINE_RST": "RST0",
|
|
"RESETMODE": "SYNC",
|
|
"SOURCEB_MODE": "B_SHIFT"
|
|
},
|
|
"ports": {
|
|
"A17": {
|
|
"direction": "input",
|
|
"bits": [ 2 ]
|
|
},
|
|
"A16": {
|
|
"direction": "input",
|
|
"bits": [ 3 ]
|
|
},
|
|
"A15": {
|
|
"direction": "input",
|
|
"bits": [ 4 ]
|
|
},
|
|
"A14": {
|
|
"direction": "input",
|
|
"bits": [ 5 ]
|
|
},
|
|
"A13": {
|
|
"direction": "input",
|
|
"bits": [ 6 ]
|
|
},
|
|
"A12": {
|
|
"direction": "input",
|
|
"bits": [ 7 ]
|
|
},
|
|
"A11": {
|
|
"direction": "input",
|
|
"bits": [ 8 ]
|
|
},
|
|
"A10": {
|
|
"direction": "input",
|
|
"bits": [ 9 ]
|
|
},
|
|
"A9": {
|
|
"direction": "input",
|
|
"bits": [ 10 ]
|
|
},
|
|
"A8": {
|
|
"direction": "input",
|
|
"bits": [ 11 ]
|
|
},
|
|
"A7": {
|
|
"direction": "input",
|
|
"bits": [ 12 ]
|
|
},
|
|
"A6": {
|
|
"direction": "input",
|
|
"bits": [ 13 ]
|
|
},
|
|
"A5": {
|
|
"direction": "input",
|
|
"bits": [ 14 ]
|
|
},
|
|
"A4": {
|
|
"direction": "input",
|
|
"bits": [ 15 ]
|
|
},
|
|
"A3": {
|
|
"direction": "input",
|
|
"bits": [ 16 ]
|
|
},
|
|
"A2": {
|
|
"direction": "input",
|
|
"bits": [ 17 ]
|
|
},
|
|
"A1": {
|
|
"direction": "input",
|
|
"bits": [ 18 ]
|
|
},
|
|
"A0": {
|
|
"direction": "input",
|
|
"bits": [ 19 ]
|
|
},
|
|
"B17": {
|
|
"direction": "input",
|
|
"bits": [ 20 ]
|
|
},
|
|
"B16": {
|
|
"direction": "input",
|
|
"bits": [ 21 ]
|
|
},
|
|
"B15": {
|
|
"direction": "input",
|
|
"bits": [ 22 ]
|
|
},
|
|
"B14": {
|
|
"direction": "input",
|
|
"bits": [ 23 ]
|
|
},
|
|
"B13": {
|
|
"direction": "input",
|
|
"bits": [ 24 ]
|
|
},
|
|
"B12": {
|
|
"direction": "input",
|
|
"bits": [ 25 ]
|
|
},
|
|
"B11": {
|
|
"direction": "input",
|
|
"bits": [ 26 ]
|
|
},
|
|
"B10": {
|
|
"direction": "input",
|
|
"bits": [ 27 ]
|
|
},
|
|
"B9": {
|
|
"direction": "input",
|
|
"bits": [ 28 ]
|
|
},
|
|
"B8": {
|
|
"direction": "input",
|
|
"bits": [ 29 ]
|
|
},
|
|
"B7": {
|
|
"direction": "input",
|
|
"bits": [ 30 ]
|
|
},
|
|
"B6": {
|
|
"direction": "input",
|
|
"bits": [ 31 ]
|
|
},
|
|
"B5": {
|
|
"direction": "input",
|
|
"bits": [ 32 ]
|
|
},
|
|
"B4": {
|
|
"direction": "input",
|
|
"bits": [ 33 ]
|
|
},
|
|
"B3": {
|
|
"direction": "input",
|
|
"bits": [ 34 ]
|
|
},
|
|
"B2": {
|
|
"direction": "input",
|
|
"bits": [ 35 ]
|
|
},
|
|
"B1": {
|
|
"direction": "input",
|
|
"bits": [ 36 ]
|
|
},
|
|
"B0": {
|
|
"direction": "input",
|
|
"bits": [ 37 ]
|
|
},
|
|
"C17": {
|
|
"direction": "input",
|
|
"bits": [ 38 ]
|
|
},
|
|
"C16": {
|
|
"direction": "input",
|
|
"bits": [ 39 ]
|
|
},
|
|
"C15": {
|
|
"direction": "input",
|
|
"bits": [ 40 ]
|
|
},
|
|
"C14": {
|
|
"direction": "input",
|
|
"bits": [ 41 ]
|
|
},
|
|
"C13": {
|
|
"direction": "input",
|
|
"bits": [ 42 ]
|
|
},
|
|
"C12": {
|
|
"direction": "input",
|
|
"bits": [ 43 ]
|
|
},
|
|
"C11": {
|
|
"direction": "input",
|
|
"bits": [ 44 ]
|
|
},
|
|
"C10": {
|
|
"direction": "input",
|
|
"bits": [ 45 ]
|
|
},
|
|
"C9": {
|
|
"direction": "input",
|
|
"bits": [ 46 ]
|
|
},
|
|
"C8": {
|
|
"direction": "input",
|
|
"bits": [ 47 ]
|
|
},
|
|
"C7": {
|
|
"direction": "input",
|
|
"bits": [ 48 ]
|
|
},
|
|
"C6": {
|
|
"direction": "input",
|
|
"bits": [ 49 ]
|
|
},
|
|
"C5": {
|
|
"direction": "input",
|
|
"bits": [ 50 ]
|
|
},
|
|
"C4": {
|
|
"direction": "input",
|
|
"bits": [ 51 ]
|
|
},
|
|
"C3": {
|
|
"direction": "input",
|
|
"bits": [ 52 ]
|
|
},
|
|
"C2": {
|
|
"direction": "input",
|
|
"bits": [ 53 ]
|
|
},
|
|
"C1": {
|
|
"direction": "input",
|
|
"bits": [ 54 ]
|
|
},
|
|
"C0": {
|
|
"direction": "input",
|
|
"bits": [ 55 ]
|
|
},
|
|
"SIGNEDA": {
|
|
"direction": "input",
|
|
"bits": [ 56 ]
|
|
},
|
|
"SIGNEDB": {
|
|
"direction": "input",
|
|
"bits": [ 57 ]
|
|
},
|
|
"SOURCEA": {
|
|
"direction": "input",
|
|
"bits": [ 58 ]
|
|
},
|
|
"SOURCEB": {
|
|
"direction": "input",
|
|
"bits": [ 59 ]
|
|
},
|
|
"CLK3": {
|
|
"direction": "input",
|
|
"bits": [ 60 ]
|
|
},
|
|
"CLK2": {
|
|
"direction": "input",
|
|
"bits": [ 61 ]
|
|
},
|
|
"CLK1": {
|
|
"direction": "input",
|
|
"bits": [ 62 ]
|
|
},
|
|
"CLK0": {
|
|
"direction": "input",
|
|
"bits": [ 63 ]
|
|
},
|
|
"CE3": {
|
|
"direction": "input",
|
|
"bits": [ 64 ]
|
|
},
|
|
"CE2": {
|
|
"direction": "input",
|
|
"bits": [ 65 ]
|
|
},
|
|
"CE1": {
|
|
"direction": "input",
|
|
"bits": [ 66 ]
|
|
},
|
|
"CE0": {
|
|
"direction": "input",
|
|
"bits": [ 67 ]
|
|
},
|
|
"RST3": {
|
|
"direction": "input",
|
|
"bits": [ 68 ]
|
|
},
|
|
"RST2": {
|
|
"direction": "input",
|
|
"bits": [ 69 ]
|
|
},
|
|
"RST1": {
|
|
"direction": "input",
|
|
"bits": [ 70 ]
|
|
},
|
|
"RST0": {
|
|
"direction": "input",
|
|
"bits": [ 71 ]
|
|
},
|
|
"SRIA17": {
|
|
"direction": "input",
|
|
"bits": [ 72 ]
|
|
},
|
|
"SRIA16": {
|
|
"direction": "input",
|
|
"bits": [ 73 ]
|
|
},
|
|
"SRIA15": {
|
|
"direction": "input",
|
|
"bits": [ 74 ]
|
|
},
|
|
"SRIA14": {
|
|
"direction": "input",
|
|
"bits": [ 75 ]
|
|
},
|
|
"SRIA13": {
|
|
"direction": "input",
|
|
"bits": [ 76 ]
|
|
},
|
|
"SRIA12": {
|
|
"direction": "input",
|
|
"bits": [ 77 ]
|
|
},
|
|
"SRIA11": {
|
|
"direction": "input",
|
|
"bits": [ 78 ]
|
|
},
|
|
"SRIA10": {
|
|
"direction": "input",
|
|
"bits": [ 79 ]
|
|
},
|
|
"SRIA9": {
|
|
"direction": "input",
|
|
"bits": [ 80 ]
|
|
},
|
|
"SRIA8": {
|
|
"direction": "input",
|
|
"bits": [ 81 ]
|
|
},
|
|
"SRIA7": {
|
|
"direction": "input",
|
|
"bits": [ 82 ]
|
|
},
|
|
"SRIA6": {
|
|
"direction": "input",
|
|
"bits": [ 83 ]
|
|
},
|
|
"SRIA5": {
|
|
"direction": "input",
|
|
"bits": [ 84 ]
|
|
},
|
|
"SRIA4": {
|
|
"direction": "input",
|
|
"bits": [ 85 ]
|
|
},
|
|
"SRIA3": {
|
|
"direction": "input",
|
|
"bits": [ 86 ]
|
|
},
|
|
"SRIA2": {
|
|
"direction": "input",
|
|
"bits": [ 87 ]
|
|
},
|
|
"SRIA1": {
|
|
"direction": "input",
|
|
"bits": [ 88 ]
|
|
},
|
|
"SRIA0": {
|
|
"direction": "input",
|
|
"bits": [ 89 ]
|
|
},
|
|
"SRIB17": {
|
|
"direction": "input",
|
|
"bits": [ 90 ]
|
|
},
|
|
"SRIB16": {
|
|
"direction": "input",
|
|
"bits": [ 91 ]
|
|
},
|
|
"SRIB15": {
|
|
"direction": "input",
|
|
"bits": [ 92 ]
|
|
},
|
|
"SRIB14": {
|
|
"direction": "input",
|
|
"bits": [ 93 ]
|
|
},
|
|
"SRIB13": {
|
|
"direction": "input",
|
|
"bits": [ 94 ]
|
|
},
|
|
"SRIB12": {
|
|
"direction": "input",
|
|
"bits": [ 95 ]
|
|
},
|
|
"SRIB11": {
|
|
"direction": "input",
|
|
"bits": [ 96 ]
|
|
},
|
|
"SRIB10": {
|
|
"direction": "input",
|
|
"bits": [ 97 ]
|
|
},
|
|
"SRIB9": {
|
|
"direction": "input",
|
|
"bits": [ 98 ]
|
|
},
|
|
"SRIB8": {
|
|
"direction": "input",
|
|
"bits": [ 99 ]
|
|
},
|
|
"SRIB7": {
|
|
"direction": "input",
|
|
"bits": [ 100 ]
|
|
},
|
|
"SRIB6": {
|
|
"direction": "input",
|
|
"bits": [ 101 ]
|
|
},
|
|
"SRIB5": {
|
|
"direction": "input",
|
|
"bits": [ 102 ]
|
|
},
|
|
"SRIB4": {
|
|
"direction": "input",
|
|
"bits": [ 103 ]
|
|
},
|
|
"SRIB3": {
|
|
"direction": "input",
|
|
"bits": [ 104 ]
|
|
},
|
|
"SRIB2": {
|
|
"direction": "input",
|
|
"bits": [ 105 ]
|
|
},
|
|
"SRIB1": {
|
|
"direction": "input",
|
|
"bits": [ 106 ]
|
|
},
|
|
"SRIB0": {
|
|
"direction": "input",
|
|
"bits": [ 107 ]
|
|
},
|
|
"SROA17": {
|
|
"direction": "output",
|
|
"bits": [ 108 ]
|
|
},
|
|
"SROA16": {
|
|
"direction": "output",
|
|
"bits": [ 109 ]
|
|
},
|
|
"SROA15": {
|
|
"direction": "output",
|
|
"bits": [ 110 ]
|
|
},
|
|
"SROA14": {
|
|
"direction": "output",
|
|
"bits": [ 111 ]
|
|
},
|
|
"SROA13": {
|
|
"direction": "output",
|
|
"bits": [ 112 ]
|
|
},
|
|
"SROA12": {
|
|
"direction": "output",
|
|
"bits": [ 113 ]
|
|
},
|
|
"SROA11": {
|
|
"direction": "output",
|
|
"bits": [ 114 ]
|
|
},
|
|
"SROA10": {
|
|
"direction": "output",
|
|
"bits": [ 115 ]
|
|
},
|
|
"SROA9": {
|
|
"direction": "output",
|
|
"bits": [ 116 ]
|
|
},
|
|
"SROA8": {
|
|
"direction": "output",
|
|
"bits": [ 117 ]
|
|
},
|
|
"SROA7": {
|
|
"direction": "output",
|
|
"bits": [ 118 ]
|
|
},
|
|
"SROA6": {
|
|
"direction": "output",
|
|
"bits": [ 119 ]
|
|
},
|
|
"SROA5": {
|
|
"direction": "output",
|
|
"bits": [ 120 ]
|
|
},
|
|
"SROA4": {
|
|
"direction": "output",
|
|
"bits": [ 121 ]
|
|
},
|
|
"SROA3": {
|
|
"direction": "output",
|
|
"bits": [ 122 ]
|
|
},
|
|
"SROA2": {
|
|
"direction": "output",
|
|
"bits": [ 123 ]
|
|
},
|
|
"SROA1": {
|
|
"direction": "output",
|
|
"bits": [ 124 ]
|
|
},
|
|
"SROA0": {
|
|
"direction": "output",
|
|
"bits": [ 125 ]
|
|
},
|
|
"SROB17": {
|
|
"direction": "output",
|
|
"bits": [ 126 ]
|
|
},
|
|
"SROB16": {
|
|
"direction": "output",
|
|
"bits": [ 127 ]
|
|
},
|
|
"SROB15": {
|
|
"direction": "output",
|
|
"bits": [ 128 ]
|
|
},
|
|
"SROB14": {
|
|
"direction": "output",
|
|
"bits": [ 129 ]
|
|
},
|
|
"SROB13": {
|
|
"direction": "output",
|
|
"bits": [ 130 ]
|
|
},
|
|
"SROB12": {
|
|
"direction": "output",
|
|
"bits": [ 131 ]
|
|
},
|
|
"SROB11": {
|
|
"direction": "output",
|
|
"bits": [ 132 ]
|
|
},
|
|
"SROB10": {
|
|
"direction": "output",
|
|
"bits": [ 133 ]
|
|
},
|
|
"SROB9": {
|
|
"direction": "output",
|
|
"bits": [ 134 ]
|
|
},
|
|
"SROB8": {
|
|
"direction": "output",
|
|
"bits": [ 135 ]
|
|
},
|
|
"SROB7": {
|
|
"direction": "output",
|
|
"bits": [ 136 ]
|
|
},
|
|
"SROB6": {
|
|
"direction": "output",
|
|
"bits": [ 137 ]
|
|
},
|
|
"SROB5": {
|
|
"direction": "output",
|
|
"bits": [ 138 ]
|
|
},
|
|
"SROB4": {
|
|
"direction": "output",
|
|
"bits": [ 139 ]
|
|
},
|
|
"SROB3": {
|
|
"direction": "output",
|
|
"bits": [ 140 ]
|
|
},
|
|
"SROB2": {
|
|
"direction": "output",
|
|
"bits": [ 141 ]
|
|
},
|
|
"SROB1": {
|
|
"direction": "output",
|
|
"bits": [ 142 ]
|
|
},
|
|
"SROB0": {
|
|
"direction": "output",
|
|
"bits": [ 143 ]
|
|
},
|
|
"ROA17": {
|
|
"direction": "output",
|
|
"bits": [ 144 ]
|
|
},
|
|
"ROA16": {
|
|
"direction": "output",
|
|
"bits": [ 145 ]
|
|
},
|
|
"ROA15": {
|
|
"direction": "output",
|
|
"bits": [ 146 ]
|
|
},
|
|
"ROA14": {
|
|
"direction": "output",
|
|
"bits": [ 147 ]
|
|
},
|
|
"ROA13": {
|
|
"direction": "output",
|
|
"bits": [ 148 ]
|
|
},
|
|
"ROA12": {
|
|
"direction": "output",
|
|
"bits": [ 149 ]
|
|
},
|
|
"ROA11": {
|
|
"direction": "output",
|
|
"bits": [ 150 ]
|
|
},
|
|
"ROA10": {
|
|
"direction": "output",
|
|
"bits": [ 151 ]
|
|
},
|
|
"ROA9": {
|
|
"direction": "output",
|
|
"bits": [ 152 ]
|
|
},
|
|
"ROA8": {
|
|
"direction": "output",
|
|
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