micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
181 lines
7.9 KiB
Plaintext
181 lines
7.9 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 40/43848 0%
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Info: logic LUTs: 16/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 16/ 5481 0%
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Info: RAMW LUTs: 8/10962 0%
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Info: Total DFFs: 56/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 32 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x66fb0815
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 56/ 43848 0%
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Info: TRELLIS_COMB: 42/ 43848 0%
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Info: TRELLIS_RAMW: 4/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 45 cells, random placement wirelen = 4472.
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Info: at initial placer iter 0, wirelen = 1154
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Info: at initial placer iter 1, wirelen = 977
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Info: at initial placer iter 2, wirelen = 954
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Info: at initial placer iter 3, wirelen = 946
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 940, spread = 976, legal = 985; time = 0.00s
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Info: HeAP Placer Time: 0.02s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 985
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Info: at iteration #5: temp = 0.000000, timing cost = 27, wirelen = 677
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Info: at iteration #10: temp = 0.000000, timing cost = 17, wirelen = 683
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Info: at iteration #13: temp = 0.000000, timing cost = 15, wirelen = 686
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Info: SA placement time 0.01s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 611.62 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.67 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.28 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10865, 10909) |*****
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Info: [ 10909, 10953) |
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Info: [ 10953, 10997) |************
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Info: [ 10997, 11041) |
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Info: [ 11041, 11085) |*****
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Info: [ 11085, 11129) |****
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Info: [ 11129, 11173) |
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Info: [ 11173, 11217) |********
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Info: [ 11217, 11261) |*********************************************************
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Info: [ 11261, 11305) |
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Info: [ 11305, 11349) |**************
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Info: [ 11349, 11393) |
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Info: [ 11393, 11437) |*********
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Info: [ 11437, 11481) |
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Info: [ 11481, 11525) |***********
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Info: [ 11525, 11569) |****
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Info: [ 11569, 11613) |********************
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Info: [ 11613, 11657) |
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Info: [ 11657, 11701) |
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Info: [ 11701, 11745) |*********
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Info: Checksum: 0x0346d215
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 301 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 322 | 18 304 | 18 304 | 0| 0.04 0.04|
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Info: Routing complete.
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Info: Router1 time 0.04s
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Info: Checksum: 0xd78872d0
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_3.Q
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Info: routing 1.09 1.48 Net fill_addr_flat[1] (8,28) -> (6,30)
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Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0$DPRAM_COMB2.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:27.24-27.29
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Info: logic 0.18 1.66 Source dut.GEN_SLOT[0].GEN_LANE[0].mem.0.0$DPRAM_COMB2.F
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Info: routing 0.12 1.78 Net dut.GEN_SLOT[0].GEN_LANE[0].mem.0.1_DO[2] (6,30) -> (6,30)
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Info: Sink dut.GEN_SLOT[0].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_7.DI
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Info: setup 0.00 1.78 Source dut.GEN_SLOT[0].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_7.DI
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Info: 0.57 ns logic, 1.20 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rst$tr_io.O
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Info: routing 4.21 4.21 Net rst$TRELLIS_IO_IN (90,29) -> (8,28)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_5.C
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:13.17-13.20
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Info: logic 0.18 4.39 Source seed_LUT4_B_Z_LUT4_Z_5.F
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Info: routing 0.12 4.51 Net seed_LUT4_B_Z[1] (8,28) -> (8,28)
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Info: Sink lfsr_TRELLIS_FF_Q_3.DI
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Info: setup 0.00 4.51 Source lfsr_TRELLIS_FF_Q_3.DI
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Info: 0.18 ns logic, 4.33 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
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Info: routing 3.76 4.16 Net checksum[1]$TRELLIS_IO_OUT (8,31) -> (90,32)
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Info: Sink checksum[1]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:40.15-40.18
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Info: 0.40 ns logic, 3.76 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 562.11 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.51 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.16 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10721, 10775) |****
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Info: [ 10775, 10829) |
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Info: [ 10829, 10883) |****
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Info: [ 10883, 10937) |****
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Info: [ 10937, 10991) |**********
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Info: [ 10991, 11045) |
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Info: [ 11045, 11099) |******
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Info: [ 11099, 11153) |*
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Info: [ 11153, 11207) |*******************
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Info: [ 11207, 11261) |***********
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Info: [ 11261, 11315) |*****************
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Info: [ 11315, 11369) |*****************
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Info: [ 11369, 11423) |**********
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Info: [ 11423, 11477) |*********
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Info: [ 11477, 11531) |****
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Info: [ 11531, 11585) |**************
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Info: [ 11585, 11639) |******
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Info: [ 11639, 11693) |**********
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Info: [ 11693, 11747) |******
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Info: [ 11747, 11801) |******
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Info: Program finished normally.
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