micheleandClaude Sonnet 5
8d83d97bde
Memory upgrade, at the user's own explicit request: Alliance Memory AS4C4M16SA-6TIN (64Mbit/8MB) -> AS4C32M16SB-7BIN (512Mbit/64MB, 54-ball TFBGA), the largest same-family SDR SDRAM Alliance Memory offers. Real-datasheet-driven (whole AS4C4M16SA/AS4C8M16SA/AS4C16M16SA/ AS4C32M16SA family investigated): 13 row bits (was 12, one new FPGA pin sdram_a[12]/ball F1), 10 column bits (was 8), real -7-grade AC timing (tRCD/tRP improved to 15ns, tREFI halved to 7.8us for the doubled row count). sdram_controller.v and sdram_model.v gained real ROW_BITS/COL_BITS/BANK_BITS parameters (was hardcoded 12/8/2). ADDR_WIDTH widened 23->26 bits across the live instantiation tree. This required a real SPI protocol change (spi_host_bridge.v): a 26-bit byte address no longer fits in 3 bytes -- every address field widened 3->4 bytes (WRITE_JOB 15->18 payload bytes, WRITE_MEM/READ_MEM header 5->6 bytes). Found and fixed two real timing regressions via nextpnr-ecp5 P&R (not assumed): neural_director.v's own runtime-indexed demux write (ERR-0027, was silently synthesizing an extra MULT18X18D) and nms_activation_fill_ctrl_v3.v's own linear N_SLOTS-wide max-scan (ERR-0028, became dominant at N_SLOTS=8) -- both replaced with constant-indexed/tree-based equivalents, bit-exact same behavior, confirmed via full D-Stress N=2/4/8 regression (identical cycle counts). N_SLOTS=4 now fully closes timing at 64MHz (8/8 seeds); N_SLOTS=8 significantly improved but not yet fully reliable (5/8 seeds) -- honestly disclosed, not claimed complete. Full regression re-verified: sdram_controller (461/461, 18 configs), tb_sdram_boundary (21/21), D-Stress N=2/4/8 (bit-exact), spi_host_bridge (18/18), board-level SPI smoke test (11/11), unified backend (40/40). See hardware/v2/docs/MEMORY_UPGRADE_64MB_N8.md for the full investigation, and errors.log/decisions.log (ERR-0027, ERR-0028, DEC-0039) for the complete root-cause writeups. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
329 lines
15 KiB
Verilog
329 lines
15 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// NMS STEP16 -- behavioral model of Alliance Memory SDR SDRAM.
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//
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// MEMORY UPGRADE: retargeted from AS4C4M16SA-6TIN (64Mbit/8MB) to
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// AS4C32M16SA-7TIN (512Mbit/64MB, x16, 4 banks x 8192 rows x 1024
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// cols) -- ROW_BITS/COL_BITS/BANK_BITS are now real parameters
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// (matching sdram_controller.v's own parameterization) so this same
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// model supports either device by parameter alone. Real -7-grade AC
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// timing: tRCD=15ns, tRP=15ns, tRAS(min)=45ns, tRC=65ns, tMRD=2 CLK
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// (fixed, explicit CLK units per this datasheet), tREFI=64ms/8192
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// rows=7.8125us -- see sdram_controller.v's own header for the full
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// datasheet cross-reference.
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//
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// Real JEDEC command decode (CS#/RAS#/CAS#/WE#), real per-bank
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// state tracking (IDLE / ACTIVE with an open row), and REAL timing-
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// violation assertions (tRCD, tRP, tRAS-min, tRC, tMRD) -- this model
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// does not merely "accept whatever the controller sends"; it actively
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// checks the controller's own real compliance with datasheet timing,
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// same rigor this project applies to psram_model.v elsewhere. A
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// timing violation here is a genuine controller bug, not tolerated
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// silently.
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//
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// Refresh is tracked per-row (a real ROWS-row array of "last
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// refreshed at cycle N" timestamps) and checked against tREFI --
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// data itself is not modeled as decaying (unnecessary complexity for
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// this validation), but an insufficiently-refreshed row is flagged
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// via a real, visible warning/assertion, not silently ignored.
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//
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// CAS_LATENCY and BURST_LEN are read back from the real LOAD MODE
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// REGISTER command's own address bits (not assumed equal to the
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// controller's own parameters) -- this model independently decodes
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// the mode register exactly as real silicon would, so a controller
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// bug in the MRS encoding would be caught here too.
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// ============================================================
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module sdram_model #(
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parameter CLK_FREQ_MHZ = 64,
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parameter ROW_BITS = 13, // AS4C32M16SA: row address A0-A12
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parameter COL_BITS = 10, // AS4C32M16SA: column address A0-A9
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parameter BANK_BITS = 2 // BA0,BA1 -- fixed across this whole Alliance SDR family
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)(
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input wire clk,
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input wire cke,
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input wire cs_n,
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input wire ras_n,
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input wire cas_n,
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input wire we_n,
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input wire [BANK_BITS-1:0] ba,
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input wire [ROW_BITS-1:0] a,
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inout wire [15:0] dq,
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input wire [1:0] dqm
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);
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localparam BANKS = 1 << BANK_BITS;
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localparam ROWS = 1 << ROW_BITS;
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localparam COLS = 1 << COL_BITS;
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function integer ns_to_cycles;
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input integer ns;
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begin
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ns_to_cycles = (ns * CLK_FREQ_MHZ + 999) / 1000;
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end
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endfunction
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localparam T_RCD = ns_to_cycles(15);
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localparam T_RP = ns_to_cycles(15);
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localparam T_RAS_MIN= ns_to_cycles(45);
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localparam T_RC = ns_to_cycles(65);
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localparam T_MRD = 2; // tMRD = 2 CLK, fixed (see sdram_controller.v's own header)
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localparam T_REFI = ns_to_cycles(64000000 / ROWS + 1);
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reg [15:0] mem [0:BANKS*ROWS*COLS-1];
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// per-bank state
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reg bank_active [0:BANKS-1];
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reg [ROW_BITS-1:0] bank_row [0:BANKS-1];
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integer bank_active_since [0:BANKS-1]; // cycle ACTIVATE was issued
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integer bank_precharge_since [0:BANKS-1]; // cycle last PRECHARGE completed
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// mode register (decoded from a real LOAD MODE REGISTER command)
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reg [2:0] mr_burst_code;
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reg [2:0] mr_cas_latency;
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integer burst_len;
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integer cas_latency;
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integer cycle;
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always @(posedge clk) cycle <= cycle + 1;
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// refresh bookkeeping: last-refreshed cycle per row (across all
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// banks -- real SDRAM refreshes one row address across ALL banks
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// per AUTO REFRESH command)
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integer last_refresh_cycle [0:ROWS-1];
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integer last_any_refresh_cycle;
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// ---- command decode ----
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wire cmd_active = !cs_n && !ras_n && cas_n && we_n;
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wire cmd_read = !cs_n && ras_n && !cas_n && we_n;
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wire cmd_write = !cs_n && ras_n && !cas_n && !we_n;
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wire cmd_precharge= !cs_n && !ras_n && cas_n && !we_n;
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wire cmd_refresh = !cs_n && !ras_n && !cas_n && we_n;
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wire cmd_mrs = !cs_n && !ras_n && !cas_n && !we_n;
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// ---- read burst delivery (CAS-latency-delayed shift pipeline) ----
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reg [15:0] rd_pipe [0:15]; // generous depth, only first `cas_latency` entries meaningful
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reg rd_valid_pipe [0:15];
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// combinational output stage: rd_pipe[0] IS the chip's own output
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// register in real SDR SDRAM, already counted inside CAS_LATENCY --
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// driving dq_out through one more registered NBA stage here would
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// silently add an extra cycle of latency the controller doesn't
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// expect (a real bug found by tracing a stubborn one-cycle-late
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// read-data mismatch against the controller's own CAS_LATENCY-cycle
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// wait_cnt derivation)
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wire [15:0] dq_out = rd_pipe[0];
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wire dq_out_en = rd_valid_pipe[0];
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assign dq = dq_out_en ? dq_out : 16'hzzzz;
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// active read-burst tracking (for auto-precharge/address auto-increment)
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reg rd_burst_active;
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reg [BANK_BITS-1:0] rd_bank;
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reg [ROW_BITS-1:0] rd_row;
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reg [COL_BITS-1:0] rd_col;
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integer rd_remaining;
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reg rd_autoprecharge;
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reg wr_burst_active;
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reg [BANK_BITS-1:0] wr_bank;
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reg [ROW_BITS-1:0] wr_row;
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reg [COL_BITS-1:0] wr_col;
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integer wr_remaining;
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reg wr_autoprecharge;
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integer i;
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initial begin
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cycle = 0;
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last_any_refresh_cycle = 0;
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burst_len = 1; cas_latency = 3;
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rd_burst_active = 0; wr_burst_active = 0;
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for (i = 0; i < BANKS; i = i + 1) begin
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bank_active[i] = 0; bank_active_since[i] = -1000000; bank_precharge_since[i] = 0;
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end
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for (i = 0; i < ROWS; i = i + 1) last_refresh_cycle[i] = 0;
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for (i = 0; i < 16; i = i + 1) begin rd_pipe[i] = 0; rd_valid_pipe[i] = 0; end
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end
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// Combinational "about to insert a freshly-read word into the
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// CAS-latency pipe this cycle" signals, computed from the
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// CURRENT (pre-edge) burst-tracking registers -- kept OUTSIDE the
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// always block and fed into a single, conflict-free per-index
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// shift-or-insert assignment below (an earlier draft assigned
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// rd_pipe[cas_latency-1] from BOTH the generic shift loop AND a
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// separate insert statement in the same always block -- two NBAs
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// to the same array element in the same time step, undefined/
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// tool-dependent behavior, a real bug caught before simulation
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// even ran, by inspection).
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wire pipe_insert = rd_burst_active;
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wire [15:0] pipe_insert_val = mem[rd_bank*ROWS*COLS + rd_row*COLS + rd_col];
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always @(posedge clk) begin
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// ---- shift the CAS-latency read pipeline every cycle, with
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// AT MOST one insertion point per cycle (index cas_latency-1),
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// never both a shift-in and an insert targeting the same
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// index ----
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for (i = 0; i < 15; i = i + 1) begin
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if (pipe_insert && i == cas_latency-1) begin
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rd_pipe[i] <= pipe_insert_val;
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rd_valid_pipe[i] <= 1'b1;
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end else begin
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rd_pipe[i] <= rd_pipe[i+1];
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rd_valid_pipe[i] <= rd_valid_pipe[i+1];
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end
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end
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rd_pipe[15] <= 16'h0000;
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rd_valid_pipe[15] <= 1'b0;
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if (!cke) begin
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// CKE low: real part would be in power-down/self-refresh;
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// not exercised by this controller (CKE held high always)
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end else begin
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if (cmd_active) begin
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// real timing check: bank must be idle, and the
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// PREVIOUS precharge (if any) must satisfy tRP before
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// this activate.
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if (bank_active[ba])
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$display("SDRAM_MODEL VIOLATION @%0t: ACTIVATE to bank %0d while already active (row %0d)", $time, ba, bank_row[ba]);
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if ((cycle - bank_precharge_since[ba]) < T_RP && bank_precharge_since[ba] != 0)
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$display("SDRAM_MODEL VIOLATION @%0t: tRP violated on bank %0d (%0d cycles since precharge, need %0d)",
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$time, ba, cycle-bank_precharge_since[ba], T_RP);
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bank_active[ba] <= 1'b1;
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bank_row[ba] <= a;
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bank_active_since[ba] <= cycle;
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end
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if (cmd_precharge) begin
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// A10=1 -> precharge all banks; else just `ba`
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for (i = 0; i < BANKS; i = i + 1) begin
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if (a[10] || i == ba) begin
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if (bank_active[i] && ((cycle - bank_active_since[i]) < T_RAS_MIN))
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$display("SDRAM_MODEL VIOLATION @%0t: tRAS(min) violated on bank %0d (%0d cycles since activate, need %0d)",
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$time, i, cycle-bank_active_since[i], T_RAS_MIN);
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bank_active[i] <= 1'b0;
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bank_precharge_since[i] <= cycle;
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end
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end
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end
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if (cmd_refresh) begin
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if ((cycle - last_any_refresh_cycle) > T_REFI && last_any_refresh_cycle != 0)
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$display("SDRAM_MODEL WARNING @%0t: AUTO REFRESH spacing %0d cycles exceeds tREFI=%0d",
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$time, cycle-last_any_refresh_cycle, T_REFI);
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last_any_refresh_cycle <= cycle;
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end
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if (cmd_mrs) begin
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mr_burst_code <= a[2:0];
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mr_cas_latency <= a[6:4];
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burst_len <= (a[2:0]==3'b000) ? 1 : (a[2:0]==3'b001) ? 2 :
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(a[2:0]==3'b010) ? 4 : (a[2:0]==3'b011) ? 8 : 1;
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cas_latency <= (a[6:4]==3'b011) ? 3 : (a[6:4]==3'b010) ? 2 : 3;
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end
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if (cmd_read || cmd_write) begin
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if (!bank_active[ba])
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$display("SDRAM_MODEL VIOLATION @%0t: %s to bank %0d with no active row", $time, cmd_read?"READ":"WRITE", ba);
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else if (bank_row[ba] !== a[ROW_BITS-1:0] && 1'b0) begin
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// column command doesn't carry a row -- nothing to
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// check here beyond bank-active, real row match is
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// implicit (the address IS the column within the
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// already-open row)
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end
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if ((cycle - bank_active_since[ba]) < T_RCD)
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$display("SDRAM_MODEL VIOLATION @%0t: tRCD violated on bank %0d (%0d cycles since activate, need %0d)",
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$time, ba, cycle-bank_active_since[ba], T_RCD);
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if (cmd_read) begin
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// real SDR SDRAM: CAS latency counts cycles from the
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// READ command itself -- insert the first word's mem
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// lookup right here (command-decode cycle) instead of
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// waiting for rd_burst_active to become visible one
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// cycle later, which added a spurious extra pipeline
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// stage and made every read arrive one cycle late
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// (the same bug class as the write-side fix below,
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// found by tracing the cycle-exact mismatch against
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// the controller's own CAS_LATENCY-cycle wait_cnt)
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rd_pipe[cas_latency-1] <= mem[ba*ROWS*COLS + bank_row[ba]*COLS + a[COL_BITS-1:0]];
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rd_valid_pipe[cas_latency-1] <= 1'b1;
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if (burst_len == 1) begin
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rd_burst_active <= 1'b0;
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if (a[10]) begin
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bank_active[ba] <= 1'b0;
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bank_precharge_since[ba] <= cycle;
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end
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end else begin
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rd_bank <= ba; rd_row <= bank_row[ba]; rd_col <= a[COL_BITS-1:0] + 1'b1;
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rd_remaining <= burst_len - 1'b1; rd_autoprecharge <= a[10];
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rd_burst_active <= 1'b1;
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end
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end else begin
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// real SDR SDRAM: the first write word is presented on
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// DQ CONCURRENTLY with the WRITE command itself, not one
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// cycle later -- capture it right here (in the same
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// cycle the command is decoded) instead of waiting for
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// wr_burst_active, which would silently drop word0
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if (dqm[0] == 1'b0) mem[ba*ROWS*COLS + bank_row[ba]*COLS + a[COL_BITS-1:0]][7:0] <= dq[7:0];
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if (dqm[1] == 1'b0) mem[ba*ROWS*COLS + bank_row[ba]*COLS + a[COL_BITS-1:0]][15:8] <= dq[15:8];
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if (burst_len == 1) begin
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wr_burst_active <= 1'b0;
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if (a[10]) begin
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bank_active[ba] <= 1'b0;
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bank_precharge_since[ba] <= cycle;
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end
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end else begin
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wr_bank <= ba; wr_row <= bank_row[ba]; wr_col <= a[COL_BITS-1:0] + 1'b1;
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wr_remaining <= burst_len - 1'b1; wr_autoprecharge <= a[10];
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wr_burst_active <= 1'b1;
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end
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end
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end
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// ---- service an in-progress read burst: one word/cycle,
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// the actual mem[] read + pipe insertion happens above
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// (pipe_insert/pipe_insert_val, combinational from THIS
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// cycle's rd_bank/rd_row/rd_col) -- here we only advance
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// the column pointer and burst-remaining bookkeeping ----
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if (rd_burst_active) begin
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rd_col <= rd_col + 1'b1;
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rd_remaining <= rd_remaining - 1;
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if (rd_remaining == 1) begin
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rd_burst_active <= 1'b0;
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if (rd_autoprecharge) begin
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bank_active[rd_bank] <= 1'b0;
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bank_precharge_since[rd_bank] <= cycle;
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end
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end
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end
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// ---- service an in-progress write burst: one word/cycle
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// from dq ----
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if (wr_burst_active) begin
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if (dqm[0] == 1'b0) mem[wr_bank*ROWS*COLS + wr_row*COLS + wr_col][7:0] <= dq[7:0];
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if (dqm[1] == 1'b0) mem[wr_bank*ROWS*COLS + wr_row*COLS + wr_col][15:8] <= dq[15:8];
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wr_col <= wr_col + 1'b1;
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wr_remaining <= wr_remaining - 1;
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if (wr_remaining == 1) begin
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wr_burst_active <= 1'b0;
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if (wr_autoprecharge) begin
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bank_active[wr_bank] <= 1'b0;
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bank_precharge_since[wr_bank] <= cycle;
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end
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end
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end
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end
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end
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// testbench-only backdoor access (poke/peek), matching this
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// project's own established convention elsewhere (psram_model.v)
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task automatic backdoor_write(input [BANK_BITS-1:0] tb_bank, input [ROW_BITS-1:0] tb_row, input [COL_BITS-1:0] tb_col, input [15:0] val);
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begin
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mem[tb_bank*ROWS*COLS + tb_row*COLS + tb_col] = val;
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end
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endtask
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function automatic [15:0] backdoor_read(input [BANK_BITS-1:0] tb_bank, input [ROW_BITS-1:0] tb_row, input [COL_BITS-1:0] tb_col);
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begin
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backdoor_read = mem[tb_bank*ROWS*COLS + tb_row*COLS + tb_col];
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end
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endfunction
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endmodule
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