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micheleandClaude Sonnet 5 55c827bedf feat: PSRAM page-mode reads + graph engine (Type #2) + real pinout/IRQ pins 
PSRAM page-mode read burst support in psram_controller.v: enables the
ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register
software-access sequence at boot (disabled by default on the real
chip), then keeps CE#/OE# asserted after a read so a same-page
continuation only pays tAPA (20ns) instead of a full tAA (70ns)
random access, with automatic tCEM-safe session closing. Only a WRITE
closes the page -- byte-enable changes do not, since
int8_memory_access.v alternates them on nearly every access and an
early implementation attempt that treated them as a close condition
measured a real regression (53.25->61.25 cycles/edge) before being
corrected (53.25->37.53 cycles/edge, +42% gather bandwidth).
sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement
(with a real Verilog same-timestep event-ordering race found and
fixed via a #0 sync) so the regression proves real timing compliance,
not just data correctness. New sim/psram_page_mode_tb.v; full 26-file
regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on
the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and
65.13MHz (P8) -- still under the 80MHz target but not regressed, with
the critical path confirmed (not assumed) to remain entirely inside
neuron_parallel's accumulate chain, never psram_controller.

Also includes this session's other already-validated work: the graph
engine (Type #2 sparse-graph network: act_buffer, graph_engine,
netasm host assembler), real CABGA381 pinout (.lpf, place&route
verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing
closure logs -- all previously uncommitted, documented in WORKLOG.md.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
2026-09-03 17:12:05 +02:00

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/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
-- Executing script file `synth/ecp5/graph_engine/synth.ys' --
1. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v' to AST representation.
Generating RTLIL representation for module `\act_buffer'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v' to AST representation.
Generating RTLIL representation for module `\mac_unit'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v' to AST representation.
Generating RTLIL representation for module `\mac8'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v' to AST representation.
Generating RTLIL representation for module `\neuron_parallel'.
Successfully finished Verilog frontend.
5. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v
Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v' to AST representation.
Generating RTLIL representation for module `\graph_engine'.
Successfully finished Verilog frontend.
6. Executing HIERARCHY pass (managing design hierarchy).
6.1. Analyzing design hierarchy..
Top module: \graph_engine
Used module: \neuron_parallel
Used module: \mac8
Used module: \mac_unit
Used module: \act_buffer
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
6.2. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Generating RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Reprocessing module mac8 because instantiated module $paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit has become available.
Generating RTLIL representation for module `\mac8'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Parameter \PARALLEL = 8
6.3. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Parameter \PARALLEL = 8
Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
6.4. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'.
Parameter \DATA_WIDTH = 8
Parameter \N_INPUTS = 32
Parameter \PARALLEL = 8
Parameter \ACC_WIDTH = 32
Generating RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
Parameter \N_TOTAL = 4096
Parameter \DATA_WIDTH = 8
6.5. Executing AST frontend in derive mode using pre-parsed AST for module `\act_buffer'.
Parameter \N_TOTAL = 4096
Parameter \DATA_WIDTH = 8
Generating RTLIL representation for module `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer'.
6.6. Analyzing design hierarchy..
Top module: \graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: \mac8
Used module: \mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 16
Parameter \ACC_WIDTH = 40
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Parameter \PARALLEL = 8
Found cached RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
6.7. Analyzing design hierarchy..
Top module: \graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: \mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
6.8. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Generating RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Reprocessing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 because instantiated module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit has become available.
Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
6.9. Analyzing design hierarchy..
Top module: \graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: \mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
Parameter \DATA_WIDTH = 8
Parameter \ACC_WIDTH = 32
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
6.10. Analyzing design hierarchy..
Top module: \graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
6.11. Analyzing design hierarchy..
Top module: \graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Removing unused module `\mac8'.
Removing unused module `\neuron_parallel'.
Removing unused module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
Removing unused module `\mac_unit'.
Removing unused module `\act_buffer'.
Removed 5 unused modules.
7. Executing SYNTH_LATTICE pass.
7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\VLO'.
Generating RTLIL representation for module `\VHI'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\DP16KD'.
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
Generating RTLIL representation for module `\FD1P3AX'.
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
Generating RTLIL representation for module `\FD1P3AY'.
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
Generating RTLIL representation for module `\FD1P3BX'.
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
Generating RTLIL representation for module `\FD1P3DX'.
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
Generating RTLIL representation for module `\FD1P3IX'.
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
Generating RTLIL representation for module `\FD1P3JX'.
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
Generating RTLIL representation for module `\FD1S3AX'.
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
Generating RTLIL representation for module `\FD1S3AY'.
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
Generating RTLIL representation for module `\FD1S3BX'.
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
Generating RTLIL representation for module `\FD1S3DX'.
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
Generating RTLIL representation for module `\FD1S3IX'.
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
Generating RTLIL representation for module `\FD1S3JX'.
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
Generating RTLIL representation for module `\IFS1P3BX'.
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
Generating RTLIL representation for module `\IFS1P3DX'.
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
Generating RTLIL representation for module `\IFS1P3IX'.
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
Generating RTLIL representation for module `\IFS1P3JX'.
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
Generating RTLIL representation for module `\OFS1P3BX'.
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
Generating RTLIL representation for module `\OFS1P3DX'.
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
Generating RTLIL representation for module `\OFS1P3IX'.
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
Generating RTLIL representation for module `\OFS1P3JX'.
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
Generating RTLIL representation for module `\IB'.
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
Generating RTLIL representation for module `\IBPU'.
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
Generating RTLIL representation for module `\IBPD'.
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
Generating RTLIL representation for module `\OB'.
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
Generating RTLIL representation for module `\OBZ'.
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
Generating RTLIL representation for module `\OBZPU'.
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
Generating RTLIL representation for module `\OBZPD'.
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
Generating RTLIL representation for module `\OBCO'.
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
Generating RTLIL representation for module `\BB'.
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
Generating RTLIL representation for module `\BBPU'.
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
Generating RTLIL representation for module `\BBPD'.
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
Generating RTLIL representation for module `\ILVDS'.
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
7.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DCUA'.
Successfully finished Verilog frontend.
7.3. Executing HIERARCHY pass (managing design hierarchy).
7.3.1. Analyzing design hierarchy..
Top module: \graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
7.3.2. Analyzing design hierarchy..
Top module: \graph_engine
Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel
Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
Removed 0 unused modules.
7.4. Executing PROC pass (convert processes to netlists).
7.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
7.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 11 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126 in module graph_engine.
Marked 8 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468 in module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$479 in module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
Removed a total of 0 dead cases.
7.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 5 redundant assignments.
Promoted 98 assignments to connections.
7.4.4. Executing PROC_INIT pass (extract init attributes).
7.4.5. Executing PROC_ARST pass (detect async resets in processes).
7.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~29 debug messages>
7.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
1/108: $0\src_id_acc[15:0] [15:8]
2/108: $0\src_id_acc[15:0] [7:0]
3/108: $0\out_id_acc[15:0] [7:0]
4/108: $0\n_conn_acc[15:0] [7:0]
5/108: $0\conn_ptr_acc[23:0] [7:0]
6/108: $0\conn_ptr_acc[23:0] [23:16]
7/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_DATA[7:0]$271
8/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_ADDR[5:0]$270
9/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$269
10/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_DATA[7:0]$268
11/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_ADDR[5:0]$267
12/108: $1\ri[31:0]
13/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$260
14/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$259
15/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$258
16/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$257
17/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$256
18/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$255
19/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$254
20/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$253
21/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$252
22/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$251
23/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$250
24/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$249
25/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$248
26/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$247
27/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$246
28/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$245
29/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$244
30/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$243
31/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$242
32/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$241
33/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$240
34/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$239
35/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$238
36/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$237
37/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$236
38/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$235
39/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$234
40/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$233
41/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$232
42/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$231
43/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$230
44/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$229
45/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$228
46/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$227
47/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$226
48/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$225
49/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$224
50/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$223
51/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$222
52/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$221
53/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$220
54/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$219
55/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$218
56/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$217
57/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$216
58/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$215
59/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$214
60/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$213
61/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$212
62/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$211
63/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$210
64/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$209
65/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$208
66/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$207
67/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$206
68/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$205
69/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$204
70/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$203
71/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$202
72/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$201
73/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$200
74/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$199
75/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$198
76/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$197
77/108: $0\ram_req[0:0]
78/108: $0\neuron_start[0:0]
79/108: $0\act_wr_en[0:0]
80/108: $0\done[0:0]
81/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$266
82/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_DATA[7:0]$265
83/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_ADDR[5:0]$264
84/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$263
85/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_DATA[7:0]$262
86/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_ADDR[5:0]$261
87/108: $0\n_conn_padded_reg[15:0]
88/108: $0\activation_reg[1:0]
89/108: $0\bias_reg[7:0]
90/108: $0\act_wr_data[7:0]
91/108: $0\act_wr_addr[11:0]
92/108: $0\weight_acc[7:0]
93/108: $0\out_id_acc[15:0] [15:8]
94/108: $0\edge_byte_idx[1:0]
95/108: $0\conn_i[5:0]
96/108: $0\n_conn_acc[15:0] [15:8]
97/108: $0\conn_ptr_acc[23:0] [15:8]
98/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$272
99/108: $0\desc_byte_idx[3:0]
100/108: $0\desc_addr[22:0]
101/108: $0\neuron_idx[15:0]
102/108: $0\in_idx[15:0]
103/108: $0\state[3:0]
104/108: $0\ram_wdata[7:0]
105/108: $0\ram_addr[22:0]
106/108: $0\ram_wr[0:0]
107/108: $0\err[0:0]
108/108: $0\busy[0:0]
Creating decoders for process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468'.
1/5: $0\done[0:0]
2/5: $0\acc[31:0]
3/5: $0\group_index[1:0]
4/5: $0\busy[0:0]
5/5: $0\y[7:0]
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$551'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$549'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$547'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$545'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$543'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$541'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$539'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$538'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$537'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$536'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$535'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$534'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$533'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$532'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$531'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$530'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$529'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$528'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$527'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$526'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$525'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$524'.
Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$523'.
Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$486'.
Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$479'.
1/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$485
2/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_DATA[7:0]$484
3/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_ADDR[11:0]$483
7.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[24]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$551'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[17]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$549'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[16]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$547'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[11]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$545'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[10]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$543'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[9]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$541'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[8]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$539'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$538'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$537'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$536'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$535'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$534'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$533'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$532'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$531'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$530'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$529'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$528'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$527'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$526'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$525'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$524'.
No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$523'.
7.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\graph_engine.\busy' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1759' with positive edge clock.
Creating register for signal `\graph_engine.\done' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1760' with positive edge clock.
Creating register for signal `\graph_engine.\err' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1761' with positive edge clock.
Creating register for signal `\graph_engine.\ram_req' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1762' with positive edge clock.
Creating register for signal `\graph_engine.\ram_wr' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1763' with positive edge clock.
Creating register for signal `\graph_engine.\ram_addr' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1764' with positive edge clock.
Creating register for signal `\graph_engine.\ram_wdata' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1765' with positive edge clock.
Creating register for signal `\graph_engine.\state' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1766' with positive edge clock.
Creating register for signal `\graph_engine.\in_idx' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1767' with positive edge clock.
Creating register for signal `\graph_engine.\neuron_idx' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1768' with positive edge clock.
Creating register for signal `\graph_engine.\desc_addr' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1769' with positive edge clock.
Creating register for signal `\graph_engine.\desc_byte_idx' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1770' with positive edge clock.
Creating register for signal `\graph_engine.\conn_ptr_acc' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1771' with positive edge clock.
Creating register for signal `\graph_engine.\n_conn_acc' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1772' with positive edge clock.
Creating register for signal `\graph_engine.\out_id_acc' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1773' with positive edge clock.
Creating register for signal `\graph_engine.\conn_i' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1774' with positive edge clock.
Creating register for signal `\graph_engine.\edge_byte_idx' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1775' with positive edge clock.
Creating register for signal `\graph_engine.\src_id_acc' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1776' with positive edge clock.
Creating register for signal `\graph_engine.\weight_acc' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1777' with positive edge clock.
Creating register for signal `\graph_engine.\act_wr_en' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1778' with positive edge clock.
Creating register for signal `\graph_engine.\act_wr_addr' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1779' with positive edge clock.
Creating register for signal `\graph_engine.\act_wr_data' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1780' with positive edge clock.
Creating register for signal `\graph_engine.\neuron_start' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1781' with positive edge clock.
Creating register for signal `\graph_engine.\bias_reg' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1782' with positive edge clock.
Creating register for signal `\graph_engine.\activation_reg' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1783' with positive edge clock.
Creating register for signal `\graph_engine.\n_conn_padded_reg' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1784' with positive edge clock.
Creating register for signal `\graph_engine.\ri' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1785' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1786' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1787' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1788' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1789' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1790' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1791' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1792' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1793' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1794' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1795' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1796' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1797' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1798' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1799' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1800' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1801' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1802' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1803' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1804' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1805' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1806' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1807' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1808' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1809' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1810' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1811' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1812' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1813' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1814' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1815' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1816' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1817' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1818' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1819' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1820' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1821' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1822' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1823' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1824' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1825' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1826' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1827' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1828' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1829' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1830' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1831' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1832' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1833' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1834' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1835' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1836' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1837' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1838' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1839' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1840' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1841' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1842' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1843' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1844' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1845' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1846' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1847' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1848' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1849' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_ADDR' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1850' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_DATA' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1851' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1852' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_ADDR' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1853' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_DATA' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1854' with positive edge clock.
Creating register for signal `\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN' using process `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
created $dff cell `$procdff$1855' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\y' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468'.
created $dff cell `$procdff$1856' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\busy' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468'.
created $dff cell `$procdff$1857' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\done' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468'.
created $dff cell `$procdff$1858' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\group_index' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468'.
created $dff cell `$procdff$1859' with positive edge clock.
Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\acc' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468'.
created $dff cell `$procdff$1860' with positive edge clock.
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.\rd_data' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$486'.
created $dff cell `$procdff$1861' with positive edge clock.
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_ADDR' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$479'.
created $dff cell `$procdff$1862' with positive edge clock.
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_DATA' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$479'.
created $dff cell `$procdff$1863' with positive edge clock.
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$479'.
created $dff cell `$procdff$1864' with positive edge clock.
7.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
7.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 19 empty switches in `\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
Removing empty process `graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$126'.
Found and cleaned up 9 empty switches in `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468'.
Removing empty process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:130$468'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$551'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$549'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$547'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$545'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$543'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$541'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$539'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$538'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$537'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$536'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$535'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$534'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$533'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$532'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$531'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$530'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$529'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$528'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$527'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$526'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$525'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$524'.
Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$523'.
Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$486'.
Found and cleaned up 1 empty switch in `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$479'.
Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$479'.
Cleaned up 29 empty switches.
7.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~11 debug messages>
Optimizing module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
<suppressed ~1 debug messages>
Optimizing module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
Optimizing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.
Optimizing module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
7.5. Executing CHECK pass (checking for obvious problems).
Checking module graph_engine...
Checking module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel...
Checking module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit...
Checking module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8...
Checking module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer...
Found and reported 0 problems.
7.6. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.
Deleting now unused module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
Deleting now unused module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.
Deleting now unused module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
<suppressed ~11 debug messages>
7.7. Executing TRIBUF pass.
7.8. Executing DEMINOUT pass (demote inout ports to input or output).
7.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~22 debug messages>
7.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 75 unused cells and 666 unused wires.
<suppressed ~104 debug messages>
7.11. Executing CHECK pass (checking for obvious problems).
Checking module graph_engine...
Found and reported 0 problems.
7.12. Executing OPT pass (performing simple optimizations).
7.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 611 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 537 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 531 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~240 debug messages>
Removed a total of 80 cells.
7.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port A of cell $flatten\u_neuron.$procmux$1716: \u_neuron.busy -> 1'0
Replacing known input bits on port A of cell $flatten\u_neuron.$procmux$1714: \u_neuron.busy -> 1'1
Analyzing evaluation results.
dead port 1/2 on $mux $procmux$1426.
dead port 1/2 on $mux $procmux$947.
dead port 1/2 on $mux $procmux$937.
dead port 1/2 on $mux $procmux$927.
dead port 1/2 on $mux $procmux$917.
dead port 1/2 on $mux $procmux$907.
Removed 6 multiplexer ports.
<suppressed ~382 debug messages>
7.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
New ctrl vector for $pmux cell $procmux$1607: { $procmux$1608_CMP $procmux$1673_CMP $auto$opt_reduce.cc:137:opt_pmux$1944 }
Consolidated identical input bits for $mux cell $procmux$1423:
Old ports: A=8'00000000, B=8'11111111, Y=$procmux$1423_Y
New ports: A=1'0, B=1'1, Y=$procmux$1423_Y [0]
New connections: $procmux$1423_Y [7:1] = { $procmux$1423_Y [0] $procmux$1423_Y [0] $procmux$1423_Y [0] $procmux$1423_Y [0] $procmux$1423_Y [0] $procmux$1423_Y [0] $procmux$1423_Y [0] }
New ctrl vector for $pmux cell $procmux$1146: { $auto$opt_reduce.cc:137:opt_pmux$1946 $procmux$1673_CMP }
Consolidated identical input bits for $mux cell $procmux$1142:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$57_EN[7:0]$127 [0] }
Consolidated identical input bits for $mux cell $procmux$1139:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$58_EN[7:0]$128 [0] }
Consolidated identical input bits for $mux cell $procmux$1136:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$59_EN[7:0]$129 [0] }
Consolidated identical input bits for $mux cell $procmux$1133:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$60_EN[7:0]$130 [0] }
Consolidated identical input bits for $mux cell $procmux$1130:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$61_EN[7:0]$131 [0] }
Consolidated identical input bits for $mux cell $procmux$1127:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$62_EN[7:0]$132 [0] }
Consolidated identical input bits for $mux cell $procmux$1124:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$63_EN[7:0]$133 [0] }
Consolidated identical input bits for $mux cell $procmux$1121:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$64_EN[7:0]$134 [0] }
Consolidated identical input bits for $mux cell $procmux$1118:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$65_EN[7:0]$135 [0] }
Consolidated identical input bits for $mux cell $procmux$1115:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$66_EN[7:0]$136 [0] }
Consolidated identical input bits for $mux cell $procmux$1112:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$67_EN[7:0]$137 [0] }
Consolidated identical input bits for $mux cell $procmux$1109:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$68_EN[7:0]$138 [0] }
Consolidated identical input bits for $mux cell $procmux$1106:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$69_EN[7:0]$139 [0] }
Consolidated identical input bits for $mux cell $procmux$1103:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$70_EN[7:0]$140 [0] }
Consolidated identical input bits for $mux cell $procmux$1100:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$71_EN[7:0]$141 [0] }
Consolidated identical input bits for $mux cell $procmux$1097:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$72_EN[7:0]$142 [0] }
Consolidated identical input bits for $mux cell $procmux$1094:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$73_EN[7:0]$143 [0] }
Consolidated identical input bits for $mux cell $procmux$1091:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$74_EN[7:0]$144 [0] }
Consolidated identical input bits for $mux cell $procmux$1088:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$75_EN[7:0]$145 [0] }
Consolidated identical input bits for $mux cell $procmux$1085:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$76_EN[7:0]$146 [0] }
Consolidated identical input bits for $mux cell $procmux$1082:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$77_EN[7:0]$147 [0] }
Consolidated identical input bits for $mux cell $procmux$1079:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$78_EN[7:0]$148 [0] }
Consolidated identical input bits for $mux cell $procmux$1076:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$79_EN[7:0]$149 [0] }
Consolidated identical input bits for $mux cell $procmux$1073:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$80_EN[7:0]$150 [0] }
Consolidated identical input bits for $mux cell $procmux$1070:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$81_EN[7:0]$151 [0] }
Consolidated identical input bits for $mux cell $procmux$1067:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$82_EN[7:0]$152 [0] }
Consolidated identical input bits for $mux cell $procmux$1064:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$83_EN[7:0]$153 [0] }
Consolidated identical input bits for $mux cell $procmux$1061:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$84_EN[7:0]$154 [0] }
Consolidated identical input bits for $mux cell $procmux$1058:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$85_EN[7:0]$155 [0] }
Consolidated identical input bits for $mux cell $procmux$1055:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$86_EN[7:0]$156 [0] }
Consolidated identical input bits for $mux cell $procmux$1052:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$87_EN[7:0]$157 [0] }
Consolidated identical input bits for $mux cell $procmux$1049:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$88_EN[7:0]$158 [0] }
Consolidated identical input bits for $mux cell $procmux$1046:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$89_EN[7:0]$159 [0] }
Consolidated identical input bits for $mux cell $procmux$1043:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$90_EN[7:0]$160 [0] }
Consolidated identical input bits for $mux cell $procmux$1040:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$91_EN[7:0]$161 [0] }
Consolidated identical input bits for $mux cell $procmux$1037:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$92_EN[7:0]$162 [0] }
Consolidated identical input bits for $mux cell $procmux$1034:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$93_EN[7:0]$163 [0] }
Consolidated identical input bits for $mux cell $procmux$1031:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$94_EN[7:0]$164 [0] }
Consolidated identical input bits for $mux cell $procmux$1028:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$95_EN[7:0]$165 [0] }
Consolidated identical input bits for $mux cell $procmux$1025:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$96_EN[7:0]$166 [0] }
Consolidated identical input bits for $mux cell $procmux$1022:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$97_EN[7:0]$167 [0] }
Consolidated identical input bits for $mux cell $procmux$1019:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$98_EN[7:0]$168 [0] }
Consolidated identical input bits for $mux cell $procmux$1016:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$99_EN[7:0]$169 [0] }
Consolidated identical input bits for $mux cell $procmux$1013:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$100_EN[7:0]$170 [0] }
Consolidated identical input bits for $mux cell $procmux$1010:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$101_EN[7:0]$171 [0] }
Consolidated identical input bits for $mux cell $procmux$1007:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$102_EN[7:0]$172 [0] }
Consolidated identical input bits for $mux cell $procmux$1004:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$103_EN[7:0]$173 [0] }
Consolidated identical input bits for $mux cell $procmux$1001:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$104_EN[7:0]$174 [0] }
Consolidated identical input bits for $mux cell $procmux$998:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$105_EN[7:0]$175 [0] }
Consolidated identical input bits for $mux cell $procmux$995:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$106_EN[7:0]$176 [0] }
Consolidated identical input bits for $mux cell $procmux$992:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$107_EN[7:0]$177 [0] }
Consolidated identical input bits for $mux cell $procmux$989:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$108_EN[7:0]$178 [0] }
Consolidated identical input bits for $mux cell $procmux$986:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$109_EN[7:0]$179 [0] }
Consolidated identical input bits for $mux cell $procmux$983:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$110_EN[7:0]$180 [0] }
Consolidated identical input bits for $mux cell $procmux$980:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$111_EN[7:0]$181 [0] }
Consolidated identical input bits for $mux cell $procmux$977:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$112_EN[7:0]$182 [0] }
Consolidated identical input bits for $mux cell $procmux$974:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$113_EN[7:0]$183 [0] }
Consolidated identical input bits for $mux cell $procmux$971:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$114_EN[7:0]$184 [0] }
Consolidated identical input bits for $mux cell $procmux$968:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$115_EN[7:0]$185 [0] }
Consolidated identical input bits for $mux cell $procmux$965:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$116_EN[7:0]$186 [0] }
Consolidated identical input bits for $mux cell $procmux$962:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$117_EN[7:0]$187 [0] }
Consolidated identical input bits for $mux cell $procmux$959:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$118_EN[7:0]$188 [0] }
Consolidated identical input bits for $mux cell $procmux$956:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189
New ports: A=1'0, B=1'1, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$119_EN[7:0]$189 [0] }
Consolidated identical input bits for $mux cell $procmux$953:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190
New ports: A=1'0, B=1'1, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$120_EN[7:0]$190 [0] }
Consolidated identical input bits for $mux cell $procmux$924:
Old ports: A=8'00000000, B=8'11111111, Y=$procmux$924_Y
New ports: A=1'0, B=1'1, Y=$procmux$924_Y [0]
New connections: $procmux$924_Y [7:1] = { $procmux$924_Y [0] $procmux$924_Y [0] $procmux$924_Y [0] $procmux$924_Y [0] $procmux$924_Y [0] $procmux$924_Y [0] $procmux$924_Y [0] }
Consolidated identical input bits for $mux cell $flatten\u_act_buffer.$procmux$1751:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482
New ports: A=1'0, B=1'1, Y=$flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [0]
New connections: $flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [7:1] = { $flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [0] $flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [0] $flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [0] $flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [0] $flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [0] $flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [0] $flatten\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$478_EN[7:0]$482 [0] }
Optimizing cells in module \graph_engine.
Consolidated identical input bits for $mux cell $procmux$1209:
Old ports: A=$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$269, B=8'00000000, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193
New ports: A=$procmux$924_Y [0], B=1'0, Y=$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [0]
New connections: $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [7:1] = { $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [0] $0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$121_EN[7:0]$193 [0] }
Consolidated identical input bits for $mux cell $procmux$1200:
Old ports: A=$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$272, B=8'00000000, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196
New ports: A=$procmux$1423_Y [0], B=1'0, Y=$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [0]
New connections: $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [7:1] = { $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [0] $0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_EN[7:0]$196 [0] }
Optimizing cells in module \graph_engine.
Performed a total of 71 changes.
7.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 527 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 456 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 454 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~219 debug messages>
Removed a total of 73 cells.
7.12.6. Executing OPT_DFF pass (perform DFF optimizations).
7.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 0 unused cells and 154 unused wires.
<suppressed ~1 debug messages>
7.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.12.9. Rerunning OPT passes. (Maybe there is more to do..)
7.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~256 debug messages>
7.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 454 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.12.13. Executing OPT_DFF pass (perform DFF optimizations).
7.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.12.16. Finished fast OPT passes. (There is nothing left to do.)
7.13. Executing FSM pass (extract and optimize FSM).
7.13.1. Executing FSM_DETECT pass (finding FSMs in design).
Found FSM state register graph_engine.state.
7.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\state' from module `\graph_engine'.
found $dff cell for state register: $procdff$1766
root of input selection tree: $0\state[3:0]
found reset state: 4'0000 (guessed from mux tree)
found ctrl input: \rst
found ctrl input: $procmux$1186_CMP
found ctrl input: $procmux$1147_CMP
found ctrl input: $procmux$1172_CMP
found ctrl input: $procmux$1162_CMP
found ctrl input: $procmux$1362_CMP
found ctrl input: $procmux$1307_CMP
found ctrl input: $procmux$1151_CMP
found ctrl input: $procmux$1231_CMP
found ctrl input: $procmux$1152_CMP
found ctrl input: $procmux$1175_CMP
found ctrl input: $procmux$1153_CMP
found ctrl input: $procmux$1479_CTRL
found state code: 4'0000
found ctrl input: \ram_ready
found ctrl input: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$298_Y
found state code: 4'0011
found state code: 4'1011
found ctrl input: \u_neuron.done
found ctrl input: \is_output_sink
found state code: 4'1010
found state code: 4'1001
found ctrl input: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$295_Y
found state code: 4'0101
found state code: 4'1000
found ctrl input: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$287_Y
found ctrl input: $logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$292_Y
found state code: 4'0111
found state code: 4'1100
found ctrl input: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$283_Y
found state code: 4'0110
found ctrl input: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$278_Y
found state code: 4'0100
found ctrl input: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$275_Y
found state code: 4'0001
found state code: 4'0010
found ctrl input: \run_start
found ctrl output: $procmux$1162_CMP
found ctrl output: $procmux$1362_CMP
found ctrl output: $procmux$1231_CMP
found ctrl output: $procmux$1175_CMP
found ctrl output: $procmux$1147_CMP
found ctrl output: $procmux$1152_CMP
found ctrl output: $procmux$1153_CMP
found ctrl output: $procmux$1186_CMP
found ctrl output: $procmux$1172_CMP
found ctrl output: $procmux$1307_CMP
found ctrl output: $procmux$1151_CMP
found ctrl output: $procmux$1479_CMP [0]
found ctrl output: $procmux$1479_CMP [1]
ctrl inputs: { \u_neuron.done $procmux$1479_CTRL $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$298_Y $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$295_Y $logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$292_Y $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$287_Y $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$283_Y $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$278_Y $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$275_Y \is_output_sink \ram_ready \run_start \rst }
ctrl outputs: { $procmux$1479_CMP $procmux$1362_CMP $procmux$1307_CMP $procmux$1231_CMP $procmux$1186_CMP $procmux$1175_CMP $procmux$1172_CMP $procmux$1162_CMP $procmux$1153_CMP $procmux$1152_CMP $procmux$1151_CMP $procmux$1147_CMP $0\state[3:0] }
transition: 4'0000 13'-----------00 -> 4'0000 17'01000000000000000
transition: 4'0000 13'-----------10 -> 4'0001 17'01000000000000001
transition: 4'0000 13'------------1 -> 4'0000 17'01000000000000000
transition: 4'1000 13'------------0 -> 4'1001 17'00000000100001001
transition: 4'1000 13'------------1 -> 4'0000 17'00000000100000000
transition: 4'0100 13'----------0-0 -> 4'0100 17'00001000000000100
transition: 4'0100 13'-------0--1-0 -> 4'0011 17'00001000000000011
transition: 4'0100 13'-------1--1-0 -> 4'0101 17'00001000000000101
transition: 4'0100 13'------------1 -> 4'0000 17'00001000000000000
transition: 4'1100 13'-----------00 -> 4'1100 17'10000000000001100
transition: 4'1100 13'-----------10 -> 4'0001 17'10000000000000001
transition: 4'1100 13'------------1 -> 4'0000 17'10000000000000000
transition: 4'0010 13'----------0-0 -> 4'0010 17'00000010000000010
transition: 4'0010 13'--------0-1-0 -> 4'0001 17'00000010000000001
transition: 4'0010 13'--------1-1-0 -> 4'0011 17'00000010000000011
transition: 4'0010 13'------------1 -> 4'0000 17'00000010000000000
transition: 4'1010 13'------------0 -> 4'1011 17'00000000000011011
transition: 4'1010 13'------------1 -> 4'0000 17'00000000000010000
transition: 4'0110 13'----------0-0 -> 4'0110 17'00010000000000110
transition: 4'0110 13'-----0----1-0 -> 4'0101 17'00010000000000101
transition: 4'0110 13'----01----1-0 -> 4'0111 17'00010000000000111
transition: 4'0110 13'----11----1-0 -> 4'1100 17'00010000000001100
transition: 4'0110 13'------------1 -> 4'0000 17'00010000000000000
transition: 4'0001 13'------------0 -> 4'0010 17'00000000010000010
transition: 4'0001 13'------------1 -> 4'0000 17'00000000010000000
transition: 4'1001 13'0-----------0 -> 4'1001 17'00000001000001001
transition: 4'1001 13'1-0------0--0 -> 4'0011 17'00000001000000011
transition: 4'1001 13'1-1------0--0 -> 4'0000 17'00000001000000000
transition: 4'1001 13'1--------1--0 -> 4'1010 17'00000001000001010
transition: 4'1001 13'------------1 -> 4'0000 17'00000001000000000
transition: 4'0101 13'------0-----0 -> 4'0110 17'00000000000100110
transition: 4'0101 13'------1-----0 -> 4'1100 17'00000000000101100
transition: 4'0101 13'------------1 -> 4'0000 17'00000000000100000
transition: 4'0011 13'------------0 -> 4'0100 17'00000000001000100
transition: 4'0011 13'------------1 -> 4'0000 17'00000000001000000
transition: 4'1011 13'----------0-0 -> 4'1011 17'00000100000001011
transition: 4'1011 13'--0-------1-0 -> 4'0011 17'00000100000000011
transition: 4'1011 13'--1-------1-0 -> 4'0000 17'00000100000000000
transition: 4'1011 13'------------1 -> 4'0000 17'00000100000000000
transition: 4'0111 13'---0--------0 -> 4'0101 17'00100000000000101
transition: 4'0111 13'---1--------0 -> 4'1000 17'00100000000001000
transition: 4'0111 13'------------1 -> 4'0000 17'00100000000000000
7.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\state$1947' from module `\graph_engine'.
Removing unused input signal $procmux$1479_CTRL.
7.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 30 unused cells and 30 unused wires.
<suppressed ~31 debug messages>
7.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\state$1947' from module `\graph_engine'.
Removing unused output signal $0\state[3:0] [0].
Removing unused output signal $0\state[3:0] [1].
Removing unused output signal $0\state[3:0] [2].
Removing unused output signal $0\state[3:0] [3].
7.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\state$1947' from module `\graph_engine' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
0000 -> ------------1
1000 -> -----------1-
0100 -> ----------1--
1100 -> ---------1---
0010 -> --------1----
1010 -> -------1-----
0110 -> ------1------
0001 -> -----1-------
1001 -> ----1--------
0101 -> ---1---------
0011 -> --1----------
1011 -> -1-----------
0111 -> 1------------
7.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
FSM `$fsm$\state$1947' from module `graph_engine':
-------------------------------------
Information on FSM $fsm$\state$1947 (\state):
Number of input signals: 12
Number of output signals: 13
Number of state bits: 13
Input signals:
0: \rst
1: \run_start
2: \ram_ready
3: \is_output_sink
4: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$275_Y
5: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$278_Y
6: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$283_Y
7: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$287_Y
8: $logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$292_Y
9: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$295_Y
10: $eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$298_Y
11: \u_neuron.done
Output signals:
0: $procmux$1147_CMP
1: $procmux$1151_CMP
2: $procmux$1152_CMP
3: $procmux$1153_CMP
4: $procmux$1162_CMP
5: $procmux$1172_CMP
6: $procmux$1175_CMP
7: $procmux$1186_CMP
8: $procmux$1231_CMP
9: $procmux$1307_CMP
10: $procmux$1362_CMP
11: $procmux$1479_CMP [0]
12: $procmux$1479_CMP [1]
State encoding:
0: 13'------------1 <RESET STATE>
1: 13'-----------1-
2: 13'----------1--
3: 13'---------1---
4: 13'--------1----
5: 13'-------1-----
6: 13'------1------
7: 13'-----1-------
8: 13'----1--------
9: 13'---1---------
10: 13'--1----------
11: 13'-1-----------
12: 13'1------------
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 12'----------00 -> 0 13'0100000000000
1: 0 12'-----------1 -> 0 13'0100000000000
2: 0 12'----------10 -> 7 13'0100000000000
3: 1 12'-----------1 -> 0 13'0000000010000
4: 1 12'-----------0 -> 8 13'0000000010000
5: 2 12'-----------1 -> 0 13'0000100000000
6: 2 12'---------0-0 -> 2 13'0000100000000
7: 2 12'------1--1-0 -> 9 13'0000100000000
8: 2 12'------0--1-0 -> 10 13'0000100000000
9: 3 12'-----------1 -> 0 13'1000000000000
10: 3 12'----------00 -> 3 13'1000000000000
11: 3 12'----------10 -> 7 13'1000000000000
12: 4 12'-----------1 -> 0 13'0000001000000
13: 4 12'---------0-0 -> 4 13'0000001000000
14: 4 12'-------0-1-0 -> 7 13'0000001000000
15: 4 12'-------1-1-0 -> 10 13'0000001000000
16: 5 12'-----------1 -> 0 13'0000000000001
17: 5 12'-----------0 -> 11 13'0000000000001
18: 6 12'-----------1 -> 0 13'0001000000000
19: 6 12'---11----1-0 -> 3 13'0001000000000
20: 6 12'---------0-0 -> 6 13'0001000000000
21: 6 12'----0----1-0 -> 9 13'0001000000000
22: 6 12'---01----1-0 -> 12 13'0001000000000
23: 7 12'-----------1 -> 0 13'0000000001000
24: 7 12'-----------0 -> 4 13'0000000001000
25: 8 12'11------0--0 -> 0 13'0000000100000
26: 8 12'-----------1 -> 0 13'0000000100000
27: 8 12'1-------1--0 -> 5 13'0000000100000
28: 8 12'0----------0 -> 8 13'0000000100000
29: 8 12'10------0--0 -> 10 13'0000000100000
30: 9 12'-----------1 -> 0 13'0000000000010
31: 9 12'-----1-----0 -> 3 13'0000000000010
32: 9 12'-----0-----0 -> 6 13'0000000000010
33: 10 12'-----------1 -> 0 13'0000000000100
34: 10 12'-----------0 -> 2 13'0000000000100
35: 11 12'-1-------1-0 -> 0 13'0000010000000
36: 11 12'-----------1 -> 0 13'0000010000000
37: 11 12'-0-------1-0 -> 10 13'0000010000000
38: 11 12'---------0-0 -> 11 13'0000010000000
39: 12 12'-----------1 -> 0 13'0010000000000
40: 12 12'--1--------0 -> 1 13'0010000000000
41: 12 12'--0--------0 -> 9 13'0010000000000
-------------------------------------
7.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\state$1947' from module `\graph_engine'.
7.14. Executing OPT pass (performing simple optimizations).
7.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~14 debug messages>
7.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 492 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 484 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~24 debug messages>
Removed a total of 8 cells.
7.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~236 debug messages>
7.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 484 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.14.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$1767 ($dff) from module graph_engine (D = $procmux$1521_Y, Q = \in_idx, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2092 ($sdff) from module graph_engine (D = $procmux$1521_Y, Q = \in_idx).
Adding SRST signal on $procdff$1768 ($dff) from module graph_engine (D = $procmux$1489_Y, Q = \neuron_idx, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2104 ($sdff) from module graph_engine (D = $procmux$1489_Y, Q = \neuron_idx).
Adding SRST signal on $procdff$1769 ($dff) from module graph_engine (D = $procmux$1466_Y, Q = \desc_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2118 ($sdff) from module graph_engine (D = $procmux$1466_Y, Q = \desc_addr).
Adding SRST signal on $procdff$1770 ($dff) from module graph_engine (D = $procmux$1434_Y, Q = \desc_byte_idx, rval = 4'0000).
Adding EN signal on $auto$ff.cc:337:slice$2132 ($sdff) from module graph_engine (D = $procmux$1434_Y, Q = \desc_byte_idx).
Adding SRST signal on $procdff$1771 ($dff) from module graph_engine (D = { $procmux$894_Y $procmux$1413_Y $procmux$869_Y }, Q = \conn_ptr_acc, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2152 ($sdff) from module graph_engine (D = \ram_rdata, Q = \conn_ptr_acc [7:0]).
Adding EN signal on $auto$ff.cc:337:slice$2152 ($sdff) from module graph_engine (D = \ram_rdata, Q = \conn_ptr_acc [23:16]).
Adding EN signal on $auto$ff.cc:337:slice$2152 ($sdff) from module graph_engine (D = \ram_rdata, Q = \conn_ptr_acc [15:8]).
Adding SRST signal on $procdff$1772 ($dff) from module graph_engine (D = { $procmux$1389_Y $procmux$846_Y }, Q = \n_conn_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2162 ($sdff) from module graph_engine (D = \ram_rdata, Q = \n_conn_acc [7:0]).
Adding EN signal on $auto$ff.cc:337:slice$2162 ($sdff) from module graph_engine (D = \ram_rdata, Q = \n_conn_acc [15:8]).
Adding SRST signal on $procdff$1773 ($dff) from module graph_engine (D = { $procmux$1326_Y $procmux$825_Y }, Q = \out_id_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2169 ($sdff) from module graph_engine (D = \ram_rdata, Q = \out_id_acc [7:0]).
Adding EN signal on $auto$ff.cc:337:slice$2169 ($sdff) from module graph_engine (D = \ram_rdata, Q = \out_id_acc [15:8]).
Adding SRST signal on $procdff$1774 ($dff) from module graph_engine (D = $procmux$1361_Y, Q = \conn_i, rval = 6'000000).
Adding EN signal on $auto$ff.cc:337:slice$2176 ($sdff) from module graph_engine (D = $procmux$1361_Y, Q = \conn_i).
Adding SRST signal on $procdff$1775 ($dff) from module graph_engine (D = $procmux$1342_Y, Q = \edge_byte_idx, rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$2186 ($sdff) from module graph_engine (D = $procmux$1342_Y, Q = \edge_byte_idx).
Adding SRST signal on $procdff$1776 ($dff) from module graph_engine (D = { $procmux$790_Y $procmux$806_Y }, Q = \src_id_acc, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2198 ($sdff) from module graph_engine (D = \ram_rdata, Q = \src_id_acc [15:8]).
Adding EN signal on $auto$ff.cc:337:slice$2198 ($sdff) from module graph_engine (D = \ram_rdata, Q = \src_id_acc [7:0]).
Adding SRST signal on $procdff$1777 ($dff) from module graph_engine (D = $procmux$1306_Y, Q = \weight_acc, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$2205 ($sdff) from module graph_engine (D = \ram_rdata, Q = \weight_acc).
Adding SRST signal on $procdff$1778 ($dff) from module graph_engine (D = $procmux$1171_Y, Q = \act_wr_en, rval = 1'0).
Adding SRST signal on $procdff$1779 ($dff) from module graph_engine (D = $procmux$1288_Y, Q = \act_wr_addr, rval = 12'000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2210 ($sdff) from module graph_engine (D = $procmux$1288_Y, Q = \act_wr_addr).
Adding SRST signal on $procdff$1780 ($dff) from module graph_engine (D = $procmux$1275_Y, Q = \act_wr_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$2220 ($sdff) from module graph_engine (D = $procmux$1275_Y, Q = \act_wr_data).
Adding SRST signal on $procdff$1781 ($dff) from module graph_engine (D = $procmux$1161_Y, Q = \neuron_start, rval = 1'0).
Adding SRST signal on $procdff$1782 ($dff) from module graph_engine (D = $procmux$1265_Y, Q = \bias_reg, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$2231 ($sdff) from module graph_engine (D = \ram_rdata, Q = \bias_reg).
Adding SRST signal on $procdff$1783 ($dff) from module graph_engine (D = $procmux$1248_Y, Q = \activation_reg, rval = 2'01).
Adding EN signal on $auto$ff.cc:337:slice$2235 ($sdff) from module graph_engine (D = \ram_rdata [1:0], Q = \activation_reg).
Adding SRST signal on $procdff$1784 ($dff) from module graph_engine (D = $procmux$1230_Y, Q = \n_conn_padded_reg, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2239 ($sdff) from module graph_engine (D = { $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$279_Y [15:3] 3'000 }, Q = \n_conn_padded_reg).
Adding SRST signal on $flatten\u_neuron.$procdff$1856 ($dff) from module graph_engine (D = $flatten\u_neuron.$procmux$1745_Y, Q = \u_neuron.y, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$2243 ($sdff) from module graph_engine (D = $flatten\u_neuron.$procmux$1738_Y, Q = \u_neuron.y).
Adding SRST signal on $flatten\u_neuron.$procdff$1857 ($dff) from module graph_engine (D = $flatten\u_neuron.$procmux$1719_Y, Q = \u_neuron.busy, rval = 1'0).
Adding SRST signal on $flatten\u_neuron.$procdff$1858 ($dff) from module graph_engine (D = $flatten\u_neuron.$procmux$1681_Y, Q = \u_neuron.done, rval = 1'0).
Adding SRST signal on $flatten\u_neuron.$procdff$1859 ($dff) from module graph_engine (D = $flatten\u_neuron.$procmux$1705_Y, Q = \u_neuron.group_index, rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$2255 ($sdff) from module graph_engine (D = $flatten\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$477_Y, Q = \u_neuron.group_index).
Adding SRST signal on $flatten\u_neuron.$procdff$1860 ($dff) from module graph_engine (D = $flatten\u_neuron.$procmux$1694_Y, Q = \u_neuron.acc, rval = 0).
Adding EN signal on $auto$ff.cc:337:slice$2263 ($sdff) from module graph_engine (D = $flatten\u_neuron.$procmux$1692_Y, Q = \u_neuron.acc).
Adding SRST signal on $procdff$1764 ($dff) from module graph_engine (D = $procmux$1594_Y, Q = \ram_addr, rval = 23'00000000000000000000000).
Adding EN signal on $auto$ff.cc:337:slice$2267 ($sdff) from module graph_engine (D = $procmux$1594_Y, Q = \ram_addr).
Adding SRST signal on $procdff$1765 ($dff) from module graph_engine (D = $procmux$1587_Y, Q = \ram_wdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:337:slice$2275 ($sdff) from module graph_engine (D = \u_neuron.y, Q = \ram_wdata).
Adding SRST signal on $procdff$1763 ($dff) from module graph_engine (D = $procmux$1607_Y, Q = \ram_wr, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$2277 ($sdff) from module graph_engine (D = $procmux$1607_Y, Q = \ram_wr).
Adding SRST signal on $procdff$1762 ($dff) from module graph_engine (D = $procmux$1146_Y, Q = \ram_req, rval = 1'0).
Adding SRST signal on $procdff$1761 ($dff) from module graph_engine (D = $procmux$1632_Y, Q = \err, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$2286 ($sdff) from module graph_engine (D = $procmux$1632_Y, Q = \err).
Adding SRST signal on $procdff$1760 ($dff) from module graph_engine (D = $procmux$1185_Y, Q = \done, rval = 1'0).
Adding SRST signal on $procdff$1759 ($dff) from module graph_engine (D = $procmux$1650_Y, Q = \busy, rval = 1'0).
Adding EN signal on $auto$ff.cc:337:slice$2303 ($sdff) from module graph_engine (D = $procmux$1650_Y, Q = \busy).
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$2240 ($sdffe) from module graph_engine.
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$2240 ($sdffe) from module graph_engine.
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$2240 ($sdffe) from module graph_engine.
7.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 85 unused cells and 104 unused wires.
<suppressed ~86 debug messages>
7.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~12 debug messages>
7.14.9. Rerunning OPT passes. (Maybe there is more to do..)
7.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~136 debug messages>
7.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 491 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 460 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 458 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~99 debug messages>
Removed a total of 33 cells.
7.14.13. Executing OPT_DFF pass (perform DFF optimizations).
7.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 0 unused cells and 33 unused wires.
<suppressed ~1 debug messages>
7.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.14.16. Rerunning OPT passes. (Maybe there is more to do..)
7.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~138 debug messages>
7.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.14.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 458 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.14.20. Executing OPT_DFF pass (perform DFF optimizations).
7.14.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.14.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.14.23. Finished fast OPT passes. (There is nothing left to do.)
7.15. Executing WREDUCE pass (reducing word size of cells).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1927 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1926 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1925 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1924 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1923 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1922 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1921 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1920 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1919 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1918 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1917 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1916 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1915 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1914 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1928 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1913 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1912 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1911 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1910 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1909 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1908 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1907 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1906 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1905 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1904 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1903 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1902 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1901 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1900 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1899 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1898 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1897 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1896 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1895 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1894 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1893 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1892 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1891 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1890 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1889 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1888 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1887 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1886 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1885 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1884 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1883 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1882 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1881 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1880 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1879 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1878 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1877 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1876 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1875 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1874 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1873 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1872 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1871 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1870 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1869 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1868 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1867 (x_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1866 (w_mem).
Removed top 27 address bits (of 32) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1865 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$369 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$368 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$367 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$366 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$365 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$364 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$363 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$362 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$361 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$360 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$359 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$358 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$357 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$356 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$355 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$354 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$353 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$352 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$351 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$350 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$349 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$348 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$347 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$346 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$345 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$344 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$343 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$342 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$341 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$340 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$339 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$338 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$337 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$336 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$335 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$334 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$333 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$332 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$331 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$330 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$329 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$328 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$327 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$326 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$325 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$324 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$323 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$322 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$321 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$320 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$319 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$318 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$317 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$316 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$315 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$314 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$313 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$312 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$311 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$310 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$309 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$308 (x_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$307 (w_mem).
Removed top 27 address bits (of 32) from memory read port graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$306 (x_mem).
Removed top 1 address bits (of 6) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1929 (x_mem).
Removed top 1 address bits (of 6) from memory init port graph_engine.$auto$proc_memwr.cc:45:proc_memwr$1930 (w_mem).
Removed top 1 bits (of 2) from port B of cell graph_engine.$auto$opt_dff.cc:320:make_patterns_logic$2299 ($ne).
Removed top 1 bits (of 2) from port B of cell graph_engine.$auto$opt_dff.cc:320:make_patterns_logic$2297 ($ne).
Removed top 1 bits (of 2) from port B of cell graph_engine.$auto$opt_dff.cc:320:make_patterns_logic$2295 ($ne).
Removed top 1 bits (of 2) from port B of cell graph_engine.$auto$opt_dff.cc:320:make_patterns_logic$2183 ($ne).
Removed top 1 bits (of 8) from FF cell graph_engine.$auto$ff.cc:337:slice$2156 ($sdffe).
Removed top 1 bits (of 2) from port B of cell graph_engine.$auto$opt_dff.cc:320:make_patterns_logic$2149 ($ne).
Removed top 1 bits (of 2) from port B of cell graph_engine.$auto$opt_dff.cc:320:make_patterns_logic$2145 ($ne).
Removed top 1 bits (of 2) from port B of cell graph_engine.$auto$opt_dff.cc:320:make_patterns_logic$2109 ($ne).
Removed top 1 bits (of 4) from port B of cell graph_engine.$auto$fsm_map.cc:77:implement_pattern_cache$2089 ($eq).
Removed top 1 bits (of 3) from port B of cell graph_engine.$auto$fsm_map.cc:77:implement_pattern_cache$2071 ($eq).
Removed top 1 bits (of 3) from port B of cell graph_engine.$auto$fsm_map.cc:77:implement_pattern_cache$2067 ($eq).
Removed top 1 bits (of 3) from port B of cell graph_engine.$auto$fsm_map.cc:77:implement_pattern_cache$2054 ($eq).
Removed top 1 bits (of 3) from port B of cell graph_engine.$auto$fsm_map.cc:77:implement_pattern_cache$2036 ($eq).
Removed top 15 bits (of 16) from port B of cell graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$274 ($sub).
Removed top 15 bits (of 16) from port B of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$276 ($add).
Removed top 29 bits (of 32) from port B of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$279 ($add).
Removed top 16 bits (of 32) from port Y of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$279 ($add).
Removed top 3 bits (of 4) from port B of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$282 ($add).
Removed top 24 bits (of 32) from port B of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$285 ($add).
Removed top 8 bits (of 32) from port Y of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$285 ($add).
Removed top 8 bits (of 32) from port A of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$286 ($add).
Removed top 9 bits (of 32) from port Y of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$286 ($add).
Removed top 1 bits (of 24) from port A of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$286 ($add).
Removed top 3 bits (of 16) from port B of cell graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$289 ($ge).
Removed top 3 bits (of 16) from port B of cell graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$291 ($ge).
Removed top 1 bits (of 2) from port B of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$293 ($add).
Removed top 15 bits (of 16) from port B of cell graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:561$302 ($sub).
Removed top 15 bits (of 16) from port B of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:566$304 ($add).
Removed top 28 bits (of 32) from port B of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:567$305 ($add).
Removed top 9 bits (of 32) from port Y of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:567$305 ($add).
Removed top 1 bits (of 2) from port B of cell graph_engine.$procmux$803_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell graph_engine.$procmux$822_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell graph_engine.$procmux$843_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell graph_engine.$procmux$866_CMP0 ($eq).
Removed top 1 bits (of 6) from mux cell graph_engine.$procmux$1215 ($mux).
Removed top 1 bits (of 4) from port B of cell graph_engine.$procmux$1245_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell graph_engine.$procmux$1323_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell graph_engine.$procmux$1386_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell graph_engine.$procmux$1410_CMP0 ($eq).
Converting cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$540 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$540 ($add).
Removed top 16 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$540 ($add).
Removed top 15 bits (of 32) from port Y of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$540 ($add).
Converting cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$542 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$542 ($add).
Removed top 16 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$542 ($add).
Removed top 15 bits (of 32) from port Y of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$542 ($add).
Converting cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$544 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$544 ($add).
Removed top 16 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$544 ($add).
Removed top 15 bits (of 32) from port Y of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$544 ($add).
Converting cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$546 ($add) from unsigned to signed.
Removed top 16 bits (of 32) from port A of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$546 ($add).
Removed top 16 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$546 ($add).
Removed top 15 bits (of 32) from port Y of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$546 ($add).
Converting cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$548 ($add) from unsigned to signed.
Removed top 15 bits (of 32) from port A of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$548 ($add).
Removed top 15 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$548 ($add).
Removed top 14 bits (of 32) from port Y of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$548 ($add).
Converting cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$550 ($add) from unsigned to signed.
Removed top 15 bits (of 32) from port A of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$550 ($add).
Removed top 15 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$550 ($add).
Removed top 14 bits (of 32) from port Y of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$550 ($add).
Converting cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552 ($add) from unsigned to signed.
Removed top 14 bits (of 32) from port A of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552 ($add).
Removed top 14 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552 ($add).
Removed top 13 bits (of 32) from port Y of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552 ($add).
Removed top 24 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.$gt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$476 ($gt).
Removed top 31 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.$le$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:176$475 ($le).
Removed top 24 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.$lt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165$474 ($lt).
Removed top 24 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:128$467 ($add).
Removed top 13 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$522 ($add).
Removed top 23 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:107$466 ($shiftx).
Removed top 23 bits (of 32) from port B of cell graph_engine.$flatten\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:101$462 ($shiftx).
Removed top 1 bits (of 24) from port Y of cell graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$285 ($add).
Removed top 1 bits (of 6) from mux cell graph_engine.$procmux$944 ($mux).
Removed top 9 bits (of 32) from wire graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$300_Y.
Removed top 9 bits (of 32) from wire graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$286_Y.
Removed top 9 bits (of 32) from wire graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$285_Y.
Removed top 16 bits (of 32) from wire graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$279_Y.
Removed top 1 bits (of 6) from wire graph_engine.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_ADDR[5:0]$270.
Removed top 1 bits (of 6) from wire graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$122_ADDR[5:0]$194.
Removed top 1 bits (of 24) from wire graph_engine.conn_ptr_acc.
7.16. Executing PEEPOPT pass (run peephole optimizers).
shiftpow2 pattern in graph_engine: shift=$flatten\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:107$466, index=\u_neuron.group_index, stride=64, width=64, ways=4
shiftpow2 pattern in graph_engine: shift=$flatten\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:101$462, index=\u_neuron.group_index, stride=64, width=64, ways=4
7.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 0 unused cells and 7 unused wires.
<suppressed ~1 debug messages>
7.18. Executing SHARE pass (SAT-based resource sharing).
Found 8 cells in module graph_engine that may be considered for resource sharing.
Analyzing resource sharing options for $flatten\u_neuron.\u_mac8.\GEN_MAC[2].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$488 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron.\u_mac8.\GEN_MAC[1].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$488 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron.\u_mac8.\GEN_MAC[0].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$488 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron.\u_mac8.\GEN_MAC[7].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$488 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron.\u_mac8.\GEN_MAC[6].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$488 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron.\u_mac8.\GEN_MAC[5].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$488 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron.\u_mac8.\GEN_MAC[3].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$488 ($mul):
Cell is always active. Therefore no sharing is possible.
Analyzing resource sharing options for $flatten\u_neuron.\u_mac8.\GEN_MAC[4].u_mac.$mul$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v:16$488 ($mul):
Cell is always active. Therefore no sharing is possible.
7.19. Executing TECHMAP pass (map to technology primitives).
7.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
7.19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~140 debug messages>
7.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.22. Executing TECHMAP pass (map to technology primitives).
7.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
7.22.2. Continuing TECHMAP pass.
Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul.
No more expansions possible.
<suppressed ~92 debug messages>
7.23. Executing TECHMAP pass (map to technology primitives).
7.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
Generating RTLIL representation for module `$__MUL18X18'.
Successfully finished Verilog frontend.
7.23.2. Continuing TECHMAP pass.
Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18.
No more expansions possible.
<suppressed ~30 debug messages>
7.24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module graph_engine:
creating $macc model for $flatten\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:152$471 ($sub).
creating $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$542 ($add).
creating $macc model for $flatten\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:128$467 ($add).
creating $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$522 ($add).
creating $macc model for $flatten\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$477 ($add).
creating $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$544 ($add).
creating $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$546 ($add).
creating $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$548 ($add).
creating $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$550 ($add).
creating $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:567$305 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:566$304 ($add).
creating $macc model for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:561$302 ($sub).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$301 ($add).
creating $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$540 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$296 ($add).
creating $macc model for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$294 ($sub).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$293 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$286 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$285 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$282 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$279 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$277 ($add).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$276 ($add).
creating $macc model for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$274 ($sub).
creating $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$273 ($add).
creating $macc model for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$125 ($sub).
creating $macc model for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$123 ($sub).
merging $macc model for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$285 into $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$286.
merging $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$548 into $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552.
merging $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$540 into $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552.
merging $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$550 into $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552.
merging $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$544 into $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552.
merging $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$542 into $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552.
merging $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$546 into $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552.
merging $macc model for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$552 into $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$522.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$282.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$293.
creating $alu model for $macc $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$294.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$296.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$277.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$301.
creating $alu model for $macc $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:561$302.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:566$304.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:567$305.
creating $alu model for $macc $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$123.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$276.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$279.
creating $alu model for $macc $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$125.
creating $alu model for $macc $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$274.
creating $alu model for $macc $flatten\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$477.
creating $alu model for $macc $flatten\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:128$467.
creating $alu model for $macc $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$273.
creating $alu model for $macc $flatten\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:152$471.
creating $macc cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$286: $auto$alumacc.cc:399:replace_macc$2352
creating $macc cell for $flatten\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$522: $auto$alumacc.cc:399:replace_macc$2353
creating $alu model for $flatten\u_neuron.$gt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$476 ($gt): new $alu
creating $alu model for $flatten\u_neuron.$le$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:176$475 ($le): new $alu
creating $alu model for $flatten\u_neuron.$lt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165$474 ($lt): new $alu
creating $alu model for $ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$291 ($ge): new $alu
creating $alu model for $ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$289 ($ge): new $alu
creating $alu model for $ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$288 ($ge): new $alu
creating $alu model for $ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:176$124 ($ge): merged with $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$125.
creating $alu cell for $ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$288: $auto$alumacc.cc:548:replace_alu$2360
creating $alu cell for $ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$289: $auto$alumacc.cc:548:replace_alu$2373
creating $alu cell for $ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$291: $auto$alumacc.cc:548:replace_alu$2386
creating $alu cell for $flatten\u_neuron.$lt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165$474: $auto$alumacc.cc:548:replace_alu$2399
creating $alu cell for $flatten\u_neuron.$le$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:176$475: $auto$alumacc.cc:548:replace_alu$2406
creating $alu cell for $flatten\u_neuron.$gt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$476: $auto$alumacc.cc:548:replace_alu$2417
creating $alu cell for $flatten\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:152$471: $auto$alumacc.cc:548:replace_alu$2430
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$273: $auto$alumacc.cc:548:replace_alu$2433
creating $alu cell for $flatten\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:128$467: $auto$alumacc.cc:548:replace_alu$2436
creating $alu cell for $flatten\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$477: $auto$alumacc.cc:548:replace_alu$2439
creating $alu cell for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$274: $auto$alumacc.cc:548:replace_alu$2442
creating $alu cell for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$125, $ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:176$124: $auto$alumacc.cc:548:replace_alu$2445
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$279: $auto$alumacc.cc:548:replace_alu$2458
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$276: $auto$alumacc.cc:548:replace_alu$2461
creating $alu cell for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$123: $auto$alumacc.cc:548:replace_alu$2464
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:567$305: $auto$alumacc.cc:548:replace_alu$2467
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:566$304: $auto$alumacc.cc:548:replace_alu$2470
creating $alu cell for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:561$302: $auto$alumacc.cc:548:replace_alu$2473
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$301: $auto$alumacc.cc:548:replace_alu$2476
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$277: $auto$alumacc.cc:548:replace_alu$2479
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$296: $auto$alumacc.cc:548:replace_alu$2482
creating $alu cell for $sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$294: $auto$alumacc.cc:548:replace_alu$2485
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$293: $auto$alumacc.cc:548:replace_alu$2488
creating $alu cell for $add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$282: $auto$alumacc.cc:548:replace_alu$2491
created 24 $alu and 2 $macc cells.
7.25. Executing OPT pass (performing simple optimizations).
7.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~5 debug messages>
7.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 487 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~138 debug messages>
7.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.25.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 487 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.25.6. Executing OPT_DFF pass (perform DFF optimizations).
7.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 9 unused cells and 78 unused wires.
<suppressed ~11 debug messages>
7.25.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.25.9. Rerunning OPT passes. (Maybe there is more to do..)
7.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~138 debug messages>
7.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.25.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 477 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.25.13. Executing OPT_DFF pass (perform DFF optimizations).
7.25.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.25.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.25.16. Finished fast OPT passes. (There is nothing left to do.)
7.26. Executing MEMORY pass.
7.26.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
7.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 992 transformations.
7.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing graph_engine.u_act_buffer.mem write port 0.
Analyzing graph_engine.w_mem write port 0.
Analyzing graph_engine.w_mem write port 1.
Analyzing graph_engine.w_mem write port 2.
Analyzing graph_engine.w_mem write port 3.
Analyzing graph_engine.w_mem write port 4.
Analyzing graph_engine.w_mem write port 5.
Analyzing graph_engine.w_mem write port 6.
Analyzing graph_engine.w_mem write port 7.
Analyzing graph_engine.w_mem write port 8.
Analyzing graph_engine.w_mem write port 9.
Analyzing graph_engine.w_mem write port 10.
Analyzing graph_engine.w_mem write port 11.
Analyzing graph_engine.w_mem write port 12.
Analyzing graph_engine.w_mem write port 13.
Analyzing graph_engine.w_mem write port 14.
Analyzing graph_engine.w_mem write port 15.
Analyzing graph_engine.w_mem write port 16.
Analyzing graph_engine.w_mem write port 17.
Analyzing graph_engine.w_mem write port 18.
Analyzing graph_engine.w_mem write port 19.
Analyzing graph_engine.w_mem write port 20.
Analyzing graph_engine.w_mem write port 21.
Analyzing graph_engine.w_mem write port 22.
Analyzing graph_engine.w_mem write port 23.
Analyzing graph_engine.w_mem write port 24.
Analyzing graph_engine.w_mem write port 25.
Analyzing graph_engine.w_mem write port 26.
Analyzing graph_engine.w_mem write port 27.
Analyzing graph_engine.w_mem write port 28.
Analyzing graph_engine.w_mem write port 29.
Analyzing graph_engine.w_mem write port 30.
Analyzing graph_engine.w_mem write port 31.
Analyzing graph_engine.w_mem write port 32.
Analyzing graph_engine.x_mem write port 0.
Analyzing graph_engine.x_mem write port 1.
Analyzing graph_engine.x_mem write port 2.
Analyzing graph_engine.x_mem write port 3.
Analyzing graph_engine.x_mem write port 4.
Analyzing graph_engine.x_mem write port 5.
Analyzing graph_engine.x_mem write port 6.
Analyzing graph_engine.x_mem write port 7.
Analyzing graph_engine.x_mem write port 8.
Analyzing graph_engine.x_mem write port 9.
Analyzing graph_engine.x_mem write port 10.
Analyzing graph_engine.x_mem write port 11.
Analyzing graph_engine.x_mem write port 12.
Analyzing graph_engine.x_mem write port 13.
Analyzing graph_engine.x_mem write port 14.
Analyzing graph_engine.x_mem write port 15.
Analyzing graph_engine.x_mem write port 16.
Analyzing graph_engine.x_mem write port 17.
Analyzing graph_engine.x_mem write port 18.
Analyzing graph_engine.x_mem write port 19.
Analyzing graph_engine.x_mem write port 20.
Analyzing graph_engine.x_mem write port 21.
Analyzing graph_engine.x_mem write port 22.
Analyzing graph_engine.x_mem write port 23.
Analyzing graph_engine.x_mem write port 24.
Analyzing graph_engine.x_mem write port 25.
Analyzing graph_engine.x_mem write port 26.
Analyzing graph_engine.x_mem write port 27.
Analyzing graph_engine.x_mem write port 28.
Analyzing graph_engine.x_mem write port 29.
Analyzing graph_engine.x_mem write port 30.
Analyzing graph_engine.x_mem write port 31.
Analyzing graph_engine.x_mem write port 32.
7.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
7.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\u_act_buffer.mem'[0] in module `\graph_engine': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\w_mem'[0] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[1] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[2] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[3] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[4] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[5] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[6] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[7] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[8] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[9] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[10] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[11] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[12] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[13] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[14] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[15] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[16] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[17] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[18] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[19] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[20] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[21] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[22] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[23] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[24] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[25] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[26] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[27] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[28] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[29] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[30] in module `\graph_engine': no output FF found.
Checking read port `\w_mem'[31] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[0] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[1] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[2] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[3] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[4] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[5] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[6] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[7] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[8] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[9] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[10] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[11] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[12] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[13] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[14] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[15] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[16] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[17] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[18] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[19] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[20] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[21] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[22] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[23] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[24] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[25] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[26] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[27] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[28] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[29] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[30] in module `\graph_engine': no output FF found.
Checking read port `\x_mem'[31] in module `\graph_engine': no output FF found.
Checking read port address `\w_mem'[0] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[1] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[2] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[3] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[4] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[5] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[6] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[7] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[8] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[9] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[10] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[11] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[12] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[13] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[14] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[15] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[16] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[17] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[18] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[19] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[20] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[21] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[22] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[23] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[24] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[25] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[26] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[27] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[28] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[29] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[30] in module `\graph_engine': no address FF found.
Checking read port address `\w_mem'[31] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[0] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[1] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[2] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[3] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[4] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[5] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[6] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[7] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[8] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[9] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[10] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[11] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[12] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[13] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[14] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[15] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[16] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[17] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[18] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[19] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[20] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[21] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[22] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[23] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[24] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[25] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[26] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[27] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[28] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[29] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[30] in module `\graph_engine': no address FF found.
Checking read port address `\x_mem'[31] in module `\graph_engine': no address FF found.
7.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 1 unused cells and 9 unused wires.
<suppressed ~2 debug messages>
7.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory graph_engine.w_mem by address:
Merging ports 0, 1 (address 5'00000).
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 4 (address 5'00000).
Merging ports 0, 5 (address 5'00000).
Merging ports 0, 6 (address 5'00000).
Merging ports 0, 7 (address 5'00000).
Merging ports 0, 8 (address 5'00000).
Merging ports 0, 9 (address 5'00000).
Merging ports 0, 10 (address 5'00000).
Merging ports 0, 11 (address 5'00000).
Merging ports 0, 12 (address 5'00000).
Merging ports 0, 13 (address 5'00000).
Merging ports 0, 14 (address 5'00000).
Merging ports 0, 15 (address 5'00000).
Merging ports 0, 16 (address 5'00000).
Merging ports 18, 19 (address 5'10010).
Merging ports 20, 21 (address 5'10100).
Merging ports 20, 22 (address 5'10100).
Merging ports 20, 23 (address 5'10100).
Merging ports 24, 25 (address 5'11000).
Merging ports 24, 26 (address 5'11000).
Merging ports 24, 27 (address 5'11000).
Merging ports 24, 28 (address 5'11000).
Merging ports 24, 29 (address 5'11000).
Merging ports 24, 30 (address 5'11000).
Merging ports 24, 31 (address 5'11000).
Consolidating read ports of memory graph_engine.w_mem by address:
Merging ports 1, 2 (address 5'10001).
Merging ports 1, 3 (address 5'10000).
Merging ports 1, 4 (address 5'10000).
Consolidating read ports of memory graph_engine.w_mem by address:
Consolidating write ports of memory graph_engine.w_mem by address:
Merging ports 0, 1 (address 5'00000).
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 4 (address 5'00000).
Merging ports 0, 5 (address 5'00000).
Merging ports 0, 6 (address 5'00000).
Merging ports 0, 7 (address 5'00000).
Merging ports 0, 8 (address 5'00000).
Merging ports 0, 9 (address 5'00000).
Merging ports 0, 10 (address 5'00000).
Merging ports 0, 11 (address 5'00000).
Merging ports 0, 12 (address 5'00000).
Merging ports 0, 13 (address 5'00000).
Merging ports 0, 14 (address 5'00000).
Merging ports 0, 15 (address 5'00000).
Merging ports 0, 16 (address 5'00000).
Merging ports 18, 19 (address 5'10010).
Merging ports 20, 21 (address 5'10100).
Merging ports 20, 22 (address 5'10100).
Merging ports 20, 23 (address 5'10100).
Merging ports 24, 25 (address 5'11000).
Merging ports 24, 26 (address 5'11000).
Merging ports 24, 27 (address 5'11000).
Merging ports 24, 28 (address 5'11000).
Merging ports 24, 29 (address 5'11000).
Merging ports 24, 30 (address 5'11000).
Merging ports 24, 31 (address 5'11000).
Consolidating write ports of memory graph_engine.w_mem by address:
Merging ports 1, 2 (address 5'10001).
Merging ports 1, 3 (address 5'10000).
Merging ports 1, 4 (address 5'10000).
Consolidating write ports of memory graph_engine.w_mem by address:
Consolidating read ports of memory graph_engine.x_mem by address:
Merging ports 0, 1 (address 5'00000).
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 4 (address 5'00000).
Merging ports 0, 5 (address 5'00000).
Merging ports 0, 6 (address 5'00000).
Merging ports 0, 7 (address 5'00000).
Merging ports 0, 8 (address 5'00000).
Merging ports 0, 9 (address 5'00000).
Merging ports 0, 10 (address 5'00000).
Merging ports 0, 11 (address 5'00000).
Merging ports 0, 12 (address 5'00000).
Merging ports 0, 13 (address 5'00000).
Merging ports 0, 14 (address 5'00000).
Merging ports 0, 15 (address 5'00000).
Merging ports 0, 16 (address 5'00000).
Merging ports 18, 19 (address 5'10010).
Merging ports 20, 21 (address 5'10100).
Merging ports 20, 22 (address 5'10100).
Merging ports 20, 23 (address 5'10100).
Merging ports 24, 25 (address 5'11000).
Merging ports 24, 26 (address 5'11000).
Merging ports 24, 27 (address 5'11000).
Merging ports 24, 28 (address 5'11000).
Merging ports 24, 29 (address 5'11000).
Merging ports 24, 30 (address 5'11000).
Merging ports 24, 31 (address 5'11000).
Consolidating read ports of memory graph_engine.x_mem by address:
Merging ports 1, 2 (address 5'10001).
Merging ports 1, 3 (address 5'10000).
Merging ports 1, 4 (address 5'10000).
Consolidating read ports of memory graph_engine.x_mem by address:
Consolidating write ports of memory graph_engine.x_mem by address:
Merging ports 0, 1 (address 5'00000).
Merging ports 0, 2 (address 5'00000).
Merging ports 0, 3 (address 5'00000).
Merging ports 0, 4 (address 5'00000).
Merging ports 0, 5 (address 5'00000).
Merging ports 0, 6 (address 5'00000).
Merging ports 0, 7 (address 5'00000).
Merging ports 0, 8 (address 5'00000).
Merging ports 0, 9 (address 5'00000).
Merging ports 0, 10 (address 5'00000).
Merging ports 0, 11 (address 5'00000).
Merging ports 0, 12 (address 5'00000).
Merging ports 0, 13 (address 5'00000).
Merging ports 0, 14 (address 5'00000).
Merging ports 0, 15 (address 5'00000).
Merging ports 0, 16 (address 5'00000).
Merging ports 18, 19 (address 5'10010).
Merging ports 20, 21 (address 5'10100).
Merging ports 20, 22 (address 5'10100).
Merging ports 20, 23 (address 5'10100).
Merging ports 24, 25 (address 5'11000).
Merging ports 24, 26 (address 5'11000).
Merging ports 24, 27 (address 5'11000).
Merging ports 24, 28 (address 5'11000).
Merging ports 24, 29 (address 5'11000).
Merging ports 24, 30 (address 5'11000).
Merging ports 24, 31 (address 5'11000).
Consolidating write ports of memory graph_engine.x_mem by address:
Merging ports 1, 2 (address 5'10001).
Merging ports 1, 3 (address 5'10000).
Merging ports 1, 4 (address 5'10000).
Consolidating write ports of memory graph_engine.x_mem by address:
Consolidating write ports of memory graph_engine.w_mem using sat-based resource sharing:
Consolidating write ports of memory graph_engine.x_mem using sat-based resource sharing:
7.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
7.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 0 unused cells and 56 unused wires.
<suppressed ~1 debug messages>
7.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
7.27. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory graph_engine.w_mem
using FF mapping for memory graph_engine.x_mem
mapping memory graph_engine.u_act_buffer.mem via $__DP16KD_
<suppressed ~553 debug messages>
7.29. Executing TECHMAP pass (map to technology primitives).
7.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
7.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
Generating RTLIL representation for module `$__DP16KD_'.
Generating RTLIL representation for module `$__PDPW16KD_'.
Successfully finished Verilog frontend.
7.29.3. Continuing TECHMAP pass.
Using template $paramod$c4aea9a221b3d95ca47d9df3d018cdac65e6baac$__DP16KD_ for cells of type $__DP16KD_.
No more expansions possible.
<suppressed ~36 debug messages>
7.30. Executing OPT pass (performing simple optimizations).
7.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~190 debug messages>
7.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 331 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.30.3. Executing OPT_DFF pass (perform DFF optimizations).
Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$2700 ($dffe) from module graph_engine.
7.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 7 unused cells and 140 unused wires.
<suppressed ~8 debug messages>
7.30.5. Rerunning OPT passes. (Removed registers in this run.)
7.30.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.30.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 324 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.30.8. Executing OPT_DFF pass (perform DFF optimizations).
7.30.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.30.10. Finished fast OPT passes.
7.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory \w_mem in module \graph_engine:
created 32 $dff cells and 0 static cells of width 8.
read interface: 0 $dff and 1 $mux cells.
write interface: 96 write mux blocks.
Mapping memory \x_mem in module \graph_engine:
created 32 $dff cells and 0 static cells of width 8.
read interface: 0 $dff and 1 $mux cells.
write interface: 96 write mux blocks.
7.32. Executing OPT pass (performing simple optimizations).
7.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~207 debug messages>
7.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 631 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 599 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~96 debug messages>
Removed a total of 32 cells.
7.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~292 debug messages>
7.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
New ctrl vector for $pmux cell $procmux$1434: { $auto$opt_reduce.cc:137:opt_pmux$4013 \state [2] }
New ctrl vector for $pmux cell $procmux$1466: $auto$opt_reduce.cc:137:opt_pmux$4015
New ctrl vector for $pmux cell $procmux$1632: $auto$opt_reduce.cc:137:opt_pmux$4017
New ctrl vector for $pmux cell $procmux$1607: $auto$opt_reduce.cc:137:opt_pmux$4019
New ctrl vector for $pmux cell $procmux$1650: { $auto$opt_reduce.cc:137:opt_pmux$4023 $auto$opt_reduce.cc:137:opt_pmux$4021 }
New ctrl vector for $pmux cell $procmux$1489: $auto$opt_reduce.cc:137:opt_pmux$4025
New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$4018: { \state [10:9] \state [7] }
Optimizing cells in module \graph_engine.
Performed a total of 7 changes.
7.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 606 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 602 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.
7.32.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$ff.cc:337:slice$2105 ($sdffe) from module graph_engine (D = $procmux$1489_Y, Q = \neuron_idx).
Adding EN signal on $auto$ff.cc:337:slice$2119 ($sdffe) from module graph_engine (D = $procmux$1466_Y, Q = \desc_addr).
Adding EN signal on $auto$ff.cc:337:slice$2133 ($sdffe) from module graph_engine (D = $procmux$1434_Y, Q = \desc_byte_idx).
Adding EN signal on $auto$ff.cc:337:slice$2304 ($sdffe) from module graph_engine (D = $procmux$1650_Y, Q = \busy).
7.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 0 unused cells and 308 unused wires.
<suppressed ~1 debug messages>
7.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~5 debug messages>
7.32.9. Rerunning OPT passes. (Maybe there is more to do..)
7.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~274 debug messages>
7.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4035: { $auto$opt_dff.cc:319:make_patterns_logic$2096 $auto$opt_dff.cc:319:make_patterns_logic$2106 $auto$opt_dff.cc:319:make_patterns_logic$2110 $auto$opt_dff.cc:319:make_patterns_logic$2112 $auto$opt_dff.cc:319:make_patterns_logic$2114 $auto$opt_dff.cc:319:make_patterns_logic$4032 }
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4045: { $auto$opt_dff.cc:319:make_patterns_logic$2096 $auto$opt_dff.cc:319:make_patterns_logic$2110 $auto$opt_dff.cc:319:make_patterns_logic$2112 $auto$opt_dff.cc:319:make_patterns_logic$2114 $auto$opt_dff.cc:319:make_patterns_logic$2190 $auto$opt_dff.cc:319:make_patterns_logic$2294 $auto$opt_dff.cc:319:make_patterns_logic$2296 $auto$opt_dff.cc:319:make_patterns_logic$2298 $auto$opt_dff.cc:319:make_patterns_logic$2305 $auto$opt_dff.cc:319:make_patterns_logic$4042 }
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4040: { $auto$opt_dff.cc:319:make_patterns_logic$2098 $auto$opt_dff.cc:319:make_patterns_logic$2110 $auto$opt_dff.cc:319:make_patterns_logic$2112 $auto$opt_dff.cc:319:make_patterns_logic$2114 $auto$opt_dff.cc:319:make_patterns_logic$2134 $auto$opt_dff.cc:319:make_patterns_logic$2140 $auto$opt_dff.cc:319:make_patterns_logic$2142 $auto$opt_dff.cc:319:make_patterns_logic$2144 $auto$opt_dff.cc:319:make_patterns_logic$4037 }
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4030: { $auto$opt_dff.cc:319:make_patterns_logic$2096 $auto$opt_dff.cc:319:make_patterns_logic$2106 $auto$opt_dff.cc:319:make_patterns_logic$2110 $auto$opt_dff.cc:319:make_patterns_logic$2112 $auto$opt_dff.cc:319:make_patterns_logic$2114 $auto$opt_dff.cc:319:make_patterns_logic$4027 }
New ctrl vector for $pmux cell $procmux$1434: \state [2]
New ctrl vector for $pmux cell $procmux$1650: $auto$opt_reduce.cc:137:opt_pmux$4047
New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$4046: { \state [11] \state [9:8] \state [6] }
Optimizing cells in module \graph_engine.
Performed a total of 7 changes.
7.32.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 606 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 604 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 603 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.
7.32.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $memory\w_mem[0]$2988 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[0][2][0]$y$3088, Q = \w_mem[0]).
Adding EN signal on $memory\w_mem[1]$2990 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[1][2][0]$y$3106, Q = \w_mem[1]).
Adding EN signal on $memory\w_mem[2]$2992 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[2][2][0]$y$3124, Q = \w_mem[2]).
Adding EN signal on $memory\w_mem[3]$2994 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[3][2][0]$y$3140, Q = \w_mem[3]).
Adding EN signal on $memory\w_mem[4]$2996 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[4][2][0]$y$3158, Q = \w_mem[4]).
Adding EN signal on $memory\w_mem[5]$2998 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[5][2][0]$y$3172, Q = \w_mem[5]).
Adding EN signal on $memory\w_mem[6]$3000 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[6][2][0]$y$3186, Q = \w_mem[6]).
Adding EN signal on $memory\w_mem[7]$3002 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[7][2][0]$y$3200, Q = \w_mem[7]).
Adding EN signal on $memory\w_mem[8]$3004 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[8][2][0]$y$3220, Q = \w_mem[8]).
Adding EN signal on $memory\w_mem[9]$3006 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[9][2][0]$y$3234, Q = \w_mem[9]).
Adding EN signal on $memory\w_mem[10]$3008 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[10][2][0]$y$3248, Q = \w_mem[10]).
Adding EN signal on $memory\w_mem[11]$3010 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[11][2][0]$y$3262, Q = \w_mem[11]).
Adding EN signal on $memory\w_mem[12]$3012 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[12][2][0]$y$3278, Q = \w_mem[12]).
Adding EN signal on $memory\w_mem[13]$3014 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[13][2][0]$y$3292, Q = \w_mem[13]).
Adding EN signal on $memory\w_mem[14]$3016 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[14][2][0]$y$3306, Q = \w_mem[14]).
Adding EN signal on $memory\w_mem[15]$3018 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[15][2][0]$y$3320, Q = \w_mem[15]).
Adding EN signal on $memory\w_mem[16]$3020 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[16][2][0]$y$3342, Q = \w_mem[16]).
Adding EN signal on $memory\w_mem[17]$3022 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[17][2][0]$y$3356, Q = \w_mem[17]).
Adding EN signal on $memory\w_mem[18]$3024 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[18][2][0]$y$3370, Q = \w_mem[18]).
Adding EN signal on $memory\w_mem[19]$3026 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[19][2][0]$y$3384, Q = \w_mem[19]).
Adding EN signal on $memory\w_mem[20]$3028 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[20][2][0]$y$3400, Q = \w_mem[20]).
Adding EN signal on $memory\w_mem[21]$3030 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[21][2][0]$y$3414, Q = \w_mem[21]).
Adding EN signal on $memory\w_mem[22]$3032 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[22][2][0]$y$3428, Q = \w_mem[22]).
Adding EN signal on $memory\w_mem[23]$3034 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[23][2][0]$y$3442, Q = \w_mem[23]).
Adding EN signal on $memory\w_mem[24]$3036 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[24][2][0]$y$3460, Q = \w_mem[24]).
Adding EN signal on $memory\w_mem[25]$3038 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[25][2][0]$y$3474, Q = \w_mem[25]).
Adding EN signal on $memory\w_mem[26]$3040 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[26][2][0]$y$3488, Q = \w_mem[26]).
Adding EN signal on $memory\w_mem[27]$3042 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[27][2][0]$y$3502, Q = \w_mem[27]).
Adding EN signal on $memory\w_mem[28]$3044 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[28][2][0]$y$3518, Q = \w_mem[28]).
Adding EN signal on $memory\w_mem[29]$3046 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[29][2][0]$y$3532, Q = \w_mem[29]).
Adding EN signal on $memory\w_mem[30]$3048 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[30][2][0]$y$3546, Q = \w_mem[30]).
Adding EN signal on $memory\w_mem[31]$3050 ($dff) from module graph_engine (D = $memory\w_mem$wrmux[31][2][0]$y$3560, Q = \w_mem[31]).
Adding EN signal on $memory\x_mem[26]$3613 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[26][2][0]$y$3951, Q = \x_mem[26]).
Adding EN signal on $memory\x_mem[27]$3615 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[27][2][0]$y$3963, Q = \x_mem[27]).
Adding EN signal on $memory\x_mem[28]$3617 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[28][2][0]$y$3975, Q = \x_mem[28]).
Adding EN signal on $memory\x_mem[29]$3619 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[29][2][0]$y$3987, Q = \x_mem[29]).
Adding EN signal on $memory\x_mem[24]$3609 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[24][2][0]$y$3927, Q = \x_mem[24]).
Adding EN signal on $memory\x_mem[30]$3621 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[30][2][0]$y$3999, Q = \x_mem[30]).
Adding EN signal on $memory\x_mem[23]$3607 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[23][2][0]$y$3915, Q = \x_mem[23]).
Adding EN signal on $memory\x_mem[31]$3623 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[31][2][0]$y$4011, Q = \x_mem[31]).
Adding EN signal on $memory\x_mem[25]$3611 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[25][2][0]$y$3939, Q = \x_mem[25]).
Adding EN signal on $memory\x_mem[22]$3605 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[22][2][0]$y$3903, Q = \x_mem[22]).
Adding EN signal on $memory\x_mem[0]$3561 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[0][2][0]$y$3639, Q = \x_mem[0]).
Adding EN signal on $memory\x_mem[1]$3563 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[1][2][0]$y$3651, Q = \x_mem[1]).
Adding EN signal on $memory\x_mem[2]$3565 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[2][2][0]$y$3663, Q = \x_mem[2]).
Adding EN signal on $memory\x_mem[3]$3567 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[3][2][0]$y$3675, Q = \x_mem[3]).
Adding EN signal on $memory\x_mem[4]$3569 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[4][2][0]$y$3687, Q = \x_mem[4]).
Adding EN signal on $memory\x_mem[5]$3571 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[5][2][0]$y$3699, Q = \x_mem[5]).
Adding EN signal on $memory\x_mem[6]$3573 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[6][2][0]$y$3711, Q = \x_mem[6]).
Adding EN signal on $memory\x_mem[7]$3575 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[7][2][0]$y$3723, Q = \x_mem[7]).
Adding EN signal on $memory\x_mem[8]$3577 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[8][2][0]$y$3735, Q = \x_mem[8]).
Adding EN signal on $memory\x_mem[9]$3579 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[9][2][0]$y$3747, Q = \x_mem[9]).
Adding EN signal on $memory\x_mem[10]$3581 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[10][2][0]$y$3759, Q = \x_mem[10]).
Adding EN signal on $memory\x_mem[11]$3583 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[11][2][0]$y$3771, Q = \x_mem[11]).
Adding EN signal on $memory\x_mem[12]$3585 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[12][2][0]$y$3783, Q = \x_mem[12]).
Adding EN signal on $memory\x_mem[13]$3587 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[13][2][0]$y$3795, Q = \x_mem[13]).
Adding EN signal on $memory\x_mem[14]$3589 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[14][2][0]$y$3807, Q = \x_mem[14]).
Adding EN signal on $memory\x_mem[15]$3591 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[15][2][0]$y$3819, Q = \x_mem[15]).
Adding EN signal on $memory\x_mem[16]$3593 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[16][2][0]$y$3831, Q = \x_mem[16]).
Adding EN signal on $memory\x_mem[17]$3595 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[17][2][0]$y$3843, Q = \x_mem[17]).
Adding EN signal on $memory\x_mem[18]$3597 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[18][2][0]$y$3855, Q = \x_mem[18]).
Adding EN signal on $memory\x_mem[19]$3599 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[19][2][0]$y$3867, Q = \x_mem[19]).
Adding EN signal on $memory\x_mem[20]$3601 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[20][2][0]$y$3879, Q = \x_mem[20]).
Adding EN signal on $memory\x_mem[21]$3603 ($dff) from module graph_engine (D = $memory\x_mem$wrmux[21][2][0]$y$3891, Q = \x_mem[21]).
7.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 3 unused cells and 11 unused wires.
<suppressed ~4 debug messages>
7.32.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~128 debug messages>
7.32.16. Rerunning OPT passes. (Maybe there is more to do..)
7.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~210 debug messages>
7.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.32.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 600 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 568 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~96 debug messages>
Removed a total of 32 cells.
7.32.20. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:337:slice$4048 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[0], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4051 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[1], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4054 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[2], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4057 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[3], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4060 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[4], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4063 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[5], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4066 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[6], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4069 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[7], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4072 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[8], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4075 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[9], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4078 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[10], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4081 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[11], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4084 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[12], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4087 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[13], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4090 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[14], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4093 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[15], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4096 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[16], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4099 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[17], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4102 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[18], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4105 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[19], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4108 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[20], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4111 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[21], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4114 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[22], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4117 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[23], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4120 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[24], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4123 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[25], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4126 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[26], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4129 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[27], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4132 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[28], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4135 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[29], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4138 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[30], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4141 ($dffe) from module graph_engine (D = \weight_acc, Q = \w_mem[31], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4144 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[26], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4147 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[27], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4150 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[28], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4153 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[29], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4156 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[24], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4159 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[30], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4162 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[23], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4165 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[31], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4168 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[25], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4171 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[22], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4174 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[0], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4177 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[1], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4180 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[2], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4183 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[3], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4186 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[4], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4189 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[5], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4192 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[6], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4195 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[7], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4198 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[8], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4201 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[9], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4204 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[10], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4207 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[11], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4210 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[12], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4213 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[13], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4216 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[14], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4219 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[15], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4222 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[16], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4225 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[17], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4228 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[18], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4231 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[19], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4234 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[20], rval = 8'00000000).
Adding SRST signal on $auto$ff.cc:337:slice$4237 ($dffe) from module graph_engine (D = \u_act_buffer.rd_data, Q = \x_mem[21], rval = 8'00000000).
7.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 64 unused cells and 160 unused wires.
<suppressed ~65 debug messages>
7.32.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.32.23. Rerunning OPT passes. (Maybe there is more to do..)
7.32.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~50 debug messages>
7.32.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.32.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 504 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.32.27. Executing OPT_DFF pass (perform DFF optimizations).
7.32.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.32.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.32.30. Finished fast OPT passes. (There is nothing left to do.)
7.33. Executing TECHMAP pass (map to technology primitives).
7.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
7.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
Generating RTLIL representation for module `\_80_ccu2c_alu'.
Successfully finished Verilog frontend.
7.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu.
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $eq.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$7945baf943a7eaf2bd95deee6e66976c53d43b8d\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$7bdc7d89ea9376c9c454fd05d9b64ca6288b61c9\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$a1665ef28c749ebcdbe9aecd466e644647b56463\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$a460ba4831a5c553df03ee15bf45a690343e194f\_80_ccu2c_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using template $paramod$8fdcfe020be5e507ba05385ffd706e02b549d39d\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$ba698a254f9a5947e85cbe7beae6b161eefc5386\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$5d0bb5be5579f553e9e7790fdead1e778acc7812\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$6694d39cad831bc5688fe7ffaed39b79bdf33392\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc_v2.
add \u_neuron.acc (32 bits, signed)
add \u_neuron.u_mac8.GEN_MAC[0].u_mac.product (16 bits, signed)
add \u_neuron.u_mac8.GEN_MAC[4].u_mac.product (16 bits, signed)
add \u_neuron.u_mac8.GEN_MAC[2].u_mac.product (16 bits, signed)
add \u_neuron.u_mac8.GEN_MAC[1].u_mac.product (16 bits, signed)
add \u_neuron.u_mac8.GEN_MAC[6].u_mac.product (16 bits, signed)
add \u_neuron.u_mac8.GEN_MAC[5].u_mac.product (16 bits, signed)
add \u_neuron.u_mac8.GEN_MAC[3].u_mac.product (16 bits, signed)
add \u_neuron.u_mac8.GEN_MAC[7].u_mac.product (16 bits, signed)
add \conn_ptr_acc (23 bits, unsigned)
add \edge_byte_idx (2 bits, unsigned)
add { \conn_i 2'00 } (8 bits, unsigned)
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $pmux.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$448756c9a9dfaa49080ce4b90c6cc182883e181f\_80_ccu2c_alu for cells of type $alu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000100000 for cells of type $fa.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ccu2c_alu for cells of type $alu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
No more expansions possible.
<suppressed ~2538 debug messages>
7.34. Executing OPT pass (performing simple optimizations).
7.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~1461 debug messages>
7.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 4566 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 4308 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 4214 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 4175 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 4142 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 4111 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 4096 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 4068 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~1494 debug messages>
Removed a total of 498 cells.
7.34.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:337:slice$6598 ($_SDFF_PP0_) from module graph_engine (D = $auto$simplemap.cc:189:logic_reduce$7363, Q = \act_wr_en, rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$6402 ($_SDFF_PP0_) from module graph_engine (D = $auto$simplemap.cc:189:logic_reduce$7373, Q = \done, rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$6437 ($_SDFF_PP0_) from module graph_engine (D = $auto$simplemap.cc:189:logic_reduce$7353, Q = \ram_req, rval = 1'0).
7.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 774 unused cells and 1868 unused wires.
<suppressed ~775 debug messages>
7.34.5. Rerunning OPT passes. (Removed registers in this run.)
7.34.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.34.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 3300 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 3299 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
7.34.8. Executing OPT_DFF pass (perform DFF optimizations).
7.34.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
7.34.10. Finished fast OPT passes.
7.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
7.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 4323 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 3843 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 3363 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~2880 debug messages>
Removed a total of 960 cells.
7.38. Executing TECHMAP pass (map to technology primitives).
7.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
7.38.2. Continuing TECHMAP pass.
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
No more expansions possible.
<suppressed ~908 debug messages>
7.39. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
7.41. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in graph_engine.
7.42. Executing ATTRMVCP pass (move or copy attributes).
7.43. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 0 unused cells and 5824 unused wires.
<suppressed ~1 debug messages>
7.44. Executing CHECK pass (checking for obvious problems).
Checking module graph_engine...
Found and reported 0 problems.
7.45. Executing TECHMAP pass (map to technology primitives).
7.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
Generating RTLIL representation for module `$_DLATCH_N_'.
Generating RTLIL representation for module `$_DLATCH_P_'.
Successfully finished Verilog frontend.
7.45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
7.46. Executing ABC9 pass.
7.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
7.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
7.46.3. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module graph_engine.
Found 0 SCCs.
7.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
7.46.5. Executing TECHMAP pass (map to technology primitives).
7.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
7.46.5.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~166 debug messages>
7.46.6. Executing OPT pass (performing simple optimizations).
7.46.6.1. Executing OPT_EXPR pass (perform const folding).
7.46.6.2. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
7.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Removed 0 multiplexer ports.
7.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Performed a total of 0 changes.
7.46.6.5. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
7.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
7.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
7.46.6.8. Executing OPT_EXPR pass (perform const folding).
7.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
7.46.7. Executing TECHMAP pass (map to technology primitives).
7.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.
7.46.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~2 debug messages>
7.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.
7.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
7.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
7.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
7.46.12. Executing TECHMAP pass (map to technology primitives).
7.46.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
7.46.12.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~205 debug messages>
7.46.13. Executing OPT pass (performing simple optimizations).
7.46.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
<suppressed ~18 debug messages>
7.46.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 59 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Computing hashes of 57 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
7.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
7.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.46.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 57 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.46.13.6. Executing OPT_DFF pass (perform DFF optimizations).
7.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>
7.46.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.46.13.9. Rerunning OPT passes. (Maybe there is more to do..)
7.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \graph_engine..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
7.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \graph_engine.
Performed a total of 0 changes.
7.46.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\graph_engine'.
Computing hashes of 57 cells of `\graph_engine'.
Finding duplicate cells in `\graph_engine'.
Removed a total of 0 cells.
7.46.13.13. Executing OPT_DFF pass (perform DFF optimizations).
7.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \graph_engine..
7.46.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module graph_engine.
7.46.13.16. Finished fast OPT passes. (There is nothing left to do.)
7.46.14. Executing AIGMAP pass (map logic to AIG).
Module graph_engine: replaced 18 cells with 120 new cells, skipped 39 cells.
replaced 3 cell types:
14 $_MUX_
2 $_OR_
2 $_XOR_
not replaced 3 cell types:
4 $_AND_
4 $_NOT_
31 $specify2
7.46.15. Executing AIGMAP pass (map logic to AIG).
Module graph_engine: replaced 1476 cells with 8863 new cells, skipped 1887 cells.
replaced 4 cell types:
588 $_MUX_
32 $_ORNOT_
447 $_OR_
409 $_XOR_
not replaced 7 cell types:
658 $_AND_
194 $_NOT_
11 $scopeinfo
826 TRELLIS_FF
2 DP16KD
8 MULT18X18D
188 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
7.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9).
7.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9).
7.46.15.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 4128 AND gates and 11781 wires from module `graph_engine' to a netlist network with 1091 inputs and 526 outputs.
7.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9).
7.46.15.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 1091/ 526 and = 3643 lev = 16 (1.28) mem = 0.10 MB box = 188 bb = 0
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 2 carries.
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f -r
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 1091/ 526 and = 5429 lev = 36 (1.13) mem = 0.12 MB ch = 734 box = 188 bb = 0
ABC: cst = 0 cls = 710 lit = 734 unused = 5640 proof = 0
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 2 carries.
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
ABC: Node = 5429. Ch = 710. Total mem = 1.53 MB. Peak cut mem = 0.06 MB.
ABC: P: Del = 6297.00. Ar = 2748.0. Edge = 3688. Cut = 60510. T = 0.01 sec
ABC: P: Del = 6297.00. Ar = 2747.0. Edge = 3732. Cut = 60353. T = 0.01 sec
ABC: P: Del = 6297.00. Ar = 1869.0. Edge = 4279. Cut = 84678. T = 0.01 sec
ABC: F: Del = 6290.00. Ar = 1315.0. Edge = 3638. Cut = 72811. T = 0.01 sec
ABC: A: Del = 6290.00. Ar = 1264.0. Edge = 3472. Cut = 73071. T = 0.01 sec
ABC: A: Del = 6290.00. Ar = 1261.0. Edge = 3464. Cut = 73025. T = 0.01 sec
ABC: Total time = 0.04 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 1091/ 526 and = 4922 lev = 20 (1.11) mem = 0.12 MB box = 187 bb = 0
ABC: Mapping (K=7) : lut = 907 edge = 3305 lev = 7 (0.44) levB = 24 mem = 0.05 MB
ABC: LUT = 907 : 2=56 6.2 % 3=442 48.7 % 4=205 22.6 % 5=184 20.3 % 6=13 1.4 % 7=7 0.8 % Ave = 3.64
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &verify
ABC: Networks are equivalent. Time = 0.07 sec
ABC: + time
ABC: elapse: 1.36 seconds, total: 1.36 seconds
7.46.15.6. Executing AIGER frontend.
<suppressed ~10 debug messages>
Removed 9070 unused cells and 12790 unused wires.
7.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
ABC RESULTS: $lut cells: 908
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 187
ABC RESULTS: input signals: 42
ABC RESULTS: output signals: 142
<suppressed ~3235 debug messages>
Removing temp directory.
7.46.16. Executing TECHMAP pass (map to technology primitives).
7.46.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.
7.46.16.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
No more expansions possible.
<suppressed ~193 debug messages>
Removed 169 unused cells and 13617 unused wires.
7.47. Executing TECHMAP pass (map to technology primitives).
7.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `$lut'.
Successfully finished Verilog frontend.
7.47.2. Continuing TECHMAP pass.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut.
Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut.
Using template $paramod$59fef476587681a978a6c2236ffcd178f550d09d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101000 for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
Using template $paramod$2c64d792d702b47ae2ec0edf026efec8d740f196$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
Using template $paramod$5964dec528c7ded1ee9f528024feacf1107270a1$lut for cells of type $lut.
Using template $paramod$8848b60011977a18b53140b04a9ae7786b2920dc$lut for cells of type $lut.
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
Using template $paramod$e87c652d68339e0a13e8ac3dd39fd0a21e0079b7$lut for cells of type $lut.
Using template $paramod$68ed5daf1034523e3aaa4fed08a0ff18fc425102$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$ec562d66ce3fe8c9be3b5745c9ad809e97cb426d$lut for cells of type $lut.
Using template $paramod$fbc981964b9e152041d6fa02ad0ce22883e227ce$lut for cells of type $lut.
Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9$lut for cells of type $lut.
Using template $paramod$e0227597af2fb229e94758ce0fe325b3c5d36fdb$lut for cells of type $lut.
Using template $paramod$0a61d13e85a7ab453150d45d8c0e79af394453a9$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110010 for cells of type $lut.
Using template $paramod$ee96e0a46c5dcf44baa594c834b6b0024e57704c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001101 for cells of type $lut.
Using template $paramod$1e244711191f72131a005966a31f25745978fa0a$lut for cells of type $lut.
Using template $paramod$c459c9f8d42117424a0070526e22ab3497eb714a$lut for cells of type $lut.
Using template $paramod$b2077130d89736f5191d0d24f7f6ffd3bddb0a2d$lut for cells of type $lut.
Using template $paramod$740fbb7462c33adfde521267177818f77d620174$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$239a649c3c5dcff42e28a38401931acf401ef810$lut for cells of type $lut.
Using template $paramod$37275f9005096a8b3beded7be16e5d19f7397fa0$lut for cells of type $lut.
Using template $paramod$b8251bd6a6009b7f8717eeee6d4ce1ee764681fb$lut for cells of type $lut.
Using template $paramod$f5598bdf7d99fbb010b9ad37cfc115d5aefe2f8c$lut for cells of type $lut.
Using template $paramod$53a931967d4390280138fe919abce921b83af282$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110001 for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$69a0131df4eeb76df3ebab997a575a3385373d9a$lut for cells of type $lut.
Using template $paramod$80296eae5a3f9cd8b9da6b44f7b0f0f48957470f$lut for cells of type $lut.
Using template $paramod$9535d31217b88b856c9546ab142fa928cbabd419$lut for cells of type $lut.
Using template $paramod$041aa1dcdd60d3c4ff6eb6326c9e544a0334c607$lut for cells of type $lut.
Using template $paramod$08bef9b5ac3107e0490c4b78b8fe4edf46d39216$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$a067ca065a0e8fdac308d6893e69914865d54ec4$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$e419df0ce7a7a128a261aa0cdd389fa2f9e6a703$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut.
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut.
Using template $paramod$126c776b0f5e5eef0fff11eb6abcf95b4d1189d2$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod$1c1a90c046979b054935df6fc70ea2da9278d077$lut for cells of type $lut.
Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9$lut for cells of type $lut.
Using template $paramod$86a69f95bdbfc36792b7c7498d3544468c88bd9a$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$cf52221ef2d451442dd7d72d5c8ad598e89310e9$lut for cells of type $lut.
Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007$lut for cells of type $lut.
Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257$lut for cells of type $lut.
Using template $paramod$e2fa172d5a27e639a49367655c11079885e12f67$lut for cells of type $lut.
Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4$lut for cells of type $lut.
Using template $paramod$61af77eed7f358aa49c13132fc0b60ac3ba6c211$lut for cells of type $lut.
Using template $paramod$3fd12db03aeee29b04c450792ea328ef1bb1f18d$lut for cells of type $lut.
Using template $paramod$1bf2057bd0198df093f02a0db6737166edb9eb39$lut for cells of type $lut.
Using template $paramod$173cfa7d1d5356b77cafdb1dbf90462b77460ae7$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a$lut for cells of type $lut.
Using template $paramod$504c9f1ca6facbed70a8a05210386b24177f23fe$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5$lut for cells of type $lut.
Using template $paramod$d2b5e7b5429639878c0a614cf001753581eebd9c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut.
Using template $paramod$5c32c59025c0b98f20e63f249d83e7ebb4b085e3$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut.
Using template $paramod$a70c36ce9c272ff5b653554a904c7bf311d2f478$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut.
Using template $paramod$085ac6daadd555b0f8cf8f603c7849f876be6cbc$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut.
Using template $paramod$766f851776a2d25e13728c9147ddfe7ff70917a3$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$90da0f34d863c7d7c891a218bf58813527b1528e$lut for cells of type $lut.
Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec$lut for cells of type $lut.
Using template $paramod$6cded6c61ce853ef2739b0e8efd438c7483cfea8$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$4d74f2369e00f301e29c94e38f7ae4497c30660c$lut for cells of type $lut.
Using template $paramod$5ce0414f30742591cfbc3ba73903b522793ddcd1$lut for cells of type $lut.
Using template $paramod$ee55d4d1d1d7325f58dbdbfce0ec75c463d4291c$lut for cells of type $lut.
Using template $paramod$37f81e0845e2ea8859a016ada9b9fe63b4b71db1$lut for cells of type $lut.
Using template $paramod$f969aefcb5fdd29444244ce17e4806b1ebc6f568$lut for cells of type $lut.
Using template $paramod$ed4b624f477a67dbd878e676981471b9a7808c29$lut for cells of type $lut.
Using template $paramod$7abf0bd5a5bd3672eaba8951644e3a7f0bde69c0$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
No more expansions possible.
<suppressed ~2644 debug messages>
7.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in graph_engine.
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$3801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$3801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$3801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$3914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$3914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$3914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$4055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$4181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$4456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger$o1859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$1927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$3914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$4055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$4804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger$o1986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$2091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$2045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$32762$lut$aiger32761$2146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$2162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$32762$lut$aiger32761$3801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$32930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 2107 unused wires.
7.49. Executing AUTONAME pass.
Renamed 3937 objects in module graph_engine.
<suppressed ~3937 debug messages>
7.50. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `graph_engine'. Setting top module to graph_engine.
7.50.1. Analyzing design hierarchy..
Top module: \graph_engine
7.50.2. Analyzing design hierarchy..
Top module: \graph_engine
Removed 0 unused modules.
7.51. Printing statistics.
=== graph_engine ===
+----------Local Count, excluding submodules.
|
1668 wires
7512 wire bits
1668 public wires
7512 public wire bits
18 ports
165 port bits
21 cells
11 $scopeinfo
2 DP16KD
8 MULT18X18D
2465 submodules
187 CCU2C
34 L6MUX21
1180 LUT4
238 PFUMX
826 TRELLIS_FF
=== design hierarchy ===
+----------Count including submodules.
|
21 graph_engine
+----------Count including submodules.
|
1668 wires
7512 wire bits
1668 public wires
7512 public wire bits
18 ports
165 port bits
- memories
- memory bits
- processes
21 cells
11 $scopeinfo
2 DP16KD
8 MULT18X18D
2465 submodules
187 CCU2C
34 L6MUX21
1180 LUT4
238 PFUMX
826 TRELLIS_FF
7.52. Executing CHECK pass (checking for obvious problems).
Checking module graph_engine...
Found and reported 0 problems.
7.53. Executing JSON backend.
8. Printing statistics.
=== graph_engine ===
+----------Local Count, excluding submodules.
|
1668 wires
7512 wire bits
1668 public wires
7512 public wire bits
18 ports
165 port bits
2486 cells
11 $scopeinfo
187 CCU2C
2 DP16KD
34 L6MUX21
1180 LUT4
8 MULT18X18D
238 PFUMX
826 TRELLIS_FF
End of script. Logfile hash: 9d40e8019c, time: 2.26s, user: 0.87s, system: 0.03s, MEM: 91.33 MB peak
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
Time spent: 60% 1x abc9_exe (1 sec), 8% 25x read_verilog (0 sec), ...
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