micheleandClaude Sonnet 5
1cbe7b85d5
New hardware/v3/ (Artix-7 port, branch v3-artix7): the compute engine
that makes the 100x-vs-ESP32 target theoretically reachable on
XC7A100T's 240 DSP48E1 budget.
mac2_dsp_packed.v: packs 2 INT8 MACs sharing one resident weight into
a single DSP48-shaped 25x18 multiply, exploiting this project's own
weight-stationary reuse pattern (layer_weight_buffer.v, EXP-0057/0058)
where one weight is genuinely multiplied against many different
activations. Verified exhaustively: 16,777,216/16,777,216
(weight,x0,x1) combinations, 0 errors.
Two real bugs found and fixed during that verification (both purely
arithmetic/RTL, not toolchain-related):
1. An off-by-one in a declared wire width caused Verilog's part-select
unsigned-by-default rule to corrupt sign extension on the upper
product field -- ~50% of vectors failed.
2. After fixing (1), still ~50% failed: concatenating two independently
sign-extended fields ({sext(x1,9), sext(x0,16)}) is NOT equivalent
to the real arithmetic sum x1*2^16+x0 whenever the lower field is
negative (its own two's-complement encoding "bleeds" an extra 2^16
into the concatenated value). Fixed by building the packed operand
with an explicit arithmetic shift-and-add instead of concatenation.
neural_processor_packed.v: full port of hardware/v2/rtl/
neural_processor.v's pipeline (same stage count/structure), doubled on
the accumulator/bias/activation/saturation side to process two
weight-reuse positions per weight-tile stream. Verified against TWO
real hardware/v2/rtl/neural_processor.v instances (job A / job B, same
shared weight, independent activations) -- 18/18 PASS, 0 errors,
covering the functional sweep, INT8 extremes, and back-to-back jobs.
A third real bug found in the process (in the new testbench, not the
RTL): clearing operand_valid/tile_last in the same simulation delta as
the handshake edge that should register tile_last=1 races against the
DUTs' own FSM evaluation of that same edge -- the same pulse-clearing
race class found three times already today in hardware/v2/sim (EXP-0058
and its follow-up commits). Fixed the same way: hold the pulse past the
edge with a real time delay (#1) before clearing.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
69 lines
2.6 KiB
Verilog
69 lines
2.6 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// Exhaustive verification of mac2_dsp_packed.v's signed packing
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// arithmetic: every (weight, x0, x1) combination in [-128,127]^3
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// (256^3 = 16,777,216 vectors), checked against independent
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// Verilog integer multiplication (the "third oracle" convention
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// used throughout this project). Checks the COMBINATIONAL packed
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// result directly (no per-vector clock edge) for speed -- the
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// registered p0/p1 outputs are just a one-cycle pipeline of the
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// same combinational value, already covered structurally by every
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// other testbench in this project using this same register idiom.
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// ============================================================
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module tb;
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localparam DATA_WIDTH = 8;
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reg clk = 0;
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always #5 clk = ~clk;
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reg rst;
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reg signed [DATA_WIDTH-1:0] weight, x0, x1;
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reg valid_in;
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wire signed [2*DATA_WIDTH-1:0] p0, p1;
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wire valid_out;
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mac2_dsp_packed #(.DATA_WIDTH(DATA_WIDTH)) dut (
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.clk(clk), .rst(rst),
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.weight(weight), .x0(x0), .x1(x1), .valid_in(valid_in),
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.p0(p0), .p1(p1), .valid_out(valid_out)
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);
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integer w, a, b;
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integer tests, errors;
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integer exp0, exp1;
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initial begin
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rst = 1; weight = 0; x0 = 0; x1 = 0; valid_in = 0;
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tests = 0; errors = 0;
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@(posedge clk); @(posedge clk);
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rst = 0;
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@(posedge clk);
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for (w = -128; w <= 127; w = w + 1) begin
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weight = w[7:0];
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for (a = -128; a <= 127; a = a + 1) begin
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x0 = a[7:0];
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for (b = -128; b <= 127; b = b + 1) begin
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x1 = b[7:0];
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#1;
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tests = tests + 1;
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exp0 = a * w;
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exp1 = b * w;
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if (dut.p0_comb !== exp0[2*DATA_WIDTH-1:0] || dut.p1_comb !== exp1[2*DATA_WIDTH-1:0]) begin
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errors = errors + 1;
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if (errors <= 20)
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$display("FAIL w=%0d x0=%0d x1=%0d: got p0=%0d p1=%0d expected p0=%0d p1=%0d",
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w, a, b, $signed(dut.p0_comb), $signed(dut.p1_comb), exp0, exp1);
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end
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end
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end
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if (w % 32 == 0) $display("... progress: weight=%0d, tests so far=%0d, errors so far=%0d", w, tests, errors);
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end
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$display("=== RESULT: %0d/%0d PASS, %0d errors (exhaustive weight x x0 x x1, 256^3) ===", tests-errors, tests, errors);
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if (errors == 0) $display("ALL TESTS PASSED (tb_mac2_dsp_packed) -- exhaustive, mac2_dsp_packed.v is bit-exact");
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$finish;
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end
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endmodule
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