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FPGA-Neural/sim/memory_interface.vcd
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michele 16769eaa4b working with memory
2026-09-02 13:09:20 +02:00

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$date
Wed Sep 2 11:47:57 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module memory_interface_tb $end
$var wire 1 ! ready $end
$var wire 16 " rdata [15:0] $end
$var wire 1 # mem_wr $end
$var wire 16 $ mem_wdata [15:0] $end
$var wire 1 % mem_req $end
$var wire 1 & mem_ready $end
$var wire 16 ' mem_rdata [15:0] $end
$var wire 22 ( mem_addr [21:0] $end
$var parameter 32 ) ADDR_WIDTH $end
$var parameter 32 * DATA_WIDTH $end
$var reg 22 + addr [21:0] $end
$var reg 1 , clk $end
$var reg 1 - req $end
$var reg 1 . rst $end
$var reg 16 / wdata [15:0] $end
$var reg 1 0 wr $end
$scope module dut $end
$var wire 22 1 addr [21:0] $end
$var wire 1 , clk $end
$var wire 1 - req $end
$var wire 1 . rst $end
$var wire 16 2 wdata [15:0] $end
$var wire 1 0 wr $end
$var wire 1 & mem_ready $end
$var wire 16 3 mem_rdata [15:0] $end
$var parameter 32 4 ADDR_WIDTH $end
$var parameter 32 5 DATA_WIDTH $end
$var parameter 2 6 STATE_IDLE $end
$var parameter 2 7 STATE_WAIT $end
$var reg 22 8 mem_addr [21:0] $end
$var reg 1 % mem_req $end
$var reg 16 9 mem_wdata [15:0] $end
$var reg 1 # mem_wr $end
$var reg 16 : rdata [15:0] $end
$var reg 1 ! ready $end
$var reg 2 ; state [1:0] $end
$upscope $end
$scope module memory $end
$var wire 22 < addr [21:0] $end
$var wire 1 , clk $end
$var wire 1 % req $end
$var wire 1 . rst $end
$var wire 16 = wdata [15:0] $end
$var wire 1 # wr $end
$var parameter 32 > ADDR_WIDTH $end
$var parameter 32 ? DATA_WIDTH $end
$var parameter 32 @ DEPTH $end
$var parameter 32 A READ_LATENCY $end
$var reg 1 B busy $end
$var reg 22 C pending_addr [21:0] $end
$var reg 16 D pending_wdata [15:0] $end
$var reg 1 E pending_wr $end
$var reg 16 F rdata [15:0] $end
$var reg 1 & ready $end
$var integer 32 G delay_count [31:0] $end
$var integer 32 H i [31:0] $end
$upscope $end
$scope task read_mem $end
$var reg 22 I address [21:0] $end
$var reg 16 J expected [15:0] $end
$var reg 16 K received [15:0] $end
$upscope $end
$scope task write_mem $end
$var reg 22 L address [21:0] $end
$var reg 16 M data [15:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b10 A
b1000000000000 @
b10000 ?
b10110 >
b1 7
b0 6
b10000 5
b10110 4
b10000 *
b10110 )
$end
#0
$dumpvars
bx M
bx L
bx K
bx J
bx I
bx H
bx G
bx F
xE
bx D
bx C
xB
bx =
bx <
bx ;
bx :
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bx 8
bx 3
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b0 1
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bx '
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$end
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b1001000110100 M
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