micheleandClaude Sonnet 5
5afa6a7477
New hardware/v3/rtl/np_packed_weight_reuse_top.v: flat structural synthesis wrapper around the EXP-0062-verified module chain (real SDR SDRAM controller -> layer_prefetch_ctrl.v -> layer_weight_buffer.v -> weight_tile_gather.v -> neural_processor_packed.v). Real Vivado post-route: 8/240 DSP48E1 (unchanged, memory path uses zero DSPs), WNS -2.502ns @ 200MHz -> Fmax ~133.3MHz, only -1.2% vs the isolated single core (134.9MHz, EXP-0059). Real memory-path control logic adds negligible Fmax cost at this scale. Full writeup in hardware/v2/logs/experiments.log EXP-0063. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
15 lines
921 B
Tcl
15 lines
921 B
Tcl
read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/rtl/layer_prefetch_ctrl.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/rtl/layer_weight_buffer.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/weight_tile_gather.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/neural_processor_packed.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v2/nms/rtl/sdram_controller.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/np_packed_weight_reuse_top.v
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synth_design -top np_packed_weight_reuse_top -part xc7a100tcsg324-1 -mode out_of_context
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create_clock -name clk -period 5.000 [get_ports clk]
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opt_design
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place_design
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route_design
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report_utilization -file /tmp/util_weight_reuse_top_postroute.rpt
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report_timing_summary -file /tmp/timing_weight_reuse_top_postroute.rpt
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write_checkpoint -force /tmp/weight_reuse_top_postroute.dcp
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